1 /* 2 * File : x1000_otg_dwc.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2017-02-03 Urey the first version 23 */ 24 25 #ifndef _X1000_OTG_DWC_H_ 26 #define _X1000_OTG_DWC_H_ 27 28 /* Globle Regs define */ 29 #define GOTG_CTL (OTG_BASE + 0x00) 30 #define GOTG_INTR (OTG_BASE + 0x04) 31 #define GAHB_CFG (OTG_BASE + 0x08) 32 #define GUSB_CFG (OTG_BASE + 0x0c) 33 #define GRST_CTL (OTG_BASE + 0x10) 34 #define GINT_STS (OTG_BASE + 0x14) 35 #define GINT_MASK (OTG_BASE + 0x18) 36 #define GRXSTS_READ (OTG_BASE + 0x1c) 37 #define GRXSTS_POP (OTG_BASE + 0x20) 38 #define GRXFIFO_SIZE (OTG_BASE + 0x24) 39 #define GNPTXFIFO_SIZE (OTG_BASE + 0x28) 40 #define GDTXFIFO_SIZE (OTG_BASE + 0x104) 41 #define GHW_CFG1 (OTG_BASE + 0x44) 42 #define GHW_CFG2 (OTG_BASE + 0x48) 43 #define GHW_CFG3 (OTG_BASE + 0x4c) 44 #define GHW_CFG4 (OTG_BASE + 0x50) 45 #define GDFIFO_CFG (OTG_BASE + 0x5c) 46 #define PCGC_CTL (OTG_BASE + 0xe00) 47 48 /* Fifo number 1 ~ 15 */ 49 #define GDEIP_TXF(n) (OTG_BASE + (0x104 + ((n-1) * 0x4))) 50 51 #define REG_GOTG_CTL REG32(GOTG_CTL) 52 #define REG_GOTG_INTR REG32(GOTG_INTR) 53 #define REG_GAHB_CFG REG32(GAHB_CFG) 54 #define REG_GUSB_CFG REG32(GUSB_CFG) 55 #define REG_GRST_CTL REG32(GRST_CTL) 56 #define REG_GINT_STS REG32(GINT_STS) 57 #define REG_GINT_MASK REG32(GINT_MASK) 58 #define REG_GRXSTS_READ REG32(GRXSTS_READ) 59 #define REG_GRXSTS_POP REG32(GRXSTS_POP) 60 #define REG_GRXFIFO_SIZE REG32(GRXFIFO_SIZE) 61 #define REG_GNPTXFIFO_SIZE REG32(GNPTXFIFO_SIZE) 62 #define REG_GDTXFIFO_SIZE REG32(GDTXFIFO_SIZE) 63 #define REG_GHW_CFG1 REG32(GHW_CFG1) 64 #define REG_GHW_CFG2 REG32(GHW_CFG2) 65 #define REG_GHW_CFG3 REG32(GHW_CFG3) 66 #define REG_GHW_CFG4 REG32(GHW_CFG4) 67 #define REG_GDFIFO_CFG REG32(GDFIFO_CFG) 68 #define REG_GDIEP_TXF(n) REG32(GDEIP_TXF(n)) 69 #define REG_PCGC_CTL REG32(PCGC_CTL) 70 /* Device Regs define */ 71 #define EP_FIFO(n) (OTG_BASE + (n+1)*0x1000) // FiX ME 72 #define REG_EP_FIFO(n) REG32(EP_FIFO(n)) 73 74 75 #define OTG_DCFG (OTG_BASE + 0x800) 76 #define OTG_DCTL (OTG_BASE + 0x804) 77 #define OTG_DSTS (OTG_BASE + 0x808) 78 #define DIEP_MASK (OTG_BASE + 0x810) 79 #define DOEP_MASK (OTG_BASE + 0x814) 80 #define OTG_DAINT (OTG_BASE + 0x818) 81 #define DAINT_MASK (OTG_BASE + 0x81c) 82 83 #define DIEP_EMPMSK (OTG_BASE + 0x834) 84 85 86 /* It's used in OTG_MULT_PROC_INTRPT = 1 87 #define DEACH_INT (OTG_BASE + 0x838) 88 #define DEACH_INTMASK (OTG_BASE + 0x83c) 89 #define DIEP0_INTMASK (OTG_BASE + 0x840) 90 #define DIEP1_INTMASK (OTG_BASE + 0x844) 91 #define DOEP0_INTMASK (OTG_BASE + 0x880) 92 #define DOEP1_INTMASK (OTG_BASE + 0x884) 93 */ 94 95 #define DIEP_CTL(n) (OTG_BASE + (0x900 + (n)*0x20)) 96 #define DOEP_CTL(n) (OTG_BASE + (0xb00 + (n)*0x20)) 97 98 #define DIEP_INT(n) (OTG_BASE + (0x908 + (n)*0x20)) 99 #define DOEP_INT(n) (OTG_BASE + (0xb08 + (n)*0x20)) 100 101 #define DIEP_SIZE(n) (OTG_BASE + (0x910 + (n)*0x20)) 102 #define DOEP_SIZE(n) (OTG_BASE + (0xb10 + (n)*0x20)) 103 104 #define DIEP_TXFSTS(n) (OTG_BASE + (0x918 + (n)*0x20)) 105 106 #define DIEP_DMA(n) (OTG_BASE + (0x914 + (n)*0x20)) 107 #define DOEP_DMA(n) (OTG_BASE + (0xb14 + (n)*0x20)) 108 109 #define REG_OTG_DCFG REG32(OTG_DCFG) 110 #define REG_OTG_DCTL REG32(OTG_DCTL) 111 #define REG_OTG_DSTS REG32(OTG_DSTS) 112 #define REG_DIEP_MASK REG32(DIEP_MASK) 113 #define REG_DOEP_MASK REG32(DOEP_MASK) 114 #define REG_OTG_DAINT REG32(OTG_DAINT) 115 #define REG_DAINT_MASK REG32(DAINT_MASK) 116 #define REG_DIEP_EMPMSK REG32(DIEP_EMPMSK) 117 118 #define REG_DIEP_CTL(n) REG32(DIEP_CTL(n)) 119 #define REG_DOEP_CTL(n) REG32(DOEP_CTL(n)) 120 121 #define REG_DIEP_INT(n) REG32(DIEP_INT(n)) 122 #define REG_DOEP_INT(n) REG32(DOEP_INT(n)) 123 124 #define REG_DIEP_SIZE(n) REG32(DIEP_SIZE(n)) 125 #define REG_DOEP_SIZE(n) REG32(DOEP_SIZE(n)) 126 127 #define REG_DIEP_TXFSTS(n) REG32(DIEP_TXFSTS(n)) 128 129 #define REG_DIEP_DMA(n) REG32(DIEP_DMA(n)) 130 #define REG_DOEP_DMA(n) REG32(DOEP_DMA(n)) 131 132 /* Regs macro define */ 133 /*************************************************/ 134 #define AHBCFG_TXFE_LVL BIT7 135 #define AHBCFG_DMA_ENA BIT5 136 #define AHBCFG_GLOBLE_INTRMASK BIT0 137 #define USBCFG_FORCE_DEVICE BIT30 138 #define USBCFG_TRDTIME_MASK (0xf << 10) 139 #define USBCFG_TRDTIME_9 (9 << 10) 140 #define USBCFG_TRDTIME_6 (6 << 10) 141 142 /* GRSTCTL */ 143 #define RSTCTL_AHB_IDLE BIT31 144 #define RSTCTL_TXFNUM_ALL (0x10 << 6) 145 #define RSTCTL_TXFIFO_FLUSH BIT5 146 #define RSTCTL_RXFIFO_FLUSH BIT4 147 #define RSTCTL_INTK_FLUSH BIT3 148 #define RSTCTL_FRMCNT_RST BIT2 149 #define RSTCTL_CORE_RST BIT0 150 151 /* GINTMSK */ 152 #define GINTMSK_RSUME_DETE BIT31 153 #define GINTMSK_CONID_STSCHG BIT28 154 #define GINTMSK_RESET_DETE BIT23 155 #define GINTMSK_FETCH_SUSPEND BIT22 156 #define GINTMSK_OEP_INTR BIT19 157 #define GINTMSK_IEP_INTR BIT18 158 #define GINTMSK_EP_MISMATCH BIT17 159 #define GINTMSK_ENUM_DONE BIT13 160 #define GINTMSK_USB_RESET BIT12 161 #define GINTMSK_USB_SUSPEND BIT11 162 #define GINTMSK_USB_EARLYSUSPEND BIT10 163 #define GINTMSK_I2C_INT BIT9 164 #define GINTMSK_ULPK_CKINT BIT8 165 #define GINTMSK_GOUTNAK_EFF BIT7 166 #define GINTMSK_GINNAK_EFF BIT6 167 #define GINTMSK_NPTXFIFO_EMPTY BIT5 168 #define GINTMSK_RXFIFO_NEMPTY BIT4 169 #define GINTMSK_START_FRAM BIT3 170 #define GINTMSK_OTG_INTR BIT2 171 #define GINTMSK_MODE_MISMATCH BIT1 172 173 /* GINTSTS */ 174 #define GINTSTS_RSUME_DETE BIT31 175 #define GINTSTS_CONID_STSCHG BIT28 176 #define GINTSTS_RESET_DETE BIT23 177 #define GINTSTS_FETCH_SUSPEND BIT22 178 #define GINTSTS_OEP_INTR BIT19 179 #define GINTSTS_IEP_INTR BIT18 180 #define GINTSTS_EP_MISMATCH BIT17 181 #define GINTSTS_ENUM_DONE BIT13 182 #define GINTSTS_USB_RESET BIT12 183 #define GINTSTS_USB_SUSPEND BIT11 184 #define GINTSTS_USB_EARLYSUSPEND BIT10 185 #define GINTSTS_I2C_INT BIT9 186 #define GINTSTS_ULPK_CKINT BIT8 187 #define GINTSTS_GOUTNAK_EFF BIT7 188 #define GINTSTS_GINNAK_EFF BIT6 189 #define GINTSTS_NPTXFIFO_EMPTY BIT5 190 #define GINTSTS_RXFIFO_NEMPTY BIT4 191 #define GINTSTS_START_FRAM BIT3 192 #define GINTSTS_OTG_INTR BIT2 193 #define GINTSTS_MODE_MISMATCH BIT1 194 195 /* DCTL */ 196 #define DCTL_CGOUTNAK BIT10 197 #define DCTL_CLR_GNPINNAK BIT8 198 #define DCTL_SGNPINNAK BIT7 199 #define DCTL_SOFT_DISCONN BIT1 200 #define DCTL_SGOUTNAK BIT9 201 /* DCFG */ 202 #define DCFG_DEV_ADDR_MASK (0x7f << 4) 203 #define DCFG_DEV_ADDR_BIT 4 204 #define DCFG_DEV_DESC_DMA (1 << 23) 205 /* DSTS */ 206 #define DSTS_ERRATIC_ERROR BIT3 207 #define DSTS_ENUM_SPEED_MASK (0x3 << 1) 208 #define DSTS_ENUM_SPEED_BIT BIT1 209 #define DSTS_ENUM_SPEED_HIGH (0x0 << 1) 210 #define DSTS_ENUM_SPEED_FULL_30OR60 (0x1 << 1) 211 #define DSTS_ENUM_SPEED_LOW (0x2 << 1) 212 #define DSTS_ENUM_SPEED_FULL_48 (0x3 << 1) 213 214 /* GRXSTSR/GRXSTSP */ 215 #define GRXSTSP_PKSTS_MASK (0xf << 17) 216 #define GRXSTSP_PKSTS_GOUT_NAK (0x1 << 17) 217 #define GRXSTSP_PKSTS_GOUT_RECV (0x2 << 17) 218 #define GRXSTSP_PKSTS_TX_COMP (0x3 << 17) 219 #define GRXSTSP_PKSTS_SETUP_COMP (0x4 << 17) 220 #define GRXSTSP_PKSTS_SETUP_RECV (0x6 << 17) 221 #define GRXSTSP_BYTE_CNT_MASK (0x7ff << 4) 222 #define GRXSTSP_BYTE_CNT_BIT 4 223 #define GRXSTSP_EPNUM_MASK (0xf) 224 #define GRXSTSP_EPNUM_BIT BIT0 225 226 227 /* DIOEPCTL */ 228 // ep0 229 #define DEP_EP0_MAXPKET_SIZE 64 230 #define DEP_EP0_MPS_64 (0x0) 231 #define DEP_EP0_MPS_32 (0x1) 232 #define DEP_EP0_MPS_16 (0x2) 233 #define DEP_EP0_MPS_8 (0x3) 234 235 #define DEP_ENA_BIT BIT31 236 #define DEP_DISENA_BIT BIT30 237 #define DEP_SET_NAK BIT27 238 #define DEP_CLEAR_NAK BIT26 239 #define DEP_SET_STALL BIT21 240 #define DEP_TYPE_MASK (0x3 << 18) 241 #define DEP_TYPE_CNTL (0x0 << 18) 242 #define DEP_TYPE_ISO (0x1 << 18) 243 #define DEP_TYPE_BULK (0x2 << 18) 244 #define DEP_TYPE_INTR (0x3 << 18) 245 #define USB_ACTIVE_EP BIT15 246 #define DEP_PKTSIZE_MASK 0x7ff 247 #define DEP_FS_PKTSIZE 64 248 #define DEP_HS_PKTSIZE 512 249 250 /* DIOEPINT */ 251 #define DEP_NYET_INT BIT14 252 #define DEP_NAK_INT BIT13 253 #define DEP_BABBLE_ERR_INT BIT12 254 #define DEP_PKT_DROP_STATUS BIT11 255 #define DEP_BNA_INT BIT9 256 #define DEP_TXFIFO_UNDRN BIT8 // Only for INEP 257 #define DEP_OUTPKT_ERR BIT8 // Only for OUTEP 258 #define DEP_TXFIFO_EMPTY BIT7 259 #define DEP_INEP_NAKEFF BIT6 // Only for INEP 260 #define DEP_B2B_SETUP_RECV BIT6 // Only for OUTEP0 261 #define DEP_INTOKEN_EPMISATCH BIT5 // Only for INEP 262 #define DEP_STATUS_PHASE_RECV BIT5 // Only for OUTEP0 263 #define DEP_INTOKEN_RECV_TXFIFO_EMPTY BIT4 // Only for INEP 264 #define DEP_OUTTOKEN_RECV_EPDIS BIT4 // Only for OUTEP 265 #define DEP_TIME_OUT BIT3 // Only for INEP 266 #define DEP_SETUP_PHASE_DONE BIT3 // Only for OUTEP0 267 #define DEP_AHB_ERR BIT2 268 #define DEP_EPDIS_INT BIT1 269 #define DEP_XFER_COMP BIT0 // Used by INEP and OUTEP 270 271 /* DOEPSIZ0 */ 272 #define DOEPSIZE0_SUPCNT_1 (0x1 << 29) 273 #define DOEPSIZE0_SUPCNT_2 (0x2 << 29) 274 #define DOEPSIZE0_SUPCNT_3 (0x3 << 29) 275 #define DOEPSIZE0_PKTCNT_BIT BIT19 276 277 278 #define DEP_RXFIFO_SIZE 1064 279 #define DEP_NPTXFIFO_SIZE 1024 280 #define DEP_DTXFIFO_SIZE 768 281 282 283 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 284 #define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 285 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 286 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 287 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 288 289 #define DWC_GAHBCFG_EXT_DMA_BURST_1word 0x0 290 #define DWC_GAHBCFG_EXT_DMA_BURST_4word 0x1 291 #define DWC_GAHBCFG_EXT_DMA_BURST_8word 0x2 292 #define DWC_GAHBCFG_EXT_DMA_BURST_16word 0x3 293 #define DWC_GAHBCFG_EXT_DMA_BURST_32word 0x4 294 #define DWC_GAHBCFG_EXT_DMA_BURST_64word 0x5 295 #define DWC_GAHBCFG_EXT_DMA_BURST_128word 0x6 296 #define DWC_GAHBCFG_EXT_DMA_BURST_256word 0x7 297 298 #define DEP_NUM 2 299 300 #if 0 301 #define UTMI_PHY_WIDTH 8 302 #else 303 #define UTMI_PHY_WIDTH 16 304 #endif 305 306 #endif /* _X1000_OTG_DWC_H_ */ 307