xref: /nrf52832-nimble/rt-thread/libcpu/mips/x1000/mips_fp_gcc.S (revision 104654410c56c573564690304ae786df310c91fc)
1/*
2 * File      : mips_vfp32_asm.S
3 * This file is part of RT-Thread RTOS
4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
5 *
6 *  This program is free software; you can redistribute it and/or modify
7 *  it under the terms of the GNU General Public License as published by
8 *  the Free Software Foundation; either version 2 of the License, or
9 *  (at your option) any later version.
10 *
11 *  This program is distributed in the hope that it will be useful,
12 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14 *  GNU General Public License for more details.
15 *
16 *  You should have received a copy of the GNU General Public License along
17 *  with this program; if not, write to the Free Software Foundation, Inc.,
18 *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Change Logs:
21 * Date           Author       Notes
22 * 2016��9��9��     Urey         the first version
23 */
24
25#ifndef __ASSEMBLY__
26#	define __ASSEMBLY__
27#endif
28
29#ifdef __mips_hard_float
30
31.module hardfloat
32.module doublefloat
33.set nomips16
34
35#include "../common/mips.h"
36#undef fp
37
38	.global mips_vfp32_init
39LEAF(mips_vfp32_init)
40    mfc0 	t0, CP0_STATUS
41    or      t0 , M_StatusCU1
42    mtc0 	t0, CP0_STATUS
43    jr      ra
44    nop
45END(mips_vfp32_init)
46
47#
48# FUNCTION:	_fpctx_save
49#
50# DESCRIPTION:	save floating point registers to memory starting at a0
51#
52# RETURNS:	int
53#			0:	No context saved
54#			CTX_*:	Type of context stored
55#
56	.global _fpctx_save
57LEAF(_fpctx_save)
58	sw 		zero, LINKCTX_NEXT(a0)
59	mfc0	t0, CP0_STATUS
60	li		t1, M_StatusCU1
61	and		t1, t0, t1
62	bnez	t1, 1f
63	# FP not enabled, bail out
64	move	v0, zero
65	jr		ra
66
671:	# Save FP32 base
68	li		t1, ST0_FR
69	and		t0, t0, t1
70	cfc1	t2, $31
71	sw		t2, FP32CTX_CSR(a0)
72	sdc1	$f0, FP32CTX_0(a0)
73	sdc1	$f2, FP32CTX_2(a0)
74	sdc1	$f4, FP32CTX_4(a0)
75	sdc1	$f6, FP32CTX_6(a0)
76	sdc1	$f8, FP32CTX_8(a0)
77	sdc1	$f10, FP32CTX_10(a0)
78	sdc1	$f12, FP32CTX_12(a0)
79	sdc1	$f14, FP32CTX_14(a0)
80	sdc1	$f16, FP32CTX_16(a0)
81	sdc1	$f18, FP32CTX_18(a0)
82	sdc1	$f20, FP32CTX_20(a0)
83	sdc1	$f22, FP32CTX_22(a0)
84	sdc1	$f24, FP32CTX_24(a0)
85	sdc1	$f26, FP32CTX_26(a0)
86	sdc1	$f28, FP32CTX_28(a0)
87	sdc1	$f30, FP32CTX_30(a0)
88	bnez	t0, 2f
89	li		v0, LINKCTX_TYPE_FP32
90	sw		v0, LINKCTX_ID(a0)
91	jr		ra
92
932:	# Save FP64 extra
94.set	push
95.set	fp=64
96	sdc1	$f1, FP64CTX_1(a0)
97	sdc1	$f3, FP64CTX_3(a0)
98	sdc1	$f5, FP64CTX_5(a0)
99	sdc1	$f7, FP64CTX_7(a0)
100	sdc1	$f9, FP64CTX_9(a0)
101	sdc1	$f11, FP64CTX_11(a0)
102	sdc1	$f13, FP64CTX_13(a0)
103	sdc1	$f15, FP64CTX_15(a0)
104	sdc1	$f17, FP64CTX_17(a0)
105	sdc1	$f19, FP64CTX_19(a0)
106	sdc1	$f21, FP64CTX_21(a0)
107	sdc1	$f23, FP64CTX_23(a0)
108	sdc1	$f25, FP64CTX_25(a0)
109	sdc1	$f27, FP64CTX_27(a0)
110	sdc1	$f29, FP64CTX_29(a0)
111	sdc1	$f31, FP64CTX_31(a0)
112.set	pop
113	li	v0, LINKCTX_TYPE_FP64
114	sw	v0, LINKCTX_ID(a0)
115	jr	ra
116END(_fpctx_save)
117
118#
119# FUNCTION:	_fpctx_load
120#
121# DESCRIPTION:	load floating point registers from context chain starting at a0
122#
123# RETURNS:	int
124#			0:	Unrecognised context
125#			CTX_*:	Type of context restored
126#
127	.global _fpctx_load
128LEAF(_fpctx_load)
129	lw	v0, LINKCTX_ID(a0)
130	# Detect type
131	li	t0, LINKCTX_TYPE_FP64
132	li	t1, LINKCTX_TYPE_FP32
133	li	t2, M_StatusCU1
134	beq	v0, t0, 0f
135	beq	v0, t1, 1f
136	# Don't recognise this context, fail
137	move	v0, zero
138	jr	ra
139
1400: 	# FP64 context
141	# Enable CU1
142	di	t3
143	ehb
144	or	t3, t3, t2
145	mtc0	t3, CP0_STATUS
146	ehb
147	# Load FP64 extra
148.set	push
149.set	fp=64
150	ldc1	$f1, FP64CTX_1(a0)
151	ldc1	$f3, FP64CTX_3(a0)
152	ldc1	$f5, FP64CTX_5(a0)
153	ldc1	$f7, FP64CTX_7(a0)
154	ldc1	$f9, FP64CTX_9(a0)
155	ldc1	$f11, FP64CTX_11(a0)
156	ldc1	$f13, FP64CTX_13(a0)
157	ldc1	$f15, FP64CTX_15(a0)
158	ldc1	$f17, FP64CTX_17(a0)
159	ldc1	$f19, FP64CTX_19(a0)
160	ldc1	$f21, FP64CTX_21(a0)
161	ldc1	$f23, FP64CTX_23(a0)
162	ldc1	$f25, FP64CTX_25(a0)
163	ldc1	$f27, FP64CTX_27(a0)
164	ldc1	$f29, FP64CTX_29(a0)
165	ldc1	$f31, FP64CTX_31(a0)
166.set	pop
1671: 	# FP32 context
168	# Enable CU1
169	di	t3
170	ehb
171	or	t3, t3, t2
172	mtc0	t3, CP0_STATUS
173	ehb
174	# Load FP32 base
175	lw	t1, FP32CTX_CSR(a0)
176	ctc1	t1, $31
177	ldc1	$f0, FP32CTX_0(a0)
178	ldc1	$f2, FP32CTX_2(a0)
179	ldc1	$f4, FP32CTX_4(a0)
180	ldc1	$f6, FP32CTX_6(a0)
181	ldc1	$f8, FP32CTX_8(a0)
182	ldc1	$f10, FP32CTX_10(a0)
183	ldc1	$f12, FP32CTX_12(a0)
184	ldc1	$f14, FP32CTX_14(a0)
185	ldc1	$f16, FP32CTX_16(a0)
186	ldc1	$f18, FP32CTX_18(a0)
187	ldc1	$f20, FP32CTX_20(a0)
188	ldc1	$f22, FP32CTX_22(a0)
189	ldc1	$f24, FP32CTX_24(a0)
190	ldc1	$f26, FP32CTX_26(a0)
191	ldc1	$f28, FP32CTX_28(a0)
192	ldc1	$f30, FP32CTX_30(a0)
193	# Return CTX_FP32/64
194	jr	ra
195END(_fpctx_load)
196
197#endif
198