1/* 2 * File : mips_excpt_asm.S 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2016��9��7�� Urey the first version 23 */ 24 25#ifndef __ASSEMBLY__ 26# define __ASSEMBLY__ 27#endif 28 29#include "../common/mips.h" 30 31#define _EXC_STKSIZE 20*1024 32 33;/********************************************************************************************************* 34; PTE BASE ��ض��� 35;*********************************************************************************************************/ 36 37#define PTE_BASE_OFFSET 23 38#define PTE_BASE_SIZE 9 39#define MIPS32_BADVPN2_SHIFT 2 40 41 42 .section ".text", "ax" 43 .set noreorder 44 45LEAF(mips_tlb_refill_handlerx) 46 .set push 47 .set noat 48 .set noreorder 49 .set volatile 50 51 ;/* 52 ; * K1 = CP0_CTXT 53 ; * K0 = K1 54 ; */ 55 mfc0 k1 , CP0_CONTEXT ;/* K1 ���� Context �Ĵ��� */ 56 ehb 57 move k0 , k1 ;/* K0 ���� Context �Ĵ��� */ 58 59 ;/* 60 ; * K1 <<= PTE_BASE_SIZE 61 ; * K1 >>= PTE_BASE_SIZE 62 ; * K1 >>= 4 63 ; * K1 >>= MIPS32_BADVPN2_SHIFT 64 ; * K1 <<= 3 65 ; */ 66 sll k1 , PTE_BASE_SIZE 67 srl k1 , (PTE_BASE_SIZE + 4 + MIPS32_BADVPN2_SHIFT) ;/* K1 Ϊ BAD VPN2 */ 68 sll k1 , (4 - 1) 69 70 ;/* 71 ; * K0 >>= PTE_BASE_OFFSET 72 ; * K0 <<= PTE_BASE_OFFSET 73 ; */ 74 srl k0 , PTE_BASE_OFFSET 75 sll k0 , PTE_BASE_OFFSET ;/* K0 Ϊ PTE BASE */ 76 77 ;/* 78 ; * K1 = K1 | K0 79 ; */ 80 or k1 , k1 , k0 ;/* �ϳ� */ 81 82 ;/* 83 ; * K0 = *K1 84 ; * K1 = *(K1 + 4) 85 ; */ 86 lw k0 , 0(k1) 87 lw k1 , 4(k1) 88 89 ;/* 90 ; * CP0_TLBLO0 = K0 91 ; * CP0_TLBLO1 = K1 92 ; */ 93 mtc0 k0 , CP0_ENTRYLO0 ;/* EntryLo0 */ 94 mtc0 k1 , CP0_ENTRYLO1 ;/* EntryLo1 */ 95 ehb 96 97 tlbwr ;/* TLB ����滻 */ 98 99 eret ;/* �쳣���� */ 100 101 .set pop 102END(mips_tlb_refill_handlerx) 103