xref: /nrf52832-nimble/rt-thread/libcpu/mips/loongson_1c/mipscfg.c (revision 104654410c56c573564690304ae786df310c91fc)
1 /*
2  * File      : mipscfg.c
3  * This file is part of RT-Thread RTOS
4  * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
5  *
6  * The license and distribution terms for this file may be
7  * found in the file LICENSE in this distribution or at
8  * http://www.rt-thread.org/license/LICENSE
9  *
10  * Change Logs:
11  * Date           Author       Notes
12  * 2010-05-27     swkyer       first version
13  */
14 #include <rtthread.h>
15 #include "../common/mipsregs.h"
16 #include "../common/mipscfg.h"
17 
18 mips32_core_cfg_t g_mips_core =
19 {
20 	16,		/* icache_line_size */
21 	256,	/* icache_lines_per_way */
22 	4,		/* icache_ways */
23 	16,		/* dcache_line_size */
24 	256,	/* dcache_lines_per_way */
25 	4,		/* dcache_ways */
26 	16,		/* max_tlb_entries */
27 };
28 
m_pow(rt_uint16_t b,rt_uint16_t n)29 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
30 {
31 	rt_uint16_t rets = 1;
32 
33     while (n--)
34         rets *= b;
35 
36     return rets;
37 }
38 
m_log2(rt_uint16_t b)39 static rt_uint16_t m_log2(rt_uint16_t b)
40 {
41 	rt_uint16_t rets = 0;
42 
43     while (b != 1)
44     {
45         b /= 2;
46         rets++;
47     }
48 
49     return rets;
50 }
51 
52 /**
53  * read core attribute
54  */
mips32_cfg_init(void)55 void mips32_cfg_init(void)
56 {
57 	rt_uint16_t val;
58 	rt_uint32_t cp0_config1;
59 
60 	cp0_config1 = read_c0_config();
61 	if (cp0_config1 & 0x80000000)
62 	{
63 		cp0_config1 = read_c0_config1();
64 
65 		val = (cp0_config1 & (7<<22))>>22;
66 		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
67 		val = (cp0_config1 & (7<<19))>>19;
68 		g_mips_core.icache_line_size = 2 * m_pow(2, val);
69 		val = (cp0_config1 & (7<<16))>>16;
70 		g_mips_core.icache_ways = val + 1;
71 
72 		val = (cp0_config1 & (7<<13))>>13;
73 		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
74 		val = (cp0_config1 & (7<<10))>>10;
75 		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
76 		val = (cp0_config1 & (7<<7))>>7;
77 		g_mips_core.dcache_ways = val + 1;
78 
79 		val = (cp0_config1 & (0x3F<<25))>>25;
80 		g_mips_core.max_tlb_entries = val + 1;
81 	}
82 }
83