1 /* 2 * File : ls1b.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team 5 * 6 * The license and distribution terms for this file may be 7 * found in the file LICENSE in this distribution or at 8 * http://www.rt-thread.org/license/LICENSE 9 * 10 * Change Logs: 11 * Date Author Notes 12 * 2011-08-08 lgnq first version 13 */ 14 15 #ifndef __LS1B_H__ 16 #define __LS1B_H__ 17 18 #include "../common/mipsregs.h" 19 20 #define LS1B_ACPI_IRQ 0 21 #define LS1B_HPET_IRQ 1 22 #define LS1B_UART0_IRQ 2 23 #define LS1B_UART1_IRQ 3 24 #define LS1B_UART2_IRQ 4 25 #define LS1B_UART3_IRQ 5 26 #define LS1B_CAN0_IRQ 6 27 #define LS1B_CAN1_IRQ 7 28 #define LS1B_SPI0_IRQ 8 29 #define LS1B_SPI1_IRQ 9 30 #define LS1B_AC97_IRQ 10 31 #define LS1B_MS_IRQ 11 32 #define LS1B_KB_IRQ 12 33 #define LS1B_DMA0_IRQ 13 34 #define LS1B_DMA1_IRQ 14 35 #define LS1B_NAND_IRQ 15 36 #define LS1B_I2C0_IRQ 16 37 #define LS1B_I2C1_IRQ 17 38 #define LS1B_PWM0_IRQ 18 39 #define LS1B_PWM1_IRQ 19 40 #define LS1B_PWM2_IRQ 20 41 #define LS1B_PWM3_IRQ 21 42 #define LS1B_LPC_IRQ 22 43 #define LS1B_EHCI_IRQ 32 44 #define LS1B_OHCI_IRQ 33 45 #define LS1B_GMAC1_IRQ 34 46 #define LS1B_GMAC2_IRQ 35 47 #define LS1B_SATA_IRQ 36 48 #define LS1B_GPU_IRQ 37 49 #define LS1B_PCI_INTA_IRQ 38 50 #define LS1B_PCI_INTB_IRQ 39 51 #define LS1B_PCI_INTC_IRQ 40 52 #define LS1B_PCI_INTD_IRQ 41 53 54 #define LS1B_GPIO_IRQ 64 55 #define LS1B_GPIO_FIRST_IRQ 64 56 #define LS1B_GPIO_IRQ_COUNT 96 57 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) 58 59 #define INT_PCI_INTA (1<<6) 60 #define INT_PCI_INTB (1<<7) 61 #define INT_PCI_INTC (1<<8) 62 #define INT_PCI_INTD (1<<9) 63 64 #define LS1B_LAST_IRQ 159 65 #define MIPS_CPU_TIMER_IRQ 167 66 #define LS1B_INTREG_BASE 0xbfd01040 67 68 #define LS1B_DMA_IRQ_BASE 168 69 #define LS1B_DMA_IRQ_COUNT 16 70 71 struct ls1b_intc_regs 72 { 73 volatile unsigned int int_isr; 74 volatile unsigned int int_en; 75 volatile unsigned int int_set; 76 volatile unsigned int int_clr; /* offset 0x10*/ 77 volatile unsigned int int_pol; 78 volatile unsigned int int_edge; /* offset 0 */ 79 }; 80 81 struct ls1b_cop_global_regs 82 { 83 volatile unsigned int control; 84 volatile unsigned int rd_inten; 85 volatile unsigned int wr_inten; 86 volatile unsigned int rd_intisr; /* offset 0x10*/ 87 volatile unsigned int wr_intisr; 88 unsigned int unused[11]; 89 } ; 90 91 struct ls1b_cop_channel_regs 92 { 93 volatile unsigned int rd_control; 94 volatile unsigned int rd_src; 95 volatile unsigned int rd_cnt; 96 volatile unsigned int rd_status; /* offset 0x10*/ 97 volatile unsigned int wr_control; 98 volatile unsigned int wr_src; 99 volatile unsigned int wr_cnt; 100 volatile unsigned int wr_status; /* offset 0x10*/ 101 } ; 102 103 struct ls1b_cop_regs 104 { 105 struct ls1b_cop_global_regs global; 106 struct ls1b_cop_channel_regs chan[8][2]; 107 } ; 108 109 #define __REG8(addr) *((volatile unsigned char *)(addr)) 110 #define __REG16(addr) *((volatile unsigned short *)(addr)) 111 #define __REG32(addr) *((volatile unsigned int *)(addr)) 112 113 #define GMAC0_BASE 0xBFE10000 114 #define GMAC0_DMA_BASE 0xBFE11000 115 #define GMAC1_BASE 0xBFE20000 116 #define GMAC1_DMA_BASE 0xBFE21000 117 #define I2C0_BASE 0xBFE58000 118 #define PWM0_BASE 0xBFE5C000 119 #define PWM1_BASE 0xBFE5C010 120 #define PWM2_BASE 0xBFE5C020 121 #define PWM3_BASE 0xBFE5C030 122 #define WDT_BASE 0xBFE5C060 123 #define RTC_BASE 0xBFE64000 124 #define I2C1_BASE 0xBFE68000 125 #define I2C2_BASE 0xBFE70000 126 #define AC97_BASE 0xBFE74000 127 #define NAND_BASE 0xBFE78000 128 #define SPI_BASE 0xBFE80000 129 #define CAN1_BASE 0xBF004300 130 #define CAN0_BASE 0xBF004400 131 132 /* Watch Dog registers */ 133 #define WDT_EN __REG32(WDT_BASE + 0x00) 134 #define WDT_SET __REG32(WDT_BASE + 0x04) 135 #define WDT_TIMER __REG32(WDT_BASE + 0x08) 136 137 #define PLL_FREQ __REG32(0xbfe78030) 138 #define PLL_DIV_PARAM __REG32(0xbfe78034) 139 140 #endif 141