1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 7 * Copyright (C) 2000 Silicon Graphics, Inc. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 9 * Kevin D. Kissell, [email protected] and Carsten Langgaard, [email protected] 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 12 * 13 * Change Logs: 14 * Date Author Notes 15 * 16 */ 17 #ifndef __MIPSREGS_H__ 18 #define __MIPSREGS_H__ 19 20 /* 21 * The following macros are especially useful for __asm__ 22 * inline assembler. 23 */ 24 #ifndef __STR 25 #define __STR(x) #x 26 #endif 27 #ifndef STR 28 #define STR(x) __STR(x) 29 #endif 30 31 /* 32 * Configure language 33 */ 34 #ifdef __ASSEMBLY__ 35 #define _ULCAST_ 36 #else 37 #define _ULCAST_ (unsigned long) 38 #endif 39 40 /* 41 * Coprocessor 0 register names 42 */ 43 #define CP0_INDEX $0 44 #define CP0_RANDOM $1 45 #define CP0_ENTRYLO0 $2 46 #define CP0_ENTRYLO1 $3 47 #define CP0_CONF $3 48 #define CP0_CONTEXT $4 49 #define CP0_PAGEMASK $5 50 #define CP0_WIRED $6 51 #define CP0_INFO $7 52 #define CP0_BADVADDR $8 53 #define CP0_COUNT $9 54 #define CP0_ENTRYHI $10 55 #define CP0_COMPARE $11 56 #define CP0_STATUS $12 57 #define CP0_CAUSE $13 58 #define CP0_EPC $14 59 #define CP0_PRID $15 60 #define CP0_CONFIG $16 61 #define CP0_LLADDR $17 62 #define CP0_WATCHLO $18 63 #define CP0_WATCHHI $19 64 #define CP0_XCONTEXT $20 65 #define CP0_FRAMEMASK $21 66 #define CP0_DIAGNOSTIC $22 67 #define CP0_DEBUG $23 68 #define CP0_DEPC $24 69 #define CP0_PERFORMANCE $25 70 #define CP0_ECC $26 71 #define CP0_CACHEERR $27 72 #define CP0_TAGLO $28 73 #define CP0_TAGHI $29 74 #define CP0_ERROREPC $30 75 #define CP0_DESAVE $31 76 77 /* 78 * R4640/R4650 cp0 register names. These registers are listed 79 * here only for completeness; without MMU these CPUs are not useable 80 * by Linux. A future ELKS port might take make Linux run on them 81 * though ... 82 */ 83 #define CP0_IBASE $0 84 #define CP0_IBOUND $1 85 #define CP0_DBASE $2 86 #define CP0_DBOUND $3 87 #define CP0_CALG $17 88 #define CP0_IWATCH $18 89 #define CP0_DWATCH $19 90 91 /* 92 * Coprocessor 0 Set 1 register names 93 */ 94 #define CP0_S1_DERRADDR0 $26 95 #define CP0_S1_DERRADDR1 $27 96 #define CP0_S1_INTCONTROL $20 97 98 /* 99 * Coprocessor 0 Set 2 register names 100 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 102 103 /* 104 * Coprocessor 0 Set 3 register names 105 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 107 108 /* 109 * TX39 Series 110 */ 111 #define CP0_TX39_CACHE $7 112 113 /* 114 * Coprocessor 1 (FPU) register names 115 */ 116 #define CP1_REVISION $0 117 #define CP1_STATUS $31 118 119 /* 120 * FPU Status Register Values 121 */ 122 /* 123 * Status Register Values 124 */ 125 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 136 137 138 /* FS/FO/FN */ 139 #define FPU_CSR_FS 0x01000000 140 #define FPU_CSR_FO 0x00400000 141 #define FPU_CSR_FN 0x00200000 142 143 /* 144 * Bits 18 - 20 of the FPU Status Register will be read as 0, 145 * and should be written as zero. 146 */ 147 #define FPU_CSR_RSVD 0x001c0000 148 149 /* 150 * X the exception cause indicator 151 * E the exception enable 152 * S the sticky/flag bit 153 */ 154 #define FPU_CSR_ALL_X 0x0003f000 155 #define FPU_CSR_UNI_X 0x00020000 156 #define FPU_CSR_INV_X 0x00010000 157 #define FPU_CSR_DIV_X 0x00008000 158 #define FPU_CSR_OVF_X 0x00004000 159 #define FPU_CSR_UDF_X 0x00002000 160 #define FPU_CSR_INE_X 0x00001000 161 162 #define FPU_CSR_ALL_E 0x00000f80 163 #define FPU_CSR_INV_E 0x00000800 164 #define FPU_CSR_DIV_E 0x00000400 165 #define FPU_CSR_OVF_E 0x00000200 166 #define FPU_CSR_UDF_E 0x00000100 167 #define FPU_CSR_INE_E 0x00000080 168 169 #define FPU_CSR_ALL_S 0x0000007c 170 #define FPU_CSR_INV_S 0x00000040 171 #define FPU_CSR_DIV_S 0x00000020 172 #define FPU_CSR_OVF_S 0x00000010 173 #define FPU_CSR_UDF_S 0x00000008 174 #define FPU_CSR_INE_S 0x00000004 175 176 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 177 #define FPU_CSR_RM 0x00000003 178 #define FPU_CSR_RN 0x0 /* nearest */ 179 #define FPU_CSR_RZ 0x1 /* towards zero */ 180 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 181 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 182 183 184 /* 185 * R4x00 interrupt enable / cause bits 186 */ 187 #define IE_SW0 (_ULCAST_(1) << 8) 188 #define IE_SW1 (_ULCAST_(1) << 9) 189 #define IE_IRQ0 (_ULCAST_(1) << 10) 190 #define IE_IRQ1 (_ULCAST_(1) << 11) 191 #define IE_IRQ2 (_ULCAST_(1) << 12) 192 #define IE_IRQ3 (_ULCAST_(1) << 13) 193 #define IE_IRQ4 (_ULCAST_(1) << 14) 194 #define IE_IRQ5 (_ULCAST_(1) << 15) 195 196 /* 197 * R4x00 interrupt cause bits 198 */ 199 #define C_SW0 (_ULCAST_(1) << 8) 200 #define C_SW1 (_ULCAST_(1) << 9) 201 #define C_IRQ0 (_ULCAST_(1) << 10) 202 #define C_IRQ1 (_ULCAST_(1) << 11) 203 #define C_IRQ2 (_ULCAST_(1) << 12) 204 #define C_IRQ3 (_ULCAST_(1) << 13) 205 #define C_IRQ4 (_ULCAST_(1) << 14) 206 #define C_IRQ5 (_ULCAST_(1) << 15) 207 208 /* 209 * Bitfields in the R4xx0 cp0 status register 210 */ 211 #define ST0_IE 0x00000001 212 #define ST0_EXL 0x00000002 213 #define ST0_ERL 0x00000004 214 #define ST0_KSU 0x00000018 215 # define KSU_USER 0x00000010 216 # define KSU_SUPERVISOR 0x00000008 217 # define KSU_KERNEL 0x00000000 218 #define ST0_UX 0x00000020 219 #define ST0_SX 0x00000040 220 #define ST0_KX 0x00000080 221 #define ST0_DE 0x00010000 222 #define ST0_CE 0x00020000 223 224 /* 225 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 226 * cacheops in userspace. This bit exists only on RM7000 and RM9000 227 * processors. 228 */ 229 #define ST0_CO 0x08000000 230 231 /* 232 * Bitfields in the R[23]000 cp0 status register. 233 */ 234 #define ST0_IEC 0x00000001 235 #define ST0_KUC 0x00000002 236 #define ST0_IEP 0x00000004 237 #define ST0_KUP 0x00000008 238 #define ST0_IEO 0x00000010 239 #define ST0_KUO 0x00000020 240 /* bits 6 & 7 are reserved on R[23]000 */ 241 #define ST0_ISC 0x00010000 242 #define ST0_SWC 0x00020000 243 #define ST0_CM 0x00080000 244 245 /* 246 * Bits specific to the R4640/R4650 247 */ 248 #define ST0_UM (_ULCAST_(1) << 4) 249 #define ST0_IL (_ULCAST_(1) << 23) 250 #define ST0_DL (_ULCAST_(1) << 24) 251 252 /* 253 * Enable the MIPS DSP ASE 254 */ 255 #define ST0_MX 0x01000000 256 257 /* 258 * Bitfields in the TX39 family CP0 Configuration Register 3 259 */ 260 #define TX39_CONF_ICS_SHIFT 19 261 #define TX39_CONF_ICS_MASK 0x00380000 262 #define TX39_CONF_ICS_1KB 0x00000000 263 #define TX39_CONF_ICS_2KB 0x00080000 264 #define TX39_CONF_ICS_4KB 0x00100000 265 #define TX39_CONF_ICS_8KB 0x00180000 266 #define TX39_CONF_ICS_16KB 0x00200000 267 268 #define TX39_CONF_DCS_SHIFT 16 269 #define TX39_CONF_DCS_MASK 0x00070000 270 #define TX39_CONF_DCS_1KB 0x00000000 271 #define TX39_CONF_DCS_2KB 0x00010000 272 #define TX39_CONF_DCS_4KB 0x00020000 273 #define TX39_CONF_DCS_8KB 0x00030000 274 #define TX39_CONF_DCS_16KB 0x00040000 275 276 #define TX39_CONF_CWFON 0x00004000 277 #define TX39_CONF_WBON 0x00002000 278 #define TX39_CONF_RF_SHIFT 10 279 #define TX39_CONF_RF_MASK 0x00000c00 280 #define TX39_CONF_DOZE 0x00000200 281 #define TX39_CONF_HALT 0x00000100 282 #define TX39_CONF_LOCK 0x00000080 283 #define TX39_CONF_ICE 0x00000020 284 #define TX39_CONF_DCE 0x00000010 285 #define TX39_CONF_IRSIZE_SHIFT 2 286 #define TX39_CONF_IRSIZE_MASK 0x0000000c 287 #define TX39_CONF_DRSIZE_SHIFT 0 288 #define TX39_CONF_DRSIZE_MASK 0x00000003 289 290 /* 291 * Status register bits available in all MIPS CPUs. 292 */ 293 #define ST0_IM 0x0000ff00 294 #define STATUSB_IP0 8 295 #define STATUSF_IP0 (_ULCAST_(1) << 8) 296 #define STATUSB_IP1 9 297 #define STATUSF_IP1 (_ULCAST_(1) << 9) 298 #define STATUSB_IP2 10 299 #define STATUSF_IP2 (_ULCAST_(1) << 10) 300 #define STATUSB_IP3 11 301 #define STATUSF_IP3 (_ULCAST_(1) << 11) 302 #define STATUSB_IP4 12 303 #define STATUSF_IP4 (_ULCAST_(1) << 12) 304 #define STATUSB_IP5 13 305 #define STATUSF_IP5 (_ULCAST_(1) << 13) 306 #define STATUSB_IP6 14 307 #define STATUSF_IP6 (_ULCAST_(1) << 14) 308 #define STATUSB_IP7 15 309 #define STATUSF_IP7 (_ULCAST_(1) << 15) 310 #define STATUSB_IP8 0 311 #define STATUSF_IP8 (_ULCAST_(1) << 0) 312 #define STATUSB_IP9 1 313 #define STATUSF_IP9 (_ULCAST_(1) << 1) 314 #define STATUSB_IP10 2 315 #define STATUSF_IP10 (_ULCAST_(1) << 2) 316 #define STATUSB_IP11 3 317 #define STATUSF_IP11 (_ULCAST_(1) << 3) 318 #define STATUSB_IP12 4 319 #define STATUSF_IP12 (_ULCAST_(1) << 4) 320 #define STATUSB_IP13 5 321 #define STATUSF_IP13 (_ULCAST_(1) << 5) 322 #define STATUSB_IP14 6 323 #define STATUSF_IP14 (_ULCAST_(1) << 6) 324 #define STATUSB_IP15 7 325 #define STATUSF_IP15 (_ULCAST_(1) << 7) 326 #define ST0_CH 0x00040000 327 #define ST0_SR 0x00100000 328 #define ST0_TS 0x00200000 329 #define ST0_BEV 0x00400000 330 #define ST0_RE 0x02000000 331 #define ST0_FR 0x04000000 332 #define ST0_CU 0xf0000000 333 #define ST0_CU0 0x10000000 334 #define ST0_CU1 0x20000000 335 #define ST0_CU2 0x40000000 336 #define ST0_CU3 0x80000000 337 #define ST0_XX 0x80000000 /* MIPS IV naming */ 338 339 /* 340 * Bitfields and bit numbers in the coprocessor 0 cause register. 341 * 342 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 343 */ 344 #define CAUSEB_EXCCODE 2 345 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 346 #define CAUSEB_IP 8 347 #define CAUSEF_IP (_ULCAST_(255) << 8) 348 #define CAUSEB_IP0 8 349 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 350 #define CAUSEB_IP1 9 351 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 352 #define CAUSEB_IP2 10 353 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 354 #define CAUSEB_IP3 11 355 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 356 #define CAUSEB_IP4 12 357 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 358 #define CAUSEB_IP5 13 359 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 360 #define CAUSEB_IP6 14 361 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 362 #define CAUSEB_IP7 15 363 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 364 #define CAUSEB_IV 23 365 #define CAUSEF_IV (_ULCAST_(1) << 23) 366 #define CAUSEB_CE 28 367 #define CAUSEF_CE (_ULCAST_(3) << 28) 368 #define CAUSEB_BD 31 369 #define CAUSEF_BD (_ULCAST_(1) << 31) 370 371 /* 372 * Bits in the coprocessor 0 config register. 373 */ 374 /* Generic bits. */ 375 #define CONF_CM_CACHABLE_NO_WA 0 376 #define CONF_CM_CACHABLE_WA 1 377 #define CONF_CM_UNCACHED 2 378 #define CONF_CM_CACHABLE_NONCOHERENT 3 379 #define CONF_CM_CACHABLE_CE 4 380 #define CONF_CM_CACHABLE_COW 5 381 #define CONF_CM_CACHABLE_CUW 6 382 #define CONF_CM_CACHABLE_ACCELERATED 7 383 #define CONF_CM_CMASK 7 384 #define CONF_BE (_ULCAST_(1) << 15) 385 386 /* Bits common to various processors. */ 387 #define CONF_CU (_ULCAST_(1) << 3) 388 #define CONF_DB (_ULCAST_(1) << 4) 389 #define CONF_IB (_ULCAST_(1) << 5) 390 #define CONF_DC (_ULCAST_(7) << 6) 391 #define CONF_IC (_ULCAST_(7) << 9) 392 #define CONF_EB (_ULCAST_(1) << 13) 393 #define CONF_EM (_ULCAST_(1) << 14) 394 #define CONF_SM (_ULCAST_(1) << 16) 395 #define CONF_SC (_ULCAST_(1) << 17) 396 #define CONF_EW (_ULCAST_(3) << 18) 397 #define CONF_EP (_ULCAST_(15)<< 24) 398 #define CONF_EC (_ULCAST_(7) << 28) 399 #define CONF_CM (_ULCAST_(1) << 31) 400 401 /* Bits specific to the R4xx0. */ 402 #define R4K_CONF_SW (_ULCAST_(1) << 20) 403 #define R4K_CONF_SS (_ULCAST_(1) << 21) 404 #define R4K_CONF_SB (_ULCAST_(3) << 22) 405 406 /* Bits specific to the R5000. */ 407 #define R5K_CONF_SE (_ULCAST_(1) << 12) 408 #define R5K_CONF_SS (_ULCAST_(3) << 20) 409 410 /* Bits specific to the RM7000. */ 411 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 412 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 413 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 414 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 415 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 416 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 417 418 /* Bits specific to the R10000. */ 419 #define R10K_CONF_DN (_ULCAST_(3) << 3) 420 #define R10K_CONF_CT (_ULCAST_(1) << 5) 421 #define R10K_CONF_PE (_ULCAST_(1) << 6) 422 #define R10K_CONF_PM (_ULCAST_(3) << 7) 423 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 424 #define R10K_CONF_SB (_ULCAST_(1) << 13) 425 #define R10K_CONF_SK (_ULCAST_(1) << 14) 426 #define R10K_CONF_SS (_ULCAST_(7) << 16) 427 #define R10K_CONF_SC (_ULCAST_(7) << 19) 428 #define R10K_CONF_DC (_ULCAST_(7) << 26) 429 #define R10K_CONF_IC (_ULCAST_(7) << 29) 430 431 /* Bits specific to the VR41xx. */ 432 #define VR41_CONF_CS (_ULCAST_(1) << 12) 433 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 434 #define VR41_CONF_AD (_ULCAST_(1) << 23) 435 436 /* Bits specific to the R30xx. */ 437 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 438 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 439 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 440 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 441 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 442 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 443 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 444 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 445 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 446 447 /* Bits specific to the TX49. */ 448 #define TX49_CONF_DC (_ULCAST_(1) << 16) 449 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 450 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 451 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 452 453 /* Bits specific to the MIPS32/64 PRA. */ 454 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 455 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 456 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 457 #define MIPS_CONF_M (_ULCAST_(1) << 31) 458 459 /* 460 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 461 */ 462 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 463 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 464 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 465 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 466 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 467 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 468 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 469 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 470 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 471 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 472 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 473 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 474 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 475 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 476 477 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 478 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 479 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 480 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 481 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 482 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 483 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 484 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 485 486 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 487 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 488 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 489 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 490 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 491 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 492 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 493 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 494 495 /* 496 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 497 */ 498 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 499 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 500 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 501 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 502 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 503 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 504 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 505 506 /* 507 * R10000 performance counter definitions. 508 * 509 * FIXME: The R10000 performance counter opens a nice way to implement CPU 510 * time accounting with a precission of one cycle. I don't have 511 * R10000 silicon but just a manual, so ... 512 */ 513 514 /* 515 * Events counted by counter #0 516 */ 517 #define CE0_CYCLES 0 518 #define CE0_INSN_ISSUED 1 519 #define CE0_LPSC_ISSUED 2 520 #define CE0_S_ISSUED 3 521 #define CE0_SC_ISSUED 4 522 #define CE0_SC_FAILED 5 523 #define CE0_BRANCH_DECODED 6 524 #define CE0_QW_WB_SECONDARY 7 525 #define CE0_CORRECTED_ECC_ERRORS 8 526 #define CE0_ICACHE_MISSES 9 527 #define CE0_SCACHE_I_MISSES 10 528 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11 529 #define CE0_EXT_INTERVENTIONS_REQ 12 530 #define CE0_EXT_INVALIDATE_REQ 13 531 #define CE0_VIRTUAL_COHERENCY_COND 14 532 #define CE0_INSN_GRADUATED 15 533 534 /* 535 * Events counted by counter #1 536 */ 537 #define CE1_CYCLES 0 538 #define CE1_INSN_GRADUATED 1 539 #define CE1_LPSC_GRADUATED 2 540 #define CE1_S_GRADUATED 3 541 #define CE1_SC_GRADUATED 4 542 #define CE1_FP_INSN_GRADUATED 5 543 #define CE1_QW_WB_PRIMARY 6 544 #define CE1_TLB_REFILL 7 545 #define CE1_BRANCH_MISSPREDICTED 8 546 #define CE1_DCACHE_MISS 9 547 #define CE1_SCACHE_D_MISSES 10 548 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11 549 #define CE1_EXT_INTERVENTION_HITS 12 550 #define CE1_EXT_INVALIDATE_REQ 13 551 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 552 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 553 554 /* 555 * These flags define in which privilege mode the counters count events 556 */ 557 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ 558 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ 559 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ 560 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ 561 562 563 #ifndef __ASSEMBLY__ 564 565 /* 566 * Macros to access the system control coprocessor 567 */ 568 #define __read_32bit_c0_register(source, sel) \ 569 ({ int __res; \ 570 if (sel == 0) \ 571 __asm__ __volatile__( \ 572 "mfc0\t%0, " #source "\n\t" \ 573 : "=r" (__res)); \ 574 else \ 575 __asm__ __volatile__( \ 576 ".set\tmips32\n\t" \ 577 "mfc0\t%0, " #source ", " #sel "\n\t" \ 578 ".set\tmips0\n\t" \ 579 : "=r" (__res)); \ 580 __res; \ 581 }) 582 583 #define __write_32bit_c0_register(register, sel, value) \ 584 do { \ 585 if (sel == 0) \ 586 __asm__ __volatile__( \ 587 "mtc0\t%z0, " #register "\n\t" \ 588 : : "Jr" ((unsigned int)(value))); \ 589 else \ 590 __asm__ __volatile__( \ 591 ".set\tmips32\n\t" \ 592 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 593 ".set\tmips0" \ 594 : : "Jr" ((unsigned int)(value))); \ 595 } while (0) 596 597 #define read_c0_index() __read_32bit_c0_register($0, 0) 598 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 599 600 #define read_c0_random() __read_32bit_c0_register($1, 0) 601 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 602 603 #define read_c0_entrylo0() __read_32bit_c0_register($2, 0) 604 #define write_c0_entrylo0(val) __write_32bit_c0_register($2, 0, val) 605 606 #define read_c0_entrylo1() __read_32bit_c0_register($3, 0) 607 #define write_c0_entrylo1(val) __write_32bit_c0_register($3, 0, val) 608 609 #define read_c0_conf() __read_32bit_c0_register($3, 0) 610 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 611 612 #define read_c0_context() __read_32bit_c0_register($4, 0) 613 #define write_c0_context(val) __write_32bit_c0_register($4, 0, val) 614 615 #define read_c0_userlocal() __read_32bit_c0_register($4, 2) 616 #define write_c0_userlocal(val) __write_32bit_c0_register($4, 2, val) 617 618 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 619 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 620 621 #define read_c0_wired() __read_32bit_c0_register($6, 0) 622 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 623 624 #define read_c0_info() __read_32bit_c0_register($7, 0) 625 626 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 627 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 628 629 #define read_c0_badvaddr() __read_32bit_c0_register($8, 0) 630 #define write_c0_badvaddr(val) __write_32bit_c0_register($8, 0, val) 631 632 #define read_c0_count() __read_32bit_c0_register($9, 0) 633 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 634 635 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 636 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 637 638 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 639 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 640 641 #define read_c0_entryhi() __read_32bit_c0_register($10, 0) 642 #define write_c0_entryhi(val) __write_32bit_c0_register($10, 0, val) 643 644 #define read_c0_compare() __read_32bit_c0_register($11, 0) 645 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 646 647 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 648 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 649 650 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 651 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 652 653 #define read_c0_status() __read_32bit_c0_register($12, 0) 654 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 655 656 #define read_c0_cause() __read_32bit_c0_register($13, 0) 657 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 658 659 #define read_c0_epc() __read_32bit_c0_register($14, 0) 660 #define write_c0_epc(val) __write_32bit_c0_register($14, 0, val) 661 662 #define read_c0_prid() __read_32bit_c0_register($15, 0) 663 664 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 665 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 666 667 #define read_c0_config() __read_32bit_c0_register($16, 0) 668 #define read_c0_config1() __read_32bit_c0_register($16, 1) 669 #define read_c0_config2() __read_32bit_c0_register($16, 2) 670 #define read_c0_config3() __read_32bit_c0_register($16, 3) 671 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 672 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 673 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 674 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 675 676 677 /* 678 * Macros to access the floating point coprocessor control registers 679 */ 680 #define read_32bit_cp1_register(source) \ 681 ({ int __res; \ 682 __asm__ __volatile__( \ 683 ".set\tpush\n\t" \ 684 ".set\treorder\n\t" \ 685 /* gas fails to assemble cfc1 for some archs (octeon).*/ \ 686 ".set\tmips1\n\t" \ 687 "cfc1\t%0,"STR(source)"\n\t" \ 688 ".set\tpop" \ 689 : "=r" (__res)); \ 690 __res;}) 691 #define write_32bit_cp1_register(register, value) \ 692 do { \ 693 __asm__ __volatile__( \ 694 "ctc1\t%z0, "STR(register)"\n\t" \ 695 : : "Jr" ((unsigned int)(value))); \ 696 } while (0) 697 698 #define read_c1_status() read_32bit_cp1_register(CP1_STATUS) 699 #define read_c1_revision() read_32bit_cp1_register(CP1_REVISION); 700 #define write_c1_status(val) write_32bit_cp1_register(CP1_STATUS, val) 701 702 703 #endif /* end of __ASSEMBLY__ */ 704 705 #endif /* end of __MIPSREGS_H__ */ 706 707