1 /* 2 * File : mips_def.h 3 * This file is part of RT-Thread RTOS 4 * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Change Logs: 21 * Date Author Notes 22 * 2016��9��7�� Urey the first version 23 */ 24 25 #ifndef _COMMON_MIPS_DEF_H_ 26 #define _COMMON_MIPS_DEF_H_ 27 28 29 /* 30 ************************************************************************ 31 * I N S T R U C T I O N F O R M A T S * 32 ************************************************************************ 33 * 34 * The following definitions describe each field in an instruction. There 35 * is one diagram for each type of instruction, with field definitions 36 * following the diagram for that instruction. Note that if a field of 37 * the same name and position is defined in an earlier diagram, it is 38 * not defined again in the subsequent diagram. Only new fields are 39 * defined for each diagram. 40 * 41 * R-Type (operate) 42 * 43 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 44 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 45 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 46 * | | rs | rt | rd | sa | | 47 * | Opcode | | | Tcode | func | 48 * | | Bcode | | sel | 49 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 50 */ 51 52 #define S_InstnOpcode 26 53 #define M_InstnOpcode (0x3f << S_InstnOpcode) 54 #define S_InstnRS 21 55 #define M_InstnRS (0x1f << S_InstnRS) 56 #define S_InstnRT 16 57 #define M_InstnRT (0x1f << S_InstnRT) 58 #define S_InstnRD 11 59 #define M_InstnRD (0x1f << S_InstnRD) 60 #define S_InstnSA 6 61 #define M_InstnSA (0x1f << S_InstnSA) 62 #define S_InstnTcode 6 63 #define M_InstnTcode (0x3ff << S_InstnTcode) 64 #define S_InstnBcode 6 65 #define M_InstnBcode (0xfffff << S_InstnBcode) 66 #define S_InstnFunc 0 67 #define M_InstnFunc (0x3f << S_InstnFunc) 68 #define S_InstnSel 0 69 #define M_InstnSel (0x7 << S_InstnSel) 70 71 /* 72 * I-Type (load, store, branch, immediate) 73 * 74 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 75 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 76 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 77 * | Opcode | rs | rt | Offset | 78 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 79 */ 80 81 #define S_InstnOffset 0 82 #define M_InstnOffset (0xffff << S_InstnOffset) 83 84 /* 85 * I-Type (pref) 86 * 87 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 88 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 89 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 90 * | Opcode | rs | hint | Offset | 91 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 92 */ 93 94 #define S_InstnHint S_InstnRT 95 #define M_InstnHint M_InstnRT 96 97 /* 98 * J-Type (jump) 99 * 100 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 101 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 102 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 103 * | Opcode | JIndex | 104 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 105 */ 106 107 #define S_InstnJIndex 0 108 #define M_InstnJIndex (0x03ffffff << S_InstnJIndex) 109 110 /* 111 * FP R-Type (operate) 112 * 113 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 114 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 115 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 116 * | Opcode | fmt | ft | fs | fd | func | 117 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 118 */ 119 120 #define S_InstnFmt S_InstnRS 121 #define M_InstnFmt M_InstnRS 122 #define S_InstnFT S_InstnRT 123 #define M_InstnFT M_InstnRT 124 #define S_InstnFS S_InstnRD 125 #define M_InstnFS M_InstnRD 126 #define S_InstnFD S_InstnSA 127 #define M_InstnFD M_InstnSA 128 129 /* 130 * FP R-Type (cpu <-> cpu data movement)) 131 * 132 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 133 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 134 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 135 * | Opcode | sub | rt | fs | 0 | 136 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 137 */ 138 139 #define S_InstnSub S_InstnRS 140 #define M_InstnSub M_InstnRS 141 142 /* 143 * FP R-Type (compare) 144 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 145 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 146 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 147 * | | | | | | |C| | 148 * | Opcode | fmt | ft | fs | cc |0|A| func | 149 * | | | | | | |B| | 150 * | | | | | | |S| | 151 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 152 */ 153 154 #define S_InstnCCcmp 8 155 #define M_InstnCCcmp (0x7 << S_InstnCCcmp) 156 #define S_InstnCABS 6 157 #define M_InstnCABS (0x1 << S_InstnCABS) 158 159 /* 160 * FP R-Type (FPR conditional move on FP cc) 161 * 162 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 163 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 164 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 165 * | Opcode | fmt | cc |n|t| fs | fd | func | 166 * | | | |d|f| | | | 167 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 168 */ 169 170 #define S_InstnCC 18 171 #define M_InstnCC (0x7 << S_InstnCC) 172 #define S_InstnND 17 173 #define M_InstnND (0x1 << S_InstnND) 174 #define S_InstnTF 16 175 #define M_InstnTF (0x1 << S_InstnTF) 176 177 /* 178 * FP R-Type (3-operand operate) 179 * 180 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 181 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 182 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 183 * | Opcode | fr | ft | fs | fd | op4 | fmt3| 184 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 185 */ 186 187 #define S_InstnFR S_InstnRS 188 #define M_InstnFR M_InstnRS 189 #define S_InstnOp4 3 190 #define M_InstnOp4 (0x7 << S_InstnOp4) 191 #define S_InstnFmt3 0 192 #define M_InstnFmt3 (0x7 << S_InstnFmt3) 193 194 /* 195 * FP R-Type (Indexed load, store) 196 * 197 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 198 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 199 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 200 * | Opcode | rs | rt | 0 | fd | func | 201 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 202 */ 203 /* 204 * FP R-Type (prefx) 205 * 206 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 207 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 208 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 209 * | Opcode | rs | rt | hint | 0 | func | 210 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 211 */ 212 213 #define S_InstnHintX S_InstnRD 214 #define M_InstnHintX M_InstnRD 215 216 /* 217 * FP R-Type (GPR conditional move on FP cc) 218 * 219 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 220 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 221 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 222 * | Opcode | rs | cc |n|t| rd | 0 | func | 223 * | | | |d|f| | | | 224 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 225 */ 226 227 /* 228 * FP I-Type (load, store) 229 * 230 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 231 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 232 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 233 * | Opcode | rs | ft | Offset | 234 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 235 */ 236 237 /* 238 * FP I-Type (branch) 239 * 240 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 241 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 242 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 243 * | Opcode | fmt | cc |n|t| Offset | 244 * | | | |d|f| | 245 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 246 */ 247 248 249 /* 250 ************************************************************************* 251 * V I R T U A L A D D R E S S D E F I N I T I O N S * 252 ************************************************************************* 253 */ 254 255 #ifdef MIPSADDR64 256 #define A_K0BASE UNS64Const(0xffffffff80000000) 257 #define A_K1BASE UNS64Const(0xffffffffa0000000) 258 #define A_K2BASE UNS64Const(0xffffffffc0000000) 259 #define A_K3BASE UNS64Const(0xffffffffe0000000) 260 #define A_REGION UNS64Const(0xc000000000000000) 261 #define A_XKPHYS_ATTR UNS64Const(0x3800000000000000) 262 #else 263 #define A_K0BASE 0x80000000 264 #define A_K1BASE 0xa0000000 265 #define A_K2BASE 0xc0000000 266 #define A_K3BASE 0xe0000000 267 #endif 268 #define M_KMAPPED 0x40000000 /* KnSEG address is mapped if bit is one */ 269 270 271 #ifdef MIPS_Model64 272 273 #define S_VMAP64 62 274 #define M_VMAP64 UNS64Const(0xc000000000000000) 275 276 #define K_VMode11 3 277 #define K_VMode10 2 278 #define K_VMode01 1 279 #define K_VMode00 0 280 281 #define S_KSEG3 29 282 #define M_KSEG3 (0x7 << S_KSEG3) 283 #define K_KSEG3 7 284 285 #define S_SSEG 29 286 #define M_SSEG (0x7 << S_KSEG3) 287 #define K_SSEG 6 288 289 #define S_KSSEG 29 290 #define M_KSSEG (0x7 << S_KSEG3) 291 #define K_KSSEG 6 292 293 #define S_KSEG1 29 294 #define M_KSEG1 (0x7 << S_KSEG3) 295 #define K_KSEG1 5 296 297 #define S_KSEG0 29 298 #define M_KSEG0 (0x7 << S_KSEG3) 299 #define K_KSEG0 4 300 301 #define S_XKSEG 29 302 #define M_XKSEG (0x7 << S_KSEG3) 303 #define K_XKSEG 3 304 305 #define S_USEG 31 306 #define M_USEG (0x1 << S_USEG) 307 #define K_USEG 0 308 309 #define S_EjtagProbeMem 20 310 #define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) 311 #define K_EjtagProbeMem 0 312 313 314 315 #else 316 317 #define S_KSEG3 29 318 #define M_KSEG3 (0x7 << S_KSEG3) 319 #define K_KSEG3 7 320 321 #define S_KSSEG 29 322 #define M_KSSEG (0x7 << S_KSSEG) 323 #define K_KSSEG 6 324 325 #define S_SSEG 29 326 #define M_SSEG (0x7 << S_SSEG) 327 #define K_SSEG 6 328 329 #define S_KSEG1 29 330 #define M_KSEG1 (0x7 << S_KSEG1) 331 #define K_KSEG1 5 332 333 #define S_KSEG0 29 334 #define M_KSEG0 (0x7 << S_KSEG0) 335 #define K_KSEG0 4 336 337 #define S_KUSEG 31 338 #define M_KUSEG (0x1 << S_KUSEG) 339 #define K_KUSEG 0 340 341 #define S_SUSEG 31 342 #define M_SUSEG (0x1 << S_SUSEG) 343 #define K_SUSEG 0 344 345 #define S_USEG 31 346 #define M_USEG (0x1 << S_USEG) 347 #define K_USEG 0 348 349 #define K_EjtagLower 0xff200000 350 #define K_EjtagUpper 0xff3fffff 351 352 #define S_EjtagProbeMem 20 353 #define M_EjtagProbeMem (0x1 << S_EjtagProbeMem) 354 #define K_EjtagProbeMem 0 355 356 #endif 357 358 359 360 /* 361 ************************************************************************* 362 * C A C H E I N S T R U C T I O N O P E R A T I O N C O D E S * 363 ************************************************************************* 364 */ 365 366 /* 367 * Cache encodings 368 */ 369 #define K_CachePriI 0 /* Primary Icache */ 370 #define K_CachePriD 1 /* Primary Dcache */ 371 #define K_CachePriU 1 /* Unified primary */ 372 #define K_CacheTerU 2 /* Unified Tertiary */ 373 #define K_CacheSecU 3 /* Unified secondary */ 374 375 376 /* 377 * Function encodings 378 */ 379 #define S_CacheFunc 2 /* Amount to shift function encoding within 5-bit field */ 380 #define K_CacheIndexInv 0 /* Index invalidate */ 381 #define K_CacheIndexWBInv 0 /* Index writeback invalidate */ 382 #define K_CacheIndexLdTag 1 /* Index load tag */ 383 #define K_CacheIndexStTag 2 /* Index store tag */ 384 #define K_CacheHitInv 4 /* Hit Invalidate */ 385 #define K_CacheFill 5 /* Fill (Icache only) */ 386 #define K_CacheHitWBInv 5 /* Hit writeback invalidate */ 387 #define K_CacheHitWB 6 /* Hit writeback */ 388 #define K_CacheFetchLock 7 /* Fetch and lock */ 389 390 #define ICIndexInv ((K_CacheIndexInv << S_CacheFunc) | K_CachePriI) 391 #define DCIndexWBInv ((K_CacheIndexWBInv << S_CacheFunc) | K_CachePriD) 392 #define DCIndexInv DCIndexWBInv 393 #define ICIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriI) 394 #define DCIndexLdTag ((K_CacheIndexLdTag << S_CacheFunc) | K_CachePriD) 395 #define ICIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriI) 396 #define DCIndexStTag ((K_CacheIndexStTag << S_CacheFunc) | K_CachePriD) 397 #define ICHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriI) 398 #define DCHitInv ((K_CacheHitInv << S_CacheFunc) | K_CachePriD) 399 #define ICFill ((K_CacheFill << S_CacheFunc) | K_CachePriI) 400 #define DCHitWBInv ((K_CacheHitWBInv << S_CacheFunc) | K_CachePriD) 401 #define DCHitWB ((K_CacheHitWB << S_CacheFunc) | K_CachePriD) 402 #define ICFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriI) 403 #define DCFetchLock ((K_CacheFetchLock << S_CacheFunc) | K_CachePriD) 404 405 406 /* 407 ************************************************************************* 408 * P R E F E T C H I N S T R U C T I O N H I N T S * 409 ************************************************************************* 410 */ 411 412 #define PrefLoad 0 413 #define PrefStore 1 414 #define PrefLoadStreamed 4 415 #define PrefStoreStreamed 5 416 #define PrefLoadRetained 6 417 #define PrefStoreRetained 7 418 #define PrefWBInval 25 419 #define PrefNudge 25 420 421 422 /* 423 ************************************************************************* 424 * C P U R E G I S T E R D E F I N I T I O N S * 425 ************************************************************************* 426 */ 427 428 429 /* 430 ************************************************************************* 431 * S O F T W A R E G P R N A M E S * 432 ************************************************************************* 433 */ 434 #ifdef __ASSEMBLY__ 435 #define zero $0 436 #define AT $1 437 #define v0 $2 438 #define v1 $3 439 #define a0 $4 440 #define a1 $5 441 #define a2 $6 442 #define a3 $7 443 #define t0 $8 444 #define t1 $9 445 #define t2 $10 446 #define t3 $11 447 #define t4 $12 448 #define t5 $13 449 #define t6 $14 450 #define t7 $15 451 #define s0 $16 452 #define s1 $17 453 #define s2 $18 454 #define s3 $19 455 #define s4 $20 456 #define s5 $21 457 #define s6 $22 458 #define s7 $23 459 #define t8 $24 460 #define t9 $25 461 #define k0 $26 462 #define k1 $27 463 #define gp $28 464 #define sp $29 465 #define fp $30 466 #define ra $31 467 468 /* 469 * The following registers are used by the AVP environment and 470 * are not part of the normal software definitions. 471 */ 472 473 #ifdef MIPSAVPENV 474 #define repc $25 /* Expected exception PC */ 475 #define tid $30 /* Current test case address */ 476 #endif 477 478 479 /* 480 ************************************************************************* 481 * H A R D W A R E G P R N A M E S * 482 ************************************************************************* 483 * 484 * In the AVP environment, several of the `r' names are removed from the 485 * name space because they are used by the kernel for special purposes. 486 * Removing them causes assembly rather than runtime errors for tests that 487 * use the `r' names. 488 * 489 * - r25 (repc) is used as the expected PC on an exception 490 * - r26-r27 (k0, k1) are used in the exception handler 491 * - r30 (tid) is used as the current test address 492 */ 493 494 #define r0 $0 495 #define r1 $1 496 #define r2 $2 497 #define r3 $3 498 #define r4 $4 499 #define r5 $5 500 #define r6 $6 501 #define r7 $7 502 #define r8 $8 503 #define r9 $9 504 #define r10 $10 505 #define r11 $11 506 #define r12 $12 507 #define r13 $13 508 #define r14 $14 509 #define r15 $15 510 #define r16 $16 511 #define r17 $17 512 #define r18 $18 513 #define r19 $19 514 #define r20 $20 515 #define r21 $21 516 #define r22 $22 517 #define r23 $23 518 #define r24 $24 519 #ifdef MIPSAVPENV 520 #define r25 r25_unknown 521 #define r26 r26_unknown 522 #define r27 r27_unknown 523 #else 524 #define r25 $25 525 #define r26 $26 526 #define r27 $27 527 #endif 528 #define r28 $28 529 #define r29 $29 530 #ifdef MIPSAVPENV 531 #define r30 r30_unknown 532 #else 533 #define r30 $30 534 #endif 535 #define r31 $31 536 537 #endif 538 539 /* 540 ************************************************************************* 541 * H A R D W A R E G P R I N D I C E S * 542 ************************************************************************* 543 * 544 * These definitions provide the index (number) of the GPR, as opposed 545 * to the assembler register name ($n). 546 */ 547 548 #define R_r0 0 549 #define R_r1 1 550 #define R_r2 2 551 #define R_r3 3 552 #define R_r4 4 553 #define R_r5 5 554 #define R_r6 6 555 #define R_r7 7 556 #define R_r8 8 557 #define R_r9 9 558 #define R_r10 10 559 #define R_r11 11 560 #define R_r12 12 561 #define R_r13 13 562 #define R_r14 14 563 #define R_r15 15 564 #define R_r16 16 565 #define R_r17 17 566 #define R_r18 18 567 #define R_r19 19 568 #define R_r20 20 569 #define R_r21 21 570 #define R_r22 22 571 #define R_r23 23 572 #define R_r24 24 573 #define R_r25 25 574 #define R_r26 26 575 #define R_r27 27 576 #define R_r28 28 577 #define R_r29 29 578 #define R_r30 30 579 #define R_r31 31 580 #define R_hi 32 /* Hi register */ 581 #define R_lo 33 /* Lo register */ 582 583 584 /* 585 ************************************************************************* 586 * S O F T W A R E G P R M A S K S * 587 ************************************************************************* 588 * 589 * These definitions provide the bit mask corresponding to the GPR number 590 */ 591 592 #define M_AT (1<<1) 593 #define M_v0 (1<<2) 594 #define M_v1 (1<<3) 595 #define M_a0 (1<<4) 596 #define M_a1 (1<<5) 597 #define M_a2 (1<<6) 598 #define M_a3 (1<<7) 599 #define M_t0 (1<<8) 600 #define M_t1 (1<<9) 601 #define M_t2 (1<<10) 602 #define M_t3 (1<<11) 603 #define M_t4 (1<<12) 604 #define M_t5 (1<<13) 605 #define M_t6 (1<<14) 606 #define M_t7 (1<<15) 607 #define M_s0 (1<<16) 608 #define M_s1 (1<<17) 609 #define M_s2 (1<<18) 610 #define M_s3 (1<<19) 611 #define M_s4 (1<<20) 612 #define M_s5 (1<<21) 613 #define M_s6 (1<<22) 614 #define M_s7 (1<<23) 615 #define M_t8 (1<<24) 616 #define M_t9 (1<<25) 617 #define M_k0 (1<<26) 618 #define M_k1 (1<<27) 619 #define M_gp (1<<28) 620 #define M_sp (1<<29) 621 #define M_fp (1<<30) 622 #define M_ra (1<<31) 623 624 625 /* 626 ************************************************************************* 627 * C P 0 R E G I S T E R D E F I N I T I O N S * 628 ************************************************************************* 629 * Each register has the following definitions: 630 * 631 * C0_rrr The register number (as a $n value) 632 * R_C0_rrr The register index (as an integer corresponding 633 * to the register number) 634 * 635 * Each field in a register has the following definitions: 636 * 637 * S_rrrfff The shift count required to right-justify 638 * the field. This corresponds to the bit 639 * number of the right-most bit in the field. 640 * M_rrrfff The Mask required to isolate the field. 641 * 642 * Register diagrams included below as comments correspond to the 643 * MIPS32 and MIPS64 architecture specifications. Refer to other 644 * sources for register diagrams for older architectures. 645 */ 646 647 648 /* 649 ************************************************************************ 650 * I N D E X R E G I S T E R ( 0 ) * 651 ************************************************************************ 652 * 653 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 654 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 655 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 656 * |P| 0 | Index | Index 657 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 658 */ 659 660 #define C0_Index $0 661 #define R_C0_Index 0 662 #define C0_INX C0_Index /* OBSOLETE - DO NOT USE IN NEW CODE */ 663 664 #define S_IndexP 31 /* Probe failure (R)*/ 665 #define M_IndexP (0x1 << S_IndexP) 666 667 #define S_IndexIndex 0 /* TLB index (R/W)*/ 668 #define M_IndexIndex (0x3f << S_IndexIndex) 669 670 #define M_Index0Fields 0x7fffffc0 671 #define M_IndexRFields 0x80000000 672 673 674 /* 675 ************************************************************************ 676 * R A N D O M R E G I S T E R ( 1 ) * 677 ************************************************************************ 678 * 679 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 680 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 681 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 682 * | 0 | Index | Random 683 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 684 */ 685 686 #define C0_Random $1 687 #define R_C0_Random 1 688 #define C0_RAND $1 /* OBSOLETE - DO NOT USE IN NEW CODE */ 689 690 #define S_RandomIndex 0 /* TLB random index (R)*/ 691 #define M_RandomIndex (0x3f << S_RandomIndex) 692 693 #define M_Random0Fields 0xffffffc0 694 #define M_RandomRFields 0x0000003f 695 696 697 /* 698 ************************************************************************ 699 * E N T R Y L O 0 R E G I S T E R ( 2 ) * 700 ************************************************************************ 701 * 702 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 703 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 704 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 705 * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo0 706 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 707 */ 708 709 #define C0_EntryLo0 $2 710 #define R_C0_EntryLo0 2 711 #define C0_TLBLO_0 C0_EntryLo0 /* OBSOLETE - DO NOT USE IN NEW CODE */ 712 713 #define S_EntryLoPFN 6 /* PFN (R/W) */ 714 #define M_EntryLoPFN (0xffffff << S_EntryLoPFN) 715 #define S_EntryLoC 3 /* Coherency attribute (R/W) */ 716 #define M_EntryLoC (0x7 << S_EntryLoC) 717 #define S_EntryLoD 2 /* Dirty (R/W) */ 718 #define M_EntryLoD (0x1 << S_EntryLoD) 719 #define S_EntryLoV 1 /* Valid (R/W) */ 720 #define M_EntryLoV (0x1 << S_EntryLoV) 721 #define S_EntryLoG 0 /* Global (R/W) */ 722 #define M_EntryLoG (0x1 << S_EntryLoG) 723 #define M_EntryLoOddPFN (0x1 << S_EntryLoPFN) /* Odd PFN bit */ 724 #define S_EntryLo_RS K_PageAlign /* Right-justify PFN */ 725 #define S_EntryLo_LS S_EntryLoPFN /* Position PFN to appropriate position */ 726 727 #define M_EntryLo0Fields 0x00000000 728 #define M_EntryLoRFields 0xc0000000 729 #define M_EntryLo0Fields64 UNS64Const(0x0000000000000000) 730 #define M_EntryLoRFields64 UNS64Const(0xffffffffc0000000) 731 732 /* 733 * Cache attribute values in the C field of EntryLo and the 734 * K0 field of Config 735 */ 736 #define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */ 737 #define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */ 738 #define K_CacheAttrU 2 /* Uncached */ 739 #define K_CacheAttrC 3 /* Cacheable */ 740 #define K_CacheAttrCN 3 /* Cacheable, non-coherent */ 741 #define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */ 742 #define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */ 743 #define K_CacheAttrCCU 6 /* Cacheable, coherent, update */ 744 #define K_CacheAttrUA 7 /* Uncached accelerated */ 745 746 747 /* 748 ************************************************************************ 749 * E N T R Y L O 1 R E G I S T E R ( 3 ) * 750 ************************************************************************ 751 * 752 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 753 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 754 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 755 * | Fill (0) //| 0 | PFN | C |D|V|G| EntryLo1 756 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 757 */ 758 759 #define C0_EntryLo1 $3 760 #define R_C0_EntryLo1 3 761 #define C0_TLBLO_1 C0_EntryLo1 /* OBSOLETE - DO NOT USE IN NEW CODE */ 762 763 /* 764 * Field definitions are as given for EntryLo0 above 765 */ 766 767 768 /* 769 ************************************************************************ 770 * C O N T E X T R E G I S T E R ( 4 ) * 771 ************************************************************************ 772 * 773 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 774 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 775 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 776 * | // PTEBase | BadVPN<31:13> | 0 | Context 777 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 778 */ 779 780 #define C0_Context $4 781 #define R_C0_Context 4 782 #define C0_CTXT C0_Context /* OBSOLETE - DO NOT USE IN NEW CODE */ 783 784 #define S_ContextPTEBase 23 /* PTE base (R/W) */ 785 #define M_ContextPTEBase (0x1ff << S_ContextPTEBase) 786 #define S_ContextBadVPN 4 /* BadVPN2 (R) */ 787 #define M_ContextBadVPN (0x7ffff << S_ContextBadVPN) 788 #define S_ContextBadVPN_LS 9 /* Position BadVPN to bit 31 */ 789 #define S_ContextBadVPN_RS 13 /* Right-justify shifted BadVPN field */ 790 791 #define M_Context0Fields 0x0000000f 792 #define M_ContextRFields 0x007ffff0 793 #define M_Context0Fields64 UNS64Const(0x000000000000000f) 794 #define M_ContextRFields64 UNS64Const(0x00000000007ffff0) 795 796 797 /* 798 ************************************************************************ 799 * P A G E M A S K R E G I S T E R ( 5 ) * 800 ************************************************************************ 801 * 802 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 803 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 804 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 805 * | 0 | Mask | 0 | PageMask 806 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 807 */ 808 809 #define C0_PageMask $5 810 #define R_C0_PageMask 5 /* Mask (R/W) */ 811 #define C0_PGMASK C0_PageMask /* OBSOLETE - DO NOT USE IN NEW CODE */ 812 813 #define S_PageMaskMask 13 814 #define M_PageMaskMask (0xfff << S_PageMaskMask) 815 816 #define M_PageMask0Fields 0xfe001fff 817 #define M_PageMaskRFields 0x00000000 818 819 /* 820 * Values in the Mask field 821 */ 822 #define K_PageMask4K 0x000 /* K_PageMasknn values are values for use */ 823 #define K_PageMask16K 0x003 /* with KReqPageAttributes or KReqPageMask macros */ 824 #define K_PageMask64K 0x00f 825 #define K_PageMask256K 0x03f 826 #define K_PageMask1M 0x0ff 827 #define K_PageMask4M 0x3ff 828 #define K_PageMask16M 0xfff 829 830 #define M_PageMask4K (K_PageMask4K << S_PageMaskMask) /* M_PageMasknn values are masks */ 831 #define M_PageMask16K (K_PageMask16K << S_PageMaskMask) /* in position in the PageMask register */ 832 #define M_PageMask64K (K_PageMask64K << S_PageMaskMask) 833 #define M_PageMask256K (K_PageMask256K << S_PageMaskMask) 834 #define M_PageMask1M (K_PageMask1M << S_PageMaskMask) 835 #define M_PageMask4M (K_PageMask4M << S_PageMaskMask) 836 #define M_PageMask16M (K_PageMask16M << S_PageMaskMask) 837 838 839 /* 840 ************************************************************************ 841 * W I R E D R E G I S T E R ( 6 ) * 842 ************************************************************************ 843 * 844 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 845 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 846 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 847 * | 0 | Index | Wired 848 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 849 */ 850 851 #define C0_Wired $6 852 #define R_C0_Wired 6 853 #define C0_TLBWIRED C0_Wired /* OBSOLETE - DO NOT USE IN NEW CODE */ 854 855 #define S_WiredIndex 0 /* TLB wired boundary (R/W) */ 856 #define M_WiredIndex (0x3f << S_WiredIndex) 857 858 #define M_Wired0Fields 0xffffffc0 859 #define M_WiredRFields 0x00000000 860 861 862 /* 863 ************************************************************************ 864 * B A D V A D D R R E G I S T E R ( 8 ) * 865 ************************************************************************ 866 * 867 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 868 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 869 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 870 * | // Bad Virtual Address | BadVAddr 871 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 872 */ 873 874 #define C0_BadVAddr $8 875 #define R_C0_BadVAddr 8 876 #define C0_BADVADDR C0_BadVAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ 877 878 #define M_BadVAddrOddPage K_PageSize /* Even/Odd VA bit for pair of PAs */ 879 880 #define M_BadVAddr0Fields 0x00000000 881 #define M_BadVAddrRFields 0xffffffff 882 #define M_BadVAddr0Fields64 UNS64Const(0x0000000000000000) 883 #define M_BadVAddrRFields64 UNS64Const(0xffffffffffffffff) 884 885 /* 886 ************************************************************************ 887 * C O U N T R E G I S T E R ( 9 ) * 888 ************************************************************************ 889 * 890 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 891 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 892 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 893 * | Count Value | Count 894 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 895 */ 896 897 #define C0_Count $9 898 #define R_C0_Count 9 899 #define C0_COUNT C0_Count /* OBSOLETE - DO NOT USE IN NEW CODE */ 900 901 #define M_Count0Fields 0x00000000 902 #define M_CountRFields 0x00000000 903 904 905 /* 906 ************************************************************************ 907 * E N T R Y H I R E G I S T E R ( 1 0 ) * 908 ************************************************************************ 909 * 910 * 6 6 6 6 5 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 911 * 3 2 1 0 9 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 912 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 913 * | R | Fill // VPN2 | 0 | ASID | EntryHi 914 * +-+-+-+-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 915 */ 916 917 #define C0_EntryHi $10 918 #define R_C0_EntryHi 10 919 #define C0_TLBHI C0_EntryHi /* OBSOLETE - DO NOT USE IN NEW CODE */ 920 921 #define S_EntryHiR64 62 /* Region (R/W) */ 922 #define M_EntryHiR64 UNS64Const(0xc000000000000000) 923 #define S_EntryHiVPN2 13 /* VPN/2 (R/W) */ 924 #define M_EntryHiVPN2 (0x7ffff << S_EntryHiVPN2) 925 #define M_EntryHiVPN264 UNS64Const(0x000000ffffffe000) 926 #define S_EntryHiASID 0 /* ASID (R/W) */ 927 #define M_EntryHiASID (0xff << S_EntryHiASID) 928 #define S_EntryHiVPN_Shf S_EntryHiVPN2 929 930 #define M_EntryHi0Fields 0x00001f00 931 #define M_EntryHiRFields 0x00000000 932 #define M_EntryHi0Fields64 UNS64Const(0x0000000000001f00) 933 #define M_EntryHiRFields64 UNS64Const(0x3fffff0000000000) 934 935 936 /* 937 ************************************************************************ 938 * C O M P A R E R E G I S T E R ( 1 1 ) * 939 ************************************************************************ 940 * 941 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 942 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 943 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 944 * | Compare Value | Compare 945 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 946 */ 947 948 #define C0_Compare $11 949 #define R_C0_Compare 11 950 #define C0_COMPARE C0_Compare /* OBSOLETE - DO NOT USE IN NEW CODE */ 951 952 #define M_Compare0Fields 0x00000000 953 #define M_CompareRFields 0x00000000 954 955 956 /* 957 ************************************************************************ 958 * S T A T U S R E G I S T E R ( 1 2 ) * 959 ************************************************************************ 960 * 961 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 962 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 963 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 964 * |C|C|C|C|R|F|R|M|P|B|T|S|M| | R |I|I|I|I|I|I|I|I|K|S|U|U|R|E|E|I| 965 * |U|U|U|U|P|R|E|X|X|E|S|R|M| | s |M|M|M|M|M|M|M|M|X|X|X|M|s|R|X|E| Status 966 * |3|2|1|0| | | | | |V| | |I| | v |7|6|5|4|3|2|1|0| | | | |v|L|L| | 967 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 968 */ 969 970 #define C0_Status $12 971 #define R_C0_Status 12 972 #define C0_SR C0_Status /* OBSOLETE - DO NOT USE IN NEW CODE */ 973 974 #define S_StatusCU 28 /* Coprocessor enable (R/W) */ 975 #define M_StatusCU (0xf << S_StatusCU) 976 #define S_StatusCU3 31 977 #define M_StatusCU3 (0x1 << S_StatusCU3) 978 #define S_StatusCU2 30 979 #define M_StatusCU2 (0x1 << S_StatusCU2) 980 #define S_StatusCU1 29 981 #define M_StatusCU1 (0x1 << S_StatusCU1) 982 #define S_StatusCU0 28 983 #define M_StatusCU0 (0x1 << S_StatusCU0) 984 #define S_StatusRP 27 /* Enable reduced power mode (R/W) */ 985 #define M_StatusRP (0x1 << S_StatusRP) 986 #define S_StatusFR 26 /* Enable 64-bit FPRs (MIPS64 only) (R/W) */ 987 #define M_StatusFR (0x1 << S_StatusFR) 988 #define S_StatusRE 25 /* Enable reverse endian (R/W) */ 989 #define M_StatusRE (0x1 << S_StatusRE) 990 #define S_StatusMX 24 /* Enable access to MDMX resources (MIPS64 only) (R/W) */ 991 #define M_StatusMX (0x1 << S_StatusMX) 992 #define S_StatusPX 23 /* Enable access to 64-bit instructions/data (MIPS64 only) (R/W) */ 993 #define M_StatusPX (0x1 << S_StatusPX) 994 #define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */ 995 #define M_StatusBEV (0x1 << S_StatusBEV) 996 #define S_StatusTS 21 /* Denote TLB shutdown (R/W) */ 997 #define M_StatusTS (0x1 << S_StatusTS) 998 #define S_StatusSR 20 /* Denote soft reset (R/W) */ 999 #define M_StatusSR (0x1 << S_StatusSR) 1000 #define S_StatusNMI 19 1001 #define M_StatusNMI (0x1 << S_StatusNMI) /* Denote NMI (R/W) */ 1002 #define S_StatusIM 8 /* Interrupt mask (R/W) */ 1003 #define M_StatusIM (0xff << S_StatusIM) 1004 #define S_StatusIM7 15 1005 #define M_StatusIM7 (0x1 << S_StatusIM7) 1006 #define S_StatusIM6 14 1007 #define M_StatusIM6 (0x1 << S_StatusIM6) 1008 #define S_StatusIM5 13 1009 #define M_StatusIM5 (0x1 << S_StatusIM5) 1010 #define S_StatusIM4 12 1011 #define M_StatusIM4 (0x1 << S_StatusIM4) 1012 #define S_StatusIM3 11 1013 #define M_StatusIM3 (0x1 << S_StatusIM3) 1014 #define S_StatusIM2 10 1015 #define M_StatusIM2 (0x1 << S_StatusIM2) 1016 #define S_StatusIM1 9 1017 #define M_StatusIM1 (0x1 << S_StatusIM1) 1018 #define S_StatusIM0 8 1019 #define M_StatusIM0 (0x1 << S_StatusIM0) 1020 #define S_StatusKX 7 /* Enable access to extended kernel addresses (MIPS64 only) (R/W) */ 1021 #define M_StatusKX (0x1 << S_StatusKX) 1022 #define S_StatusSX 6 /* Enable access to extended supervisor addresses (MIPS64 only) (R/W) */ 1023 #define M_StatusSX (0x1 << S_StatusSX) 1024 #define S_StatusUX 5 /* Enable access to extended user addresses (MIPS64 only) (R/W) */ 1025 #define M_StatusUX (0x1 << S_StatusUX) 1026 #define S_StatusKSU 3 /* Two-bit current mode (R/W) */ 1027 #define M_StatusKSU (0x3 << S_StatusKSU) 1028 #define S_StatusUM 4 /* User mode if supervisor mode not implemented (R/W) */ 1029 #define M_StatusUM (0x1 << S_StatusUM) 1030 #define S_StatusSM 3 /* Supervisor mode (R/W) */ 1031 #define M_StatusSM (0x1 << S_StatusSM) 1032 #define S_StatusERL 2 /* Denotes error level (R/W) */ 1033 #define M_StatusERL (0x1 << S_StatusERL) 1034 #define S_StatusEXL 1 /* Denotes exception level (R/W) */ 1035 #define M_StatusEXL (0x1 << S_StatusEXL) 1036 #define S_StatusIE 0 /* Enables interrupts (R/W) */ 1037 #define M_StatusIE (0x1 << S_StatusIE) 1038 1039 #define M_Status0Fields 0x00040000 1040 #define M_StatusRFields 0x058000e0 /* FR, MX, PX, KX, SX, UX unused in MIPS32 */ 1041 #define M_Status0Fields64 0x00040000 1042 #define M_StatusRFields64 0x00000000 1043 1044 /* 1045 * Values in the KSU field 1046 */ 1047 #define K_StatusKSU_U 2 /* User mode in KSU field */ 1048 #define K_StatusKSU_S 1 /* Supervisor mode in KSU field */ 1049 #define K_StatusKSU_K 0 /* Kernel mode in KSU field */ 1050 1051 1052 /* 1053 ************************************************************************ 1054 * C A U S E R E G I S T E R ( 1 3 ) * 1055 ************************************************************************ 1056 * 1057 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1058 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1059 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1060 * |B| | C | |I|W| |I|I|I|I|I|I|I|I| | | R | 1061 * |D| | E | Rsvd |V|P| Rsvd |P|P|P|P|P|P|P|P| | ExcCode | s | Cause 1062 * | | | | | | | |7|6|5|4|3|2|1|0| | | v | 1063 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1064 */ 1065 1066 #define C0_Cause $13 1067 #define R_C0_Cause 13 1068 #define C0_CAUSE C0_Cause /* OBSOLETE - DO NOT USE IN NEW CODE */ 1069 1070 #define S_CauseBD 31 1071 #define M_CauseBD (0x1 << S_CauseBD) 1072 #define S_CauseCE 28 1073 #define M_CauseCE (0x3<< S_CauseCE) 1074 #define S_CauseIV 23 1075 #define M_CauseIV (0x1 << S_CauseIV) 1076 #define S_CauseWP 22 1077 #define M_CauseWP (0x1 << S_CauseWP) 1078 #define S_CauseIP 8 1079 #define M_CauseIP (0xff << S_CauseIP) 1080 #define S_CauseIPEXT 10 1081 #define M_CauseIPEXT (0x3f << S_CauseIPEXT) 1082 #define S_CauseIP7 15 1083 #define M_CauseIP7 (0x1 << S_CauseIP7) 1084 #define S_CauseIP6 14 1085 #define M_CauseIP6 (0x1 << S_CauseIP6) 1086 #define S_CauseIP5 13 1087 #define M_CauseIP5 (0x1 << S_CauseIP5) 1088 #define S_CauseIP4 12 1089 #define M_CauseIP4 (0x1 << S_CauseIP4) 1090 #define S_CauseIP3 11 1091 #define M_CauseIP3 (0x1 << S_CauseIP3) 1092 #define S_CauseIP2 10 1093 #define M_CauseIP2 (0x1 << S_CauseIP2) 1094 #define S_CauseIP1 9 1095 #define M_CauseIP1 (0x1 << S_CauseIP1) 1096 #define S_CauseIP0 8 1097 #define M_CauseIP0 (0x1 << S_CauseIP0) 1098 #define S_CauseExcCode 2 1099 #define M_CauseExcCode (0x1f << S_CauseExcCode) 1100 1101 #define M_Cause0Fields 0x4f3f0083 1102 #define M_CauseRFields 0xb000fc7c 1103 1104 /* 1105 * Values in the CE field 1106 */ 1107 #define K_CauseCE0 0 /* Coprocessor 0 in the CE field */ 1108 #define K_CauseCE1 1 /* Coprocessor 1 in the CE field */ 1109 #define K_CauseCE2 2 /* Coprocessor 2 in the CE field */ 1110 #define K_CauseCE3 3 /* Coprocessor 3 in the CE field */ 1111 1112 /* 1113 * Values in the ExcCode field 1114 */ 1115 #define EX_INT 0 /* Interrupt */ 1116 #define EXC_INT (EX_INT << S_CauseExcCode) 1117 #define EX_MOD 1 /* TLB modified */ 1118 #define EXC_MOD (EX_MOD << S_CauseExcCode) 1119 #define EX_TLBL 2 /* TLB exception (load or ifetch) */ 1120 #define EXC_TLBL (EX_TLBL << S_CauseExcCode) 1121 #define EX_TLBS 3 /* TLB exception (store) */ 1122 #define EXC_TLBS (EX_TLBS << S_CauseExcCode) 1123 #define EX_ADEL 4 /* Address error (load or ifetch) */ 1124 #define EXC_ADEL (EX_ADEL << S_CauseExcCode) 1125 #define EX_ADES 5 /* Address error (store) */ 1126 #define EXC_ADES (EX_ADES << S_CauseExcCode) 1127 #define EX_IBE 6 /* Instruction Bus Error */ 1128 #define EXC_IBE (EX_IBE << S_CauseExcCode) 1129 #define EX_DBE 7 /* Data Bus Error */ 1130 #define EXC_DBE (EX_DBE << S_CauseExcCode) 1131 #define EX_SYS 8 /* Syscall */ 1132 #define EXC_SYS (EX_SYS << S_CauseExcCode) 1133 #define EX_SYSCALL EX_SYS 1134 #define EXC_SYSCALL EXC_SYS 1135 #define EX_BP 9 /* Breakpoint */ 1136 #define EXC_BP (EX_BP << S_CauseExcCode) 1137 #define EX_BREAK EX_BP 1138 #define EXC_BREAK EXC_BP 1139 #define EX_RI 10 /* Reserved instruction */ 1140 #define EXC_RI (EX_RI << S_CauseExcCode) 1141 #define EX_CPU 11 /* CoProcessor Unusable */ 1142 #define EXC_CPU (EX_CPU << S_CauseExcCode) 1143 #define EX_OV 12 /* OVerflow */ 1144 #define EXC_OV (EX_OV << S_CauseExcCode) 1145 #define EX_TR 13 /* Trap instruction */ 1146 #define EXC_TR (EX_TR << S_CauseExcCode) 1147 #define EX_TRAP EX_TR 1148 #define EXC_TRAP EXC_TR 1149 #define EX_FPE 15 /* floating point exception */ 1150 #define EXC_FPE (EX_FPE << S_CauseExcCode) 1151 #define EX_C2E 18 /* COP2 exception */ 1152 #define EXC_C2E (EX_C2E << S_CauseExcCode) 1153 #define EX_MDMX 22 /* MDMX exception */ 1154 #define EXC_MDMX (EX_MDMX << S_CauseExcCode) 1155 #define EX_WATCH 23 /* Watch exception */ 1156 #define EXC_WATCH (EX_WATCH << S_CauseExcCode) 1157 #define EX_MCHECK 24 /* Machine check exception */ 1158 #define EXC_MCHECK (EX_MCHECK << S_CauseExcCode) 1159 #define EX_CacheErr 30 /* Cache error caused re-entry to Debug Mode */ 1160 #define EXC_CacheErr (EX_CacheErr << S_CauseExcCode) 1161 1162 1163 /* 1164 ************************************************************************ 1165 * E P C R E G I S T E R ( 1 4 ) * 1166 ************************************************************************ 1167 * 1168 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1169 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1170 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1171 * | // Exception PC | EPC 1172 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1173 */ 1174 1175 #define C0_EPC $14 1176 #define R_C0_EPC 14 1177 1178 #define M_EPC0Fields 0x00000000 1179 #define M_EPCRFields 0x00000000 1180 #define M_EPC0Fields64 UNS64Const(0x0000000000000000) 1181 #define M_EPCRFields64 UNS64Const(0x0000000000000000) 1182 1183 /* 1184 ************************************************************************ 1185 * P R I D R E G I S T E R ( 1 5 ) * 1186 ************************************************************************ 1187 * 1188 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1189 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1190 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1191 * | Company Opts | Company ID | Procesor ID | Revision | PRId 1192 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1193 */ 1194 1195 #define C0_PRId $15 1196 #define R_C0_PRId 15 1197 #define C0_PRID C0_PRID /* OBSOLETE - DO NOT USE IN NEW CODE */ 1198 1199 #define S_PRIdCoOpt 24 /* Company options (R) */ 1200 #define M_PRIdCoOpt (0xff << S_PRIdCoOpt) 1201 #define S_PRIdCoID 16 /* Company ID (R) */ 1202 #define M_PRIdCoID (0xff << S_PRIdCoID) 1203 #define S_PRIdImp 8 /* Implementation ID (R) */ 1204 #define M_PRIdImp (0xff << S_PRIdImp) 1205 #define S_PRIdRev 0 /* Revision (R) */ 1206 #define M_PRIdRev (0xff << S_PRIdRev) 1207 1208 #define M_PRId0Fields 0x00000000 1209 #define M_PRIdRFields 0xffffffff 1210 /* 1211 * Values in the Company ID field 1212 */ 1213 #define K_PRIdCoID_MIPS 1 1214 #define K_PRIdCoID_Broadcom 2 1215 #define K_PRIdCoID_Alchemy 3 1216 #define K_PRIdCoID_SiByte 4 1217 #define K_PRIdCoID_SandCraft 5 1218 #define K_PRIdCoID_Philips 6 1219 #define K_PRIdCoID_NextAvailable 7 /* Next available encoding */ 1220 1221 1222 /* 1223 * Values in the implementation number field 1224 */ 1225 #define K_PRIdImp_Jade 0x80 1226 #define K_PRIdImp_Opal 0x81 1227 #define K_PRIdImp_Ruby 0x82 1228 #define K_PRIdImp_JadeLite 0x83 1229 #define K_PRIdImp_4KEc 0x84 /* Emerald with TLB MMU */ 1230 #define K_PRIdImp_4KEmp 0x85 /* Emerald with FM MMU */ 1231 #define K_PRIdImp_4KSc 0x86 /* Coral */ 1232 1233 #define K_PRIdImp_R3000 0x01 1234 #define K_PRIdImp_R4000 0x04 1235 #define K_PRIdImp_R10000 0x09 1236 #define K_PRIdImp_R4300 0x0b 1237 #define K_PRIdImp_R5000 0x23 1238 #define K_PRIdImp_R5200 0x28 1239 #define K_PRIdImp_R5400 0x54 1240 1241 /* 1242 ************************************************************************ 1243 * C O N F I G R E G I S T E R ( 1 6 ) * 1244 ************************************************************************ 1245 * 1246 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1247 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1248 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1249 * |M| |B| A | A | | K | Config 1250 * | | Reserved for Implementations|E| T | R | Reserved | 0 | 1251 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1252 */ 1253 1254 #define C0_Config $16 1255 #define R_C0_Config 16 1256 #define C0_CONFIG C0_Config /* OBSOLETE - DO NOT USE IN NEW CODE */ 1257 1258 #define S_ConfigMore 31 /* Additional config registers present (R) */ 1259 #define M_ConfigMore (0x1 << S_ConfigMore) 1260 #define S_ConfigImpl 16 /* Implementation-specific fields */ 1261 #define M_ConfigImpl (0x7fff << S_ConfigImpl) 1262 #define S_ConfigBE 15 /* Denotes big-endian operation (R) */ 1263 #define M_ConfigBE (0x1 << S_ConfigBE) 1264 #define S_ConfigAT 13 /* Architecture type (R) */ 1265 #define M_ConfigAT (0x3 << S_ConfigAT) 1266 #define S_ConfigAR 10 /* Architecture revision (R) */ 1267 #define M_ConfigAR (0x7 << S_ConfigAR) 1268 #define S_ConfigMT 7 /* MMU Type (R) */ 1269 #define M_ConfigMT (0x7 << S_ConfigMT) 1270 #define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */ 1271 #define M_ConfigK0 (0x7 << S_ConfigK0) 1272 1273 /* 1274 * The following definitions are technically part of the "reserved for 1275 * implementations" field, but are the semi-standard definition used in 1276 * fixed-mapping MMUs to control the cacheability of kuseg and kseg2/3 1277 * references. For that reason, they are included here, but may be 1278 * overridden by true implementation-specific definitions 1279 */ 1280 #define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */ 1281 #define M_ConfigK23 (0x7 << S_ConfigK23) 1282 #define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */ 1283 #define M_ConfigKU (0x7 << S_ConfigKU) 1284 1285 #define M_Config0Fields 0x00000078 1286 #define M_ConfigRFields 0x8000ff80 1287 1288 /* 1289 * Values in the AT field 1290 */ 1291 #define K_ConfigAT_MIPS32 0 /* MIPS32 */ 1292 #define K_ConfigAT_MIPS64S 1 /* MIPS64 with 32-bit addresses */ 1293 #define K_ConfigAT_MIPS64 2 /* MIPS64 with 32/64-bit addresses */ 1294 1295 /* 1296 * Values in the MT field 1297 */ 1298 #define K_ConfigMT_NoMMU 0 /* No MMU */ 1299 #define K_ConfigMT_TLBMMU 1 /* Standard TLB MMU */ 1300 #define K_ConfigMT_BATMMU 2 /* Standard BAT MMU */ 1301 #define K_ConfigMT_FMMMU 3 /* Standard Fixed Mapping MMU */ 1302 1303 1304 /* 1305 ************************************************************************ 1306 * C O N F I G 1 R E G I S T E R ( 1 6, SELECT 1 ) * 1307 ************************************************************************ 1308 * 1309 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1310 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1311 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1312 * |M| MMU Size | IS | IL | IA | DS | DL | DA |C|M|P|W|C|E|F| Config1 1313 * | | | | | | | | |2|D|C|R|A|P|P| 1314 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1315 */ 1316 1317 #define C0_Config1 $16,1 1318 #define R_C0_Config1 16 1319 1320 #define S_Config1More 31 /* Additional Config registers present (R) */ 1321 #define M_Config1More (0x1 << S_Config1More) 1322 #define S_Config1MMUSize 25 /* Number of MMU entries - 1 (R) */ 1323 #define M_Config1MMUSize (0x3f << S_Config1MMUSize) 1324 #define S_Config1IS 22 /* Icache sets per way (R) */ 1325 #define M_Config1IS (0x7 << S_Config1IS) 1326 #define S_Config1IL 19 /* Icache line size (R) */ 1327 #define M_Config1IL (0x7 << S_Config1IL) 1328 #define S_Config1IA 16 /* Icache associativity - 1 (R) */ 1329 #define M_Config1IA (0x7 << S_Config1IA) 1330 #define S_Config1DS 13 /* Dcache sets per way (R) */ 1331 #define M_Config1DS (0x7 << S_Config1DS) 1332 #define S_Config1DL 10 /* Dcache line size (R) */ 1333 #define M_Config1DL (0x7 << S_Config1DL) 1334 #define S_Config1DA 7 /* Dcache associativity (R) */ 1335 #define M_Config1DA (0x7 << S_Config1DA) 1336 #define S_Config1C2 6 /* Coprocessor 2 present (R) */ 1337 #define M_Config1C2 (0x1 << S_Config1C2) 1338 #define S_Config1MD 5 /* Denotes MDMX present (R) */ 1339 #define M_Config1MD (0x1 << S_Config1MD) 1340 #define S_Config1PC 4 /* Denotes performance counters present (R) */ 1341 #define M_Config1PC (0x1 << S_Config1PC) 1342 #define S_Config1WR 3 /* Denotes watch registers present (R) */ 1343 #define M_Config1WR (0x1 << S_Config1WR) 1344 #define S_Config1CA 2 /* Denotes MIPS-16 present (R) */ 1345 #define M_Config1CA (0x1 << S_Config1CA) 1346 #define S_Config1EP 1 /* Denotes EJTAG present (R) */ 1347 #define M_Config1EP (0x1 << S_Config1EP) 1348 #define S_Config1FP 0 /* Denotes floating point present (R) */ 1349 #define M_Config1FP (0x1 << S_Config1FP) 1350 1351 #define M_Config10Fields 0x00000060 1352 #define M_Config1RFields 0x7fffff9f 1353 1354 /* 1355 * The following macro generates a table that is indexed 1356 * by the Icache or Dcache sets field in Config1 and 1357 * contains the decoded value of sets per way 1358 */ 1359 #define Config1CacheSets() \ 1360 HALF(64); \ 1361 HALF(128); \ 1362 HALF(256); \ 1363 HALF(512); \ 1364 HALF(1024); \ 1365 HALF(2048); \ 1366 HALF(4096); \ 1367 HALF(8192); 1368 1369 /* 1370 * The following macro generates a table that is indexed 1371 * by the Icache or Dcache line size field in Config1 and 1372 * contains the decoded value of the cache line size, in bytes 1373 */ 1374 #define Config1CacheLineSize() \ 1375 HALF(0); \ 1376 HALF(4); \ 1377 HALF(8); \ 1378 HALF(16); \ 1379 HALF(32); \ 1380 HALF(64); \ 1381 HALF(128); \ 1382 HALF(256); 1383 1384 1385 /* 1386 ************************************************************************ 1387 * C O N F I G 2 R E G I S T E R ( 1 6, SELECT 2 ) * 1388 ************************************************************************ 1389 * 1390 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1391 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1392 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1393 * |M| | | | | | | | | | | | |S|T| Config1 1394 * | | | | | | | | | | | | | |M|L| 1395 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1396 */ 1397 1398 #define C0_Config2 $16,2 1399 #define R_C0_Config2 16 1400 1401 #define S_Config2More 31 /* Additional Config registers present (R) */ 1402 #define M_Config2More (0x1 << S_Config2More) 1403 #define S_Config2SM 1 /* Denotes SmartMIPS ASE present (R) */ 1404 #define M_Config2SM (0x1 << S_Config2SM) 1405 #define S_Config2TL 0 /* Denotes Tracing Logic present (R) */ 1406 #define M_Config2TL (0x1 << S_Config2TL) 1407 1408 #define M_Config20Fields 0xfffffffc 1409 #define M_Config2RFields 0x00000003 1410 1411 /* 1412 ************************************************************************ 1413 * L L A D D R R E G I S T E R ( 1 7 ) * 1414 ************************************************************************ 1415 * 1416 * 6 6 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1417 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1418 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1419 * | // LL Physical Address | LLAddr 1420 * +-+-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1421 */ 1422 1423 #define C0_LLAddr $17 1424 #define R_C0_LLAddr 17 1425 #define C0_LLADDR C0_LLAddr /* OBSOLETE - DO NOT USE IN NEW CODE */ 1426 1427 #define M_LLAddr0Fields 0x00000000 1428 #define M_LLAddrRFields 0x00000000 1429 #define M_LLAddr0Fields64 UNS64Const(0x0000000000000000) 1430 #define M_LLAddrRFields64 UNS64Const(0x0000000000000000) 1431 1432 1433 /* 1434 ************************************************************************ 1435 * W A T C H L O R E G I S T E R ( 1 8 ) * 1436 ************************************************************************ 1437 * 1438 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1439 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1440 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1441 * | // Watch Virtual Address |I|R|W| WatchLo 1442 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1443 */ 1444 1445 #define C0_WatchLo $18 1446 #define R_C0_WatchLo 18 1447 #define C0_WATCHLO C0_WatchLo /* OBSOLETE - DO NOT USE IN NEW CODE */ 1448 1449 #define S_WatchLoVAddr 3 /* Watch virtual address (R/W) */ 1450 #define M_WatchLoVAddr (0x1fffffff << S_WatchLoVAddr) 1451 #define S_WatchLoI 2 /* Enable Istream watch (R/W) */ 1452 #define M_WatchLoI (0x1 << S_WatchLoI) 1453 #define S_WatchLoR 1 /* Enable data read watch (R/W) */ 1454 #define M_WatchLoR (0x1 << S_WatchLoR) 1455 #define S_WatchLoW 0 /* Enable data write watch (R/W) */ 1456 #define M_WatchLoW (0x1 << S_WatchLoW) 1457 1458 #define M_WatchLo0Fields 0x00000000 1459 #define M_WatchLoRFields 0x00000000 1460 #define M_WatchLo0Fields64 UNS64Const(0x0000000000000000) 1461 #define M_WatchLoRFields64 UNS64Const(0x0000000000000000) 1462 1463 #define M_WatchLoEnables (M_WatchLoI | M_WatchLoR | M_WatchLoW) 1464 1465 1466 /* 1467 ************************************************************************ 1468 * W A T C H H I R E G I S T E R ( 1 9 ) * 1469 ************************************************************************ 1470 * 1471 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1472 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1473 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1474 * |M|G| Rsvd | ASID | Rsvd | Mask | 0 | WatchHi 1475 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1476 */ 1477 1478 #define C0_WatchHi $19 1479 #define R_C0_WatchHi 19 1480 #define C0_WATCHHI C0_WatchHi /* OBSOLETE - DO NOT USE IN NEW CODE */ 1481 1482 #define S_WatchHiM 31 /* Denotes additional Watch registers present (R) */ 1483 #define M_WatchHiM (0x1 << S_WatchHiM) 1484 #define S_WatchHiG 30 /* Enable ASID-independent Watch match (R/W) */ 1485 #define M_WatchHiG (0x1 << S_WatchHiG) 1486 #define S_WatchHiASID 16 /* ASID value to match (R/W) */ 1487 #define M_WatchHiASID (0xff << S_WatchHiASID) 1488 #define S_WatchHiMask 3 /* Address inhibit mask (R/W) */ 1489 #define M_WatchHiMask (0x1ff << S_WatchHiMask) 1490 1491 #define M_WatchHi0Fields 0x3f00f007 1492 #define M_WatchHiRFields 0x80000000 1493 1494 1495 /* 1496 ************************************************************************ 1497 * X C O N T E X T R E G I S T E R ( 2 0 ) * 1498 ************************************************************************ 1499 * 1500 * 6 // 3 3 3 3 3 3 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1501 * 3 // 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1502 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1503 * | // PTEBase | R | BadVPN2<39:13> | 0 | XContext 1504 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1505 */ 1506 1507 #define C0_XContext $20 1508 #define R_C0_XContext 20 1509 #define C0_EXTCTXT C0_XContext /* OBSOLETE - DO NOT USE IN NEW CODE */ 1510 1511 #define S_XContextBadVPN2 4 /* BadVPN2 (R) */ 1512 #define S_XContextBadVPN S_XContextBadVPN2 1513 1514 #define M_XContext0Fields 0x0000000f 1515 1516 1517 /* 1518 ************************************************************************ 1519 * D E B U G R E G I S T E R ( 2 3 ) * 1520 ************************************************************************ 1521 * 1522 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1523 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1524 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1525 * |D|D|N|L|D|H|C|I|M|C|D|I|D|D| | |N|S| |D|D|D|D|D|D| 1526 * |B|M|o|S|o|a|o|B|C|a|B|E|D|D|EJTAG|DExcCode |o|S| |I|I|D|D|B|S| 1527 * |D| |D|N|z|l|u|u|h|c|u|X|B|B| ver | |S|t| |N|B|B|B|p|S| 1528 * | | |C|M|e|t|n|s|e|h|s|I|S|L| | |S| | 0 |T| |S|L| | | Debug 1529 * | | |R| | | |t|E|c|e|E| |I|I| | |t| | | | | | | | | 1530 * | | | | | | |D|P|k|E|P| |m|m| | | | | | | | | | | | 1531 * | | | | | | |M| |P|P| | |p|p| | | | | | | | | | | | 1532 * | | | | | | | | | | | | |r|r| | | | | | | | | | | | 1533 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1534 */ 1535 1536 #define C0_Debug $23 /* EJTAG */ 1537 #define R_C0_Debug 23 1538 1539 #define S_DebugDBD 31 /* Debug branch delay (R) */ 1540 #define M_DebugDBD (0x1 << S_DebugDBD) 1541 #define S_DebugDM 30 /* Debug mode (R) */ 1542 #define M_DebugDM (0x1 << S_DebugDM) 1543 #define S_DebugNoDCR 29 /* No debug control register present (R) */ 1544 #define M_DebugNoDCR (0x1 << S_DebugNoDCR) 1545 #define S_DebugLSNM 28 /* Load/Store Normal Memory (R/W) */ 1546 #define M_DebugLSNM (0x1 << S_DebugLSNM) 1547 #define S_DebugDoze 27 /* Doze (R) */ 1548 #define M_DebugDoze (0x1 << S_DebugDoze) 1549 #define S_DebugHalt 26 /* Halt (R) */ 1550 #define M_DebugHalt (0x1 << S_DebugHalt) 1551 #define S_DebugCountDM 25 /* Count register behavior in debug mode (R/W) */ 1552 #define M_DebugCountDM (0x1 << S_DebugCountDM) 1553 #define S_DebugIBusEP 24 /* Imprecise Instn Bus Error Pending (R/W) */ 1554 #define M_DebugIBusEP (0x1 << S_DebugIBusEP) 1555 #define S_DebugMCheckP 23 /* Imprecise Machine Check Pending (R/W) */ 1556 #define M_DebugMCheckP (0x1 << S_DebugMCheckP) 1557 #define S_DebugCacheEP 22 /* Imprecise Cache Error Pending (R/W) */ 1558 #define M_DebugCacheEP (0x1 << S_DebugCacheEP) 1559 #define S_DebugDBusEP 21 /* Imprecise Data Bus Error Pending (R/W) */ 1560 #define M_DebugDBusEP (0x1 << S_DebugDBusEP) 1561 #define S_DebugIEXI 20 /* Imprecise Exception Inhibit (R/W) */ 1562 #define M_DebugIEXI (0x1 << S_DebugIEXI) 1563 #define S_DebugDDBSImpr 19 /* Debug data break store imprecise (R) */ 1564 #define M_DebugDDBSImpr (0x1 << S_DebugDDBSImpr) 1565 #define S_DebugDDBLImpr 18 /* Debug data break load imprecise (R) */ 1566 #define M_DebugDDBLImpr (0x1 << S_DebugDDBLImpr) 1567 #define S_DebugEJTAGver 15 /* EJTAG version number (R) */ 1568 #define M_DebugEJTAGver (0x7 << S_DebugEJTAGver) 1569 #define S_DebugDExcCode 10 /* Debug exception code (R) */ 1570 #define M_DebugDExcCode (0x1f << S_DebugDExcCode) 1571 #define S_DebugNoSSt 9 /* No single step implemented (R) */ 1572 #define M_DebugNoSSt (0x1 << S_DebugNoSSt) 1573 #define S_DebugSSt 8 /* Single step enable (R/W) */ 1574 #define M_DebugSSt (0x1 << S_DebugSSt) 1575 #define S_DebugDINT 5 /* Debug interrupt (R) */ 1576 #define M_DebugDINT (0x1 << S_DebugDINT) 1577 #define S_DebugDIB 4 /* Debug instruction break (R) */ 1578 #define M_DebugDIB (0x1 << S_DebugDIB) 1579 #define S_DebugDDBS 3 /* Debug data break store (R) */ 1580 #define M_DebugDDBS (0x1 << S_DebugDDBS) 1581 #define S_DebugDDBL 2 /* Debug data break load (R) */ 1582 #define M_DebugDDBL (0x1 << S_DebugDDBL) 1583 #define S_DebugDBp 1 /* Debug breakpoint (R) */ 1584 #define M_DebugDBp (0x1 << S_DebugDBp) 1585 #define S_DebugDSS 0 /* Debug single step (R) */ 1586 #define M_DebugDSS (0x1 << S_DebugDSS) 1587 1588 #define M_Debug0Fields 0x01f000c0 1589 #define M_DebugRFields 0xec0ffe3f 1590 1591 1592 /* 1593 ************************************************************************ 1594 * D E P C R E G I S T E R ( 2 4 ) * 1595 ************************************************************************ 1596 * 1597 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1598 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1599 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1600 * | // EJTAG Debug Exception PC | DEPC 1601 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1602 */ 1603 1604 1605 #define C0_DEPC $24 1606 #define R_C0_DEPC 24 1607 1608 #define M_DEEPC0Fields 0x00000000 1609 #define M_DEEPCRFields 0x00000000 1610 #define M_DEEPC0Fields64 UNS64Const(0x0000000000000000) 1611 #define M_DEEPCRFields64 UNS64Const(0x0000000000000000) 1612 1613 1614 /* 1615 ************************************************************************ 1616 * P E R F C N T R E G I S T E R ( 2 5 ) * 1617 ************************************************************************ 1618 * 1619 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1620 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1621 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1622 * | | | |I| | | |E| 1623 * |M| 0 | Event |E|U|S|K|X| PerfCnt 1624 * | | | | | | | |L| 1625 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1626 * 1627 * 1628 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1629 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1630 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1631 * | Event Count | PerfCnt 1632 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1633 */ 1634 1635 #define C0_PerfCnt $25 1636 #define R_C0_PerfCnt 25 1637 #define C0_PRFCNT0 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ 1638 #define C0_PRFCNT1 C0_PerfCnt /* OBSOLETE - DO NOT USE IN NEW CODE */ 1639 1640 #define S_PerfCntM 31 /* More performance counters exist (R) */ 1641 #define M_PerfCntM (1 << S_PerfCntM) 1642 #define S_PerfCntEvent 5 /* Enabled event (R/W) */ 1643 #define M_PerfCntEvent (0x3f << S_PerfCntEvent) 1644 #define S_PerfCntIE 4 /* Interrupt Enable (R/W) */ 1645 #define M_PerfCntIE (1 << S_PerfCntIE) 1646 #define S_PerfCntU 3 /* Enable counting in User Mode (R/W) */ 1647 #define M_PerfCntU (1 << S_PerfCntU) 1648 #define S_PerfCntS 2 /* Enable counting in Supervisor Mode (R/W) */ 1649 #define M_PerfCntS (1 << S_PerfCntS) 1650 #define S_PerfCntK 1 /* Enable counting in Kernel Mode (R/W) */ 1651 #define M_PerfCntK (1 << S_PerfCntK) 1652 #define S_PerfCntEXL 0 /* Enable counting while EXL==1 (R/W) */ 1653 #define M_PerfCntEXL (1 << S_PerfCntEXL) 1654 1655 #define M_PerfCnt0Fields 0x7ffff800 1656 #define M_PerfCntRFields 0x80000000 1657 1658 1659 /* 1660 ************************************************************************ 1661 * E R R C T L R E G I S T E R ( 2 6 ) * 1662 ************************************************************************ 1663 * 1664 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1665 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1666 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1667 * | Error Control | ErrCtl 1668 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1669 */ 1670 1671 #define C0_ErrCtl $26 1672 #define R_C0_ErrCtl 26 1673 #define C0_ECC $26 /* OBSOLETE - DO NOT USE IN NEW CODE */ 1674 #define R_C0_ECC 26 /* OBSOLETE - DO NOT USE IN NEW CODE */ 1675 1676 #define M_ErrCtl0Fields 0x00000000 1677 #define M_ErrCtlRFields 0x00000000 1678 1679 1680 /* 1681 ************************************************************************ 1682 * C A C H E E R R R E G I S T E R ( 2 7 ) * CacheErr 1683 ************************************************************************ 1684 * 1685 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1686 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1687 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1688 * | Cache Error Control | CacheErr 1689 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1690 */ 1691 1692 #define C0_CacheErr $27 1693 #define R_C0_CacheErr 27 1694 #define C0_CACHE_ERR C0_CacheErr /* OBSOLETE - DO NOT USE IN NEW CODE */ 1695 1696 #define M_CacheErr0Fields 0x00000000 1697 #define M_CachErrRFields 0x00000000 1698 1699 1700 /* 1701 ************************************************************************ 1702 * T A G L O R E G I S T E R ( 2 8 ) * TagLo 1703 ************************************************************************ 1704 * 1705 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1706 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1707 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1708 * | TagLo | TagLo 1709 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1710 */ 1711 1712 #define C0_TagLo $28 1713 #define R_C0_TagLo 28 1714 #define C0_TAGLO C0_TagLo /* OBSOLETE - DO NOT USE IN NEW CODE */ 1715 1716 /* 1717 * Some implementations use separate TagLo registers for the 1718 * instruction and data caches. In those cases, the following 1719 * definitions can be used in relevant code 1720 */ 1721 1722 #define C0_ITagLo $28,0 1723 #define C0_DTagLo $28,2 1724 1725 #define M_TagLo0Fields 0x00000000 1726 #define M_TagLoRFields 0x00000000 1727 1728 1729 /* 1730 ************************************************************************ 1731 * D A T A L O R E G I S T E R ( 2 8, SELECT 1 ) * DataLo 1732 ************************************************************************ 1733 * 1734 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1735 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1736 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1737 * | DataLo | DataLo 1738 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1739 */ 1740 1741 #define C0_DataLo $28,1 1742 #define R_C0_DataLo 28 1743 1744 /* 1745 * Some implementations use separate DataLo registers for the 1746 * instruction and data caches. In those cases, the following 1747 * definitions can be used in relevant code 1748 */ 1749 1750 #define C0_IDataLo $28,1 1751 #define C0_DDataLo $28,3 1752 1753 #define M_DataLo0Fields 0x00000000 1754 #define M_DataLoRFields 0xffffffff 1755 1756 1757 /* 1758 ************************************************************************ 1759 * T A G H I R E G I S T E R ( 2 9 ) * TagHi 1760 ************************************************************************ 1761 * 1762 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1763 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1764 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1765 * | TagHi | TagHi 1766 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1767 */ 1768 1769 #define C0_TagHi $29 1770 #define R_C0_TagHi 29 1771 #define C0_TAGHI C0_TagHi /* OBSOLETE - DO NOT USE IN NEW CODE */ 1772 1773 /* 1774 * Some implementations use separate TagHi registers for the 1775 * instruction and data caches. In those cases, the following 1776 * definitions can be used in relevant code 1777 */ 1778 1779 #define C0_ITagHi $29,0 1780 #define C0_DTagHi $29,2 1781 1782 #define M_TagHi0Fields 0x00000000 1783 #define M_TagHiRFields 0x00000000 1784 1785 1786 /* 1787 ************************************************************************ 1788 * D A T A H I R E G I S T E R ( 2 9, SELECT 1 ) * DataHi 1789 ************************************************************************ 1790 * 1791 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1792 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1793 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1794 * | DataHi | DataHi 1795 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1796 */ 1797 1798 #define C0_DataHi $29,1 1799 #define R_C0_DataHi 29 1800 1801 /* 1802 * Some implementations use separate DataHi registers for the 1803 * instruction and data caches. In those cases, the following 1804 * definitions can be used in relevant code 1805 */ 1806 1807 #define C0_IDataHi $29,1 1808 #define C0_DDataHi $29,3 1809 1810 #define M_DataHi0Fields 0x00000000 1811 #define M_DataHiRFields 0xffffffff 1812 1813 1814 /* 1815 ************************************************************************ 1816 * E R R O R E P C R E G I S T E R ( 3 0 ) * 1817 ************************************************************************ 1818 * 1819 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1820 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1821 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1822 * | // Error PC | ErrorEPC 1823 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1824 */ 1825 1826 #define C0_ErrorEPC $30 1827 #define R_C0_ErrorEPC 30 1828 #define C0_ERROR_EPC C0_ErrorEPC /* OBSOLETE - DO NOT USE IN NEW CODE */ 1829 1830 #define M_ErrorEPC0Fields 0x00000000 1831 #define M_ErrorEPCRFields 0x00000000 1832 #define M_ErrorEPC0Fields64 UNS64Const(0x0000000000000000) 1833 #define M_ErrorEPCRFields64 UNS64Const(0x0000000000000000) 1834 1835 1836 /* 1837 ************************************************************************ 1838 * D E S A V E R E G I S T E R ( 3 1 ) * 1839 ************************************************************************ 1840 * 1841 * 6 // 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1842 * 3 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 1843 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1844 * | // EJTAG Register Save Value | DESAVE 1845 * +-+//+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 1846 */ 1847 1848 #define C0_DESAVE $31 1849 #define R_C0_DESAVE 31 1850 1851 #define M_DESAVE0Fields 0x00000000 1852 #define M_DESAVERFields 0x00000000 1853 #define M_DESAVE0Fields64 UNS64Const(0x0000000000000000) 1854 #define M_DESAVERFields64 UNS64Const(0x0000000000000000) 1855 1856 1857 /* 1858 ************************************************************************* 1859 * C P 1 R E G I S T E R D E F I N I T I O N S * 1860 ************************************************************************* 1861 */ 1862 1863 1864 /* 1865 ************************************************************************* 1866 * H A R D W A R E F P R N A M E S * 1867 ************************************************************************* 1868 */ 1869 1870 #define fp0 $f0 1871 #define fp1 $f1 1872 #define fp2 $f2 1873 #define fp3 $f3 1874 #define fp4 $f4 1875 #define fp5 $f5 1876 #define fp6 $f6 1877 #define fp7 $f7 1878 #define fp8 $f8 1879 #define fp9 $f9 1880 #define fp10 $f10 1881 #define fp11 $f11 1882 #define fp12 $f12 1883 #define fp13 $f13 1884 #define fp14 $f14 1885 #define fp15 $f15 1886 #define fp16 $f16 1887 #define fp17 $f17 1888 #define fp18 $f18 1889 #define fp19 $f19 1890 #define fp20 $f20 1891 #define fp21 $f21 1892 #define fp22 $f22 1893 #define fp23 $f23 1894 #define fp24 $f24 1895 #define fp25 $f25 1896 #define fp26 $f26 1897 #define fp27 $f27 1898 #define fp28 $f28 1899 #define fp29 $f29 1900 #define fp30 $f30 1901 #define fp31 $f31 1902 1903 /* 1904 * The following definitions are used to convert an FPR name 1905 * into the corresponding even or odd name, respectively. 1906 * This is used in macro substitution in the AVPs. 1907 */ 1908 1909 #define fp1_even $f0 1910 #define fp3_even $f2 1911 #define fp5_even $f4 1912 #define fp7_even $f6 1913 #define fp9_even $f8 1914 #define fp11_even $f10 1915 #define fp13_even $f12 1916 #define fp15_even $f14 1917 #define fp17_even $f16 1918 #define fp19_even $f18 1919 #define fp21_even $f20 1920 #define fp23_even $f22 1921 #define fp25_even $f24 1922 #define fp27_even $f26 1923 #define fp29_even $f28 1924 #define fp31_even $f30 1925 1926 #define fp0_odd $f1 1927 #define fp2_odd $f3 1928 #define fp4_odd $f5 1929 #define fp6_odd $f7 1930 #define fp8_odd $f9 1931 #define fp10_odd $f11 1932 #define fp12_odd $f13 1933 #define fp14_odd $f15 1934 #define fp16_odd $f17 1935 #define fp18_odd $f19 1936 #define fp20_odd $f21 1937 #define fp22_odd $f23 1938 #define fp24_odd $f25 1939 #define fp26_odd $f27 1940 #define fp28_odd $f29 1941 #define fp30_odd $f31 1942 1943 1944 /* 1945 ************************************************************************* 1946 * H A R D W A R E F P R I N D I C E S * 1947 ************************************************************************* 1948 * 1949 * These definitions provide the index (number) of the FPR, as opposed 1950 * to the assembler register name ($n). 1951 */ 1952 1953 #define R_fp0 0 1954 #define R_fp1 1 1955 #define R_fp2 2 1956 #define R_fp3 3 1957 #define R_fp4 4 1958 #define R_fp5 5 1959 #define R_fp6 6 1960 #define R_fp7 7 1961 #define R_fp8 8 1962 #define R_fp9 9 1963 #define R_fp10 10 1964 #define R_fp11 11 1965 #define R_fp12 12 1966 #define R_fp13 13 1967 #define R_fp14 14 1968 #define R_fp15 15 1969 #define R_fp16 16 1970 #define R_fp17 17 1971 #define R_fp18 18 1972 #define R_fp19 19 1973 #define R_fp20 20 1974 #define R_fp21 21 1975 #define R_fp22 22 1976 #define R_fp23 23 1977 #define R_fp24 24 1978 #define R_fp25 25 1979 #define R_fp26 26 1980 #define R_fp27 27 1981 #define R_fp28 28 1982 #define R_fp29 29 1983 #define R_fp30 30 1984 #define R_fp31 31 1985 1986 1987 /* 1988 ************************************************************************* 1989 * H A R D W A R E F C R N A M E S * 1990 ************************************************************************* 1991 */ 1992 1993 #define fc0 $0 1994 #define fc25 $25 1995 #define fc26 $26 1996 #define fc28 $28 1997 #define fc31 $31 1998 1999 2000 /* 2001 ************************************************************************* 2002 * H A R D W A R E F C R I N D I C E S * 2003 ************************************************************************* 2004 * 2005 * These definitions provide the index (number) of the FCR, as opposed 2006 * to the assembler register name ($n). 2007 */ 2008 2009 #define R_fc0 0 2010 #define R_fc25 25 2011 #define R_fc26 26 2012 #define R_fc28 28 2013 #define R_fc31 31 2014 2015 2016 /* 2017 ************************************************************************* 2018 * H A R D W A R E F C C N A M E S * 2019 ************************************************************************* 2020 */ 2021 2022 #define cc0 $fcc0 2023 #define cc1 $fcc1 2024 #define cc2 $fcc2 2025 #define cc3 $fcc3 2026 #define cc4 $fcc4 2027 #define cc5 $fcc5 2028 #define cc6 $fcc6 2029 #define cc7 $fcc7 2030 2031 2032 /* 2033 ************************************************************************* 2034 * H A R D W A R E F C C I N D I C E S * 2035 ************************************************************************* 2036 * 2037 * These definitions provide the index (number) of the CC, as opposed 2038 * to the assembler register name ($n). 2039 */ 2040 2041 #define R_cc0 0 2042 #define R_cc1 1 2043 #define R_cc2 2 2044 #define R_cc3 3 2045 #define R_cc4 4 2046 #define R_cc5 5 2047 #define R_cc6 6 2048 #define R_cc7 7 2049 2050 2051 /* 2052 ************************************************************************ 2053 * I M P L E M E N T A T I O N R E G I S T E R * 2054 ************************************************************************ 2055 * 2056 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2057 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2058 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2059 * |Reserved for Additional|3|P|D|S| Implementation| Revision | FIR 2060 * | Configuration Bits |D|S| | | | | 2061 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2062 */ 2063 2064 #define C1_FIR $0 2065 #define R_C1_FIR 0 2066 2067 #define S_FIRConfigS 16 2068 #define M_FIRConfigS (0x1 << S_FIRConfigS) 2069 #define S_FIRConfigD 17 2070 #define M_FIRConfigD (0x1 << S_FIRConfigD) 2071 #define S_FIRConfigPS 18 2072 #define M_FIRConfigPS (0x1 << S_FIRConfigPS) 2073 #define S_FIRConfig3D 19 2074 #define M_FIRConfig3D (0x1 << S_FIRConfig3D) 2075 #define M_FIRConfigAll (M_FIRConfigS|M_FIRConfigD|M_FIRConfigPS|M_FIRConfig3D) 2076 2077 #define S_FIRImp 8 2078 #define M_FIRImp (0xff << S_FIRImp) 2079 2080 #define S_FIRRev 0 2081 #define M_FIRRev (0xff << S_FIRRev) 2082 2083 #define M_FIR0Fields 0xfff00000 2084 #define M_FIRRFields 0x000fffff 2085 2086 /* 2087 ************************************************************************ 2088 * C O N D I T I O N C O D E S R E G I S T E R * 2089 ************************************************************************ 2090 * 2091 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2092 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2093 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2094 * | 0 | CC | FCCR 2095 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2096 */ 2097 2098 #define C1_FCCR $25 2099 #define R_C1_FCCR 25 2100 2101 #define S_FCCRCC 0 2102 #define M_FCCRCC (0xff << S_FCCRCC) 2103 #define S_FCCRCC7 7 2104 #define M_FCCRCC7 (0x1 << S_FCCRCC7) 2105 #define S_FCCRCC6 6 2106 #define M_FCCRCC6 (0x1 << S_FCCRCC6) 2107 #define S_FCCRCC5 5 2108 #define M_FCCRCC5 (0x1 << S_FCCRCC5) 2109 #define S_FCCRCC4 4 2110 #define M_FCCRCC4 (0x1 << S_FCCRCC4) 2111 #define S_FCCRCC3 3 2112 #define M_FCCRCC3 (0x1 << S_FCCRCC3) 2113 #define S_FCCRCC2 2 2114 #define M_FCCRCC2 (0x1 << S_FCCRCC2) 2115 #define S_FCCRCC1 1 2116 #define M_FCCRCC1 (0x1 << S_FCCRCC1) 2117 #define S_FCCRCC0 0 2118 #define M_FCCRCC0 (0x1 << S_FCCRCC0) 2119 2120 #define M_FCCR0Fields 0xffffff00 2121 #define M_FCCRRFields 0x000000ff 2122 2123 2124 /* 2125 ************************************************************************ 2126 * E X C E P T I O N S R E G I S T E R * 2127 ************************************************************************ 2128 * 2129 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2130 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2131 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2132 * | 0 | Cause | 0 | Flags | 0 | FEXR 2133 * | |E|V|Z|O|U|I| |V|Z|O|U|I| | 2134 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2135 */ 2136 2137 #define C1_FEXR $26 2138 #define R_C1_FEXR 26 2139 2140 #define S_FEXRExc 12 2141 #define M_FEXRExc (0x3f << S_FEXRExc) 2142 #define S_FEXRExcE 17 2143 #define M_FEXRExcE (0x1 << S_FEXRExcE) 2144 #define S_FEXRExcV 16 2145 #define M_FEXRExcV (0x1 << S_FEXRExcV) 2146 #define S_FEXRExcZ 15 2147 #define M_FEXRExcZ (0x1 << S_FEXRExcZ) 2148 #define S_FEXRExcO 14 2149 #define M_FEXRExcO (0x1 << S_FEXRExcO) 2150 #define S_FEXRExcU 13 2151 #define M_FEXRExcU (0x1 << S_FEXRExcU) 2152 #define S_FEXRExcI 12 2153 #define M_FEXRExcI (0x1 << S_FEXRExcI) 2154 2155 #define S_FEXRFlg 2 2156 #define M_FEXRFlg (0x1f << S_FEXRFlg) 2157 #define S_FEXRFlgV 6 2158 #define M_FEXRFlgV (0x1 << S_FEXRFlgV) 2159 #define S_FEXRFlgZ 5 2160 #define M_FEXRFlgZ (0x1 << S_FEXRFlgZ) 2161 #define S_FEXRFlgO 4 2162 #define M_FEXRFlgO (0x1 << S_FEXRFlgO) 2163 #define S_FEXRFlgU 3 2164 #define M_FEXRFlgU (0x1 << S_FEXRFlgU) 2165 #define S_FEXRFlgI 2 2166 #define M_FEXRFlgI (0x1 << S_FEXRFlgI) 2167 2168 #define M_FEXR0Fields 0xfffc0f83 2169 #define M_FEXRRFields 0x00000000 2170 2171 2172 /* 2173 ************************************************************************ 2174 * E N A B L E S R E G I S T E R * 2175 ************************************************************************ 2176 * 2177 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2178 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2179 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2180 * | 0 | Enables | 0 |F|RM | FENR 2181 * | |V|Z|O|U|I| |S| | 2182 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2183 */ 2184 2185 #define C1_FENR $28 2186 #define R_C1_FENR 28 2187 2188 #define S_FENREna 7 2189 #define M_FENREna (0x1f << S_FENREna) 2190 #define S_FENREnaV 11 2191 #define M_FENREnaV (0x1 << S_FENREnaV) 2192 #define S_FENREnaZ 10 2193 #define M_FENREnaZ (0x1 << S_FENREnaZ) 2194 #define S_FENREnaO 9 2195 #define M_FENREnaO (0x1 << S_FENREnaO) 2196 #define S_FENREnaU 8 2197 #define M_FENREnaU (0x1 << S_FENREnaU) 2198 #define S_FENREnaI 7 2199 #define M_FENREnaI (0x1 << S_FENREnaI) 2200 2201 #define S_FENRFS 2 2202 #define M_FENRFS (0x1 << S_FENRFS) 2203 2204 #define S_FENRRM 0 2205 #define M_FENRRM (0x3 << S_FENRRM) 2206 2207 #define M_FENR0Fields 0xfffff078 2208 #define M_FENRRFields 0x00000000 2209 2210 2211 /* 2212 ************************************************************************ 2213 * C O N T R O L / S T A T U S R E G I S T E R * 2214 ************************************************************************ 2215 * 2216 * 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 2217 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 2218 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2219 * | FCC |F|C|Imp| 0 | Cause | Enables | Flags | RM| FCSR 2220 * |7|6|5|4|3|2|1|S|C| | |E|V|Z|O|U|I|V|Z|O|U|I|V|Z|O|U|I| | 2221 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 2222 */ 2223 2224 #define C1_FCSR $31 2225 #define R_C1_FCSR 31 2226 2227 #define S_FCSRFCC7_1 25 /* Floating point condition codes 7..1 (R/W) */ 2228 #define M_FCSRFCC7_1 (0x7f << S_FCSRFCC7_1) 2229 #define S_FCSRCC7 31 2230 #define M_FCSRCC7 (0x1 << S_FCSRCC7) 2231 #define S_FCSRCC6 30 2232 #define M_FCSRCC6 (0x1 << S_FCSRCC6) 2233 #define S_FCSRCC5 29 2234 #define M_FCSRCC5 (0x1 << S_FCSRCC5) 2235 #define S_FCSRCC4 28 2236 #define M_FCSRCC4 (0x1 << S_FCSRCC4) 2237 #define S_FCSRCC3 27 2238 #define M_FCSRCC3 (0x1 << S_FCSRCC3) 2239 #define S_FCSRCC2 26 2240 #define M_FCSRCC2 (0x1 << S_FCSRCC2) 2241 #define S_FCSRCC1 25 2242 #define M_FCSRCC1 (0x1 << S_FCSRCC1) 2243 2244 #define S_FCSRFS 24 /* Flush denorms to zero (R/W) */ 2245 #define M_FCSRFS (0x1 << S_FCSRFS) 2246 2247 #define S_FCSRCC0 23 /* Floating point condition code 0 (R/W) */ 2248 #define M_FCSRCC0 (0x1 << S_FCSRCC0) 2249 #define S_FCSRCC S_FCSRCC0 2250 #define M_FCSRCC M_FCSRCC0 2251 2252 #define S_FCSRImpl 21 /* Implementation-specific control bits (R/W) */ 2253 #define M_FCSRImpl (0x3 << S_FCSRImpl) 2254 2255 #define S_FCSRExc 12 /* Exception cause (R/W) */ 2256 #define M_FCSRExc (0x3f << S_FCSRExc) 2257 #define S_FCSRExcE 17 2258 #define M_FCSRExcE (0x1 << S_FCSRExcE) 2259 #define S_FCSRExcV 16 2260 #define M_FCSRExcV (0x1 << S_FCSRExcV) 2261 #define S_FCSRExcZ 15 2262 #define M_FCSRExcZ (0x1 << S_FCSRExcZ) 2263 #define S_FCSRExcO 14 2264 #define M_FCSRExcO (0x1 << S_FCSRExcO) 2265 #define S_FCSRExcU 13 2266 #define M_FCSRExcU (0x1 << S_FCSRExcU) 2267 #define S_FCSRExcI 12 2268 #define M_FCSRExcI (0x1 << S_FCSRExcI) 2269 2270 #define S_FCSREna 7 /* Exception enable (R/W) */ 2271 #define M_FCSREna (0x1f << S_FCSREna) 2272 #define S_FCSREnaV 11 2273 #define M_FCSREnaV (0x1 << S_FCSREnaV) 2274 #define S_FCSREnaZ 10 2275 #define M_FCSREnaZ (0x1 << S_FCSREnaZ) 2276 #define S_FCSREnaO 9 2277 #define M_FCSREnaO (0x1 << S_FCSREnaO) 2278 #define S_FCSREnaU 8 2279 #define M_FCSREnaU (0x1 << S_FCSREnaU) 2280 #define S_FCSREnaI 7 2281 #define M_FCSREnaI (0x1 << S_FCSREnaI) 2282 2283 #define S_FCSRFlg 2 /* Exception flags (R/W) */ 2284 #define M_FCSRFlg (0x1f << S_FCSRFlg) 2285 #define S_FCSRFlgV 6 2286 #define M_FCSRFlgV (0x1 << S_FCSRFlgV) 2287 #define S_FCSRFlgZ 5 2288 #define M_FCSRFlgZ (0x1 << S_FCSRFlgZ) 2289 #define S_FCSRFlgO 4 2290 #define M_FCSRFlgO (0x1 << S_FCSRFlgO) 2291 #define S_FCSRFlgU 3 2292 #define M_FCSRFlgU (0x1 << S_FCSRFlgU) 2293 #define S_FCSRFlgI 2 2294 #define M_FCSRFlgI (0x1 << S_FCSRFlgI) 2295 2296 #define S_FCSRRM 0 /* Rounding mode (R/W) */ 2297 #define M_FCSRRM (0x3 << S_FCSRRM) 2298 2299 #define M_FCSR0Fields 0x001c0000 2300 #define M_FCSRRFields 0x00000000 2301 2302 /* 2303 * Values in the rounding mode field (of both FCSR and FCCR) 2304 */ 2305 #define K_FCSRRM_RN 0 2306 #define K_FCSRRM_RZ 1 2307 #define K_FCSRRM_RP 2 2308 #define K_FCSRRM_RM 3 2309 2310 #endif /* _COMMON_MIPS_DEF_H_ */ 2311