1*10465441SEvalZero /* 2*10465441SEvalZero * File : mips_cfg.h 3*10465441SEvalZero * This file is part of RT-Thread RTOS 4*10465441SEvalZero * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team 5*10465441SEvalZero * 6*10465441SEvalZero * This program is free software; you can redistribute it and/or modify 7*10465441SEvalZero * it under the terms of the GNU General Public License as published by 8*10465441SEvalZero * the Free Software Foundation; either version 2 of the License, or 9*10465441SEvalZero * (at your option) any later version. 10*10465441SEvalZero * 11*10465441SEvalZero * This program is distributed in the hope that it will be useful, 12*10465441SEvalZero * but WITHOUT ANY WARRANTY; without even the implied warranty of 13*10465441SEvalZero * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14*10465441SEvalZero * GNU General Public License for more details. 15*10465441SEvalZero * 16*10465441SEvalZero * You should have received a copy of the GNU General Public License along 17*10465441SEvalZero * with this program; if not, write to the Free Software Foundation, Inc., 18*10465441SEvalZero * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19*10465441SEvalZero * 20*10465441SEvalZero * Change Logs: 21*10465441SEvalZero * Date Author Notes 22*10465441SEvalZero * 2016��9��10�� Urey the first version 23*10465441SEvalZero */ 24*10465441SEvalZero 25*10465441SEvalZero #ifndef _MIPS_CFG_H_ 26*10465441SEvalZero #define _MIPS_CFG_H_ 27*10465441SEvalZero 28*10465441SEvalZero #ifndef __ASSEMBLY__ 29*10465441SEvalZero #include <stdint.h> 30*10465441SEvalZero typedef struct mips32_core_cfg 31*10465441SEvalZero { 32*10465441SEvalZero uint16_t icache_line_size; 33*10465441SEvalZero // uint16_t icache_lines_per_way; 34*10465441SEvalZero // uint16_t icache_ways; 35*10465441SEvalZero uint16_t icache_size; 36*10465441SEvalZero uint16_t dcache_line_size; 37*10465441SEvalZero // uint16_t dcache_lines_per_way; 38*10465441SEvalZero // uint16_t dcache_ways; 39*10465441SEvalZero uint16_t dcache_size; 40*10465441SEvalZero 41*10465441SEvalZero uint16_t max_tlb_entries; /* number of tlb entry */ 42*10465441SEvalZero } mips32_core_cfg_t; 43*10465441SEvalZero 44*10465441SEvalZero extern mips32_core_cfg_t g_mips_core; 45*10465441SEvalZero 46*10465441SEvalZero #endif /* __ASSEMBLY__ */ 47*10465441SEvalZero 48*10465441SEvalZero #endif /* _MIPS_CFG_H_ */ 49