xref: /nrf52832-nimble/rt-thread/libcpu/m16c/m16c62p/context_iar.S (revision 104654410c56c573564690304ae786df310c91fc)
1/*
2 * File      : context.asm
3 * This file is part of RT-Thread RTOS
4 * COPYRIGHT (C) 2009, RT-Thread Development Team
5 *
6 * The license and distribution terms for this file may be
7 * found in the file LICENSE in this distribution or at
8 * http://www.rt-thread.org/license/LICENSE
9 *
10 * Change Logs:
11 * Date           Author       Notes
12 * 2010-04-09     fify         the first version
13 * 2010-04-19     fify         rewrite rt_hw_interrupt_disable/enable fuction
14 * 2010-04-20     fify         move peripheral ISR to bsp/interrupts.s34
15 *
16 * For       : Renesas M16C
17 * Toolchain : IAR's EW for M16C v3.401
18 */
19
20    RSEG    CSTACK
21
22    RSEG    ISTACK
23
24    RSEG    CODE(1)
25
26    EXTERN  rt_interrupt_from_thread
27    EXTERN  rt_interrupt_to_thread
28
29    PUBLIC  rt_hw_interrupt_disable
30    PUBLIC  rt_hw_interrupt_enable
31    PUBLIC  rt_hw_context_switch_to
32    PUBLIC  os_context_switch
33
34rt_hw_interrupt_disable:
35    STC     FLG, R0    ;fify 20100419
36    FCLR    I
37    RTS
38
39rt_hw_interrupt_enable:
40    LDC     R0, FLG    ;fify 20100419
41    RTS
42
43    .EVEN
44os_context_switch:
45    PUSHM   R0,R1,R2,R3,A0,A1,SB,FB
46
47    MOV.W   rt_interrupt_from_thread, A0
48    STC     ISP, [A0]
49    MOV.W   rt_interrupt_to_thread, A0
50    LDC     [A0], ISP
51
52    POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore registers from the new task's stack
53    REIT                                        ; Return from interrup
54
55/*
56 * void rt_hw_context_switch_to(rt_uint32 to);
57 * r0 --> to
58 * this fucntion is used to perform the first thread switch
59 */
60rt_hw_context_switch_to:
61    MOV.W   R0, A0
62    LDC     [A0], ISP
63    POPM    R0,R1,R2,R3,A0,A1,SB,FB
64    REIT
65
66    END
67