1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2013-07-20 Bernard first version
9 */
10
11 #include <rtthread.h>
12 #include <rthw.h>
13 #include <board.h>
14
15 #include "cp15.h"
16
17 #define DESC_SEC (0x2)
18 #define CB (3<<2) //cache_on, write_back
19 #define CNB (2<<2) //cache_on, write_through
20 #define NCB (1<<2) //cache_off,WR_BUF on
21 #define NCNB (0<<2) //cache_off,WR_BUF off
22 #define AP_RW (3<<10) //supervisor=RW, user=RW
23 #define AP_RO (2<<10) //supervisor=RW, user=RO
24 #define XN (1<<4) //eXecute Never
25
26 #define DOMAIN_FAULT (0x0)
27 #define DOMAIN_CHK (0x1)
28 #define DOMAIN_NOTCHK (0x3)
29 #define DOMAIN0 (0x0<<5)
30 #define DOMAIN1 (0x1<<5)
31
32 #define DOMAIN0_ATTR (DOMAIN_CHK<<0)
33 #define DOMAIN1_ATTR (DOMAIN_FAULT<<2)
34
35 /* Read/Write, cache, write back */
36 #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC)
37 /* Read/Write, cache, write through */
38 #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC)
39 /* Read/Write, device type */
40 #define RW_NCB (AP_RW|DOMAIN0|NCB|DESC_SEC)
41 /* Read/Write strongly ordered type */
42 #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC)
43 /* Read/Write without cache and write buffer, no execute */
44 #define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
45 /* Read/Write without cache and write buffer */
46 #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC)
47
rt_hw_cpu_dump_page_table(rt_uint32_t * ptb)48 void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
49 {
50 int i;
51 int fcnt = 0;
52
53 rt_kprintf("page table@%p\n", ptb);
54 for (i = 0; i < 1024*4; i++)
55 {
56 rt_uint32_t pte1 = ptb[i];
57 if ((pte1 & 0x3) == 0)
58 {
59 rt_kprintf("%03x: ", i);
60 fcnt++;
61 if (fcnt == 16)
62 {
63 rt_kprintf("fault\n");
64 fcnt = 0;
65 }
66 continue;
67 }
68 if (fcnt != 0)
69 {
70 rt_kprintf("fault\n");
71 fcnt = 0;
72 }
73
74 rt_kprintf("%03x: %08x: ", i, pte1);
75 if ((pte1 & 0x3) == 0x3)
76 {
77 rt_kprintf("LPAE\n");
78 }
79 else if ((pte1 & 0x3) == 0x1)
80 {
81 rt_kprintf("pte,ns:%d,domain:%d\n",
82 (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
83 /*
84 *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
85 * - 0x80000000 + 0xC0000000));
86 */
87 }
88 else if (pte1 & (1 << 18))
89 {
90 rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
91 (pte1 >> 19) & 0x1,
92 ((pte1 >> 13) | (pte1 >> 10))& 0xf,
93 (pte1 >> 4) & 0x1,
94 ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
95 }
96 else
97 {
98 rt_kprintf("section,ns:%d,ap:%x,"
99 "xn:%d,texcb:%02x,domain:%d\n",
100 (pte1 >> 19) & 0x1,
101 ((pte1 >> 13) | (pte1 >> 10))& 0xf,
102 (pte1 >> 4) & 0x1,
103 (((pte1 & (0x7 << 12)) >> 10) |
104 ((pte1 & 0x0c) >> 2)) & 0x1f,
105 (pte1 >> 5) & 0xf);
106 }
107 }
108 }
109
110 /* level1 page table, each entry for 1MB memory. */
111 /* MMUTable is the name used by codes of Xilinx */
112 volatile unsigned long MMUTable[4*1024] SECTION("mmu_tbl") __attribute__((aligned(16*1024)));
rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,rt_uint32_t vaddrEnd,rt_uint32_t paddrStart,rt_uint32_t attr)113 void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
114 rt_uint32_t vaddrEnd,
115 rt_uint32_t paddrStart,
116 rt_uint32_t attr)
117 {
118 volatile rt_uint32_t *pTT;
119 volatile int i, nSec;
120 pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
121 nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
122 for(i = 0; i <= nSec; i++)
123 {
124 *pTT = attr | (((paddrStart >> 20) + i) << 20);
125 pTT++;
126 }
127 }
128
rt_hw_set_domain_register(unsigned long domain_val)129 unsigned long rt_hw_set_domain_register(unsigned long domain_val)
130 {
131 unsigned long old_domain;
132
133 asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
134 asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
135
136 return old_domain;
137 }
138
rt_hw_mmu_init(void)139 void rt_hw_mmu_init(void)
140 {
141 extern rt_uint32_t __text_start;
142 rt_hw_cpu_dcache_disable();
143 rt_hw_cpu_icache_disable();
144 rt_cpu_mmu_disable();
145
146 /* set page table */
147 /* no access to the memory below .text */
148 /* 128M cached DDR memory */
149 rt_hw_mmu_setmtt((rt_uint32_t)&__text_start, 0x20000000-1,
150 0x1ff00000, RW_CB);
151 /* PL region */
152 rt_hw_mmu_setmtt(0x40000000, 0xBFFFFFFF, 0x40000000, RW_NCNBXN);
153 /* IOP registers */
154 rt_hw_mmu_setmtt(0xE0000000, 0xE02FFFFF, 0xE0000000, RW_NCNBXN);
155 /* no access to the SMC memory(enable it if you want) */
156 /* SLCR, PS and CPU private registers, note we map more memory space as the
157 * entry is 1MB in size. */
158 rt_hw_mmu_setmtt(0xF8000000, 0xF8FFFFFF, 0xF8000000, RW_NCNBXN);
159
160 /*rt_hw_cpu_dump_page_table(MMUTable);*/
161
162 /* become clients for all domains */
163 rt_hw_set_domain_register(0x55555555);
164
165 rt_cpu_tlb_set(MMUTable);
166
167 rt_cpu_mmu_enable();
168
169 rt_hw_cpu_icache_enable();
170 rt_hw_cpu_dcache_enable();
171 }
172
173