1;============================================================================================== 2; star_rvds.s for Keil MDK 4.10 3; 4; SEP4020 start up code 5; 6; Change Logs: 7; Date Author Notes 8; 2010-03-17 zchong 9;============================================================================================= 10 11PMU_PLTR EQU 0x10001000 ; PLL���ȶ�����ʱ�� 12PMU_PMCR EQU 0x10001004 ; ϵͳ��ʱ��PLL�Ŀ��ƼĴ��� 13PMU_PUCR EQU 0x10001008 ; USBʱ��PLL�Ŀ��ƼĴ��� 14PMU_PCSR EQU 0x1000100C ; �ڲ�ģ��ʱ��Դ�����Ŀ��ƼĴ��� 15PMU_PDSLOW EQU 0x10001010 ; SLOW״̬��ʱ�ӵķ�Ƶ���� 16PMU_PMDR EQU 0x10001014 ; оƬ����ģʽ�Ĵ��� 17PMU_RCTR EQU 0x10001018 ; Reset���ƼĴ��� 18PMU_CLRWAKUP EQU 0x1000101C ; WakeUp����Ĵ��� 19 20RTC_CTR EQU 0x1000200C ; RTC���ƼĴ��� 21 22INTC_IER EQU 0x10000000 ; IRQ�ж�����Ĵ��� 23INTC_IMR EQU 0x10000008 ; IRQ�ж����μĴ��� 24INTC_IFSR EQU 0x10000030 ; IRQ�ж�����״̬�Ĵ��� 25INTC_FIER EQU 0x100000C0 ; FIQ�ж�����Ĵ��� 26INTC_FIMR EQU 0x100000C4 ; FIQ�ж����μĴ��� 27 28EMI_CSACONF EQU 0x11000000 ; CSA�������üĴ��� 29EMI_CSECONF EQU 0x11000010 ; CSE�������üĴ��� 30EMI_CSFCONF EQU 0x11000014 ; CSF�������üĴ��� 31EMI_SDCONF1 EQU 0x11000018 ; SDRAMʱ�����üĴ���1 32EMI_SDCONF2 EQU 0x1100001C ; SDRAMʱ�����üĴ���2, SDRAM��ʼ���õ���������Ϣ 33EMI_REMAPCONF EQU 0x11000020 ; Ƭѡ�ռ估��ַӳ��REMAP���üĴ��� 34 35Mode_USR EQU 0x10 36Mode_FIQ EQU 0x11 37Mode_IRQ EQU 0x12 38Mode_SVC EQU 0x13 39Mode_ABT EQU 0x17 40Mode_UND EQU 0x1B 41Mode_SYS EQU 0x1F 42 43I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 44F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 45NOINT EQU 0xc0 46MASK_MODE EQU 0x0000003F 47MODE_SVC32 EQU 0x00000013 48 49; Internal Memory Base Addresses 50FLASH_BASE EQU 0x20000000 51RAM_BASE EQU 0x04000000 52SDRAM_BASE EQU 0x30000000 53 54; Stack 55Unused_Stack_Size EQU 0x00000100 56Svc_Stack_Size EQU 0x00001000 57Abt_Stack_Size EQU 0x00000000 58Fiq_Stack_Size EQU 0x00000000 59Irq_Stack_Size EQU 0x00001000 60Usr_Stack_Size EQU 0x00000000 61 62;SVC STACK 63 AREA STACK, NOINIT, READWRITE, ALIGN=3 64Svc_Stack SPACE Svc_Stack_Size 65__initial_sp 66Svc_Stack_Top 67 68;IRQ STACK 69 AREA STACK, NOINIT, READWRITE, ALIGN=3 70Irq_Stack SPACE Irq_Stack_Size 71Irq_Stack_Top 72 73;UNUSED STACK 74 AREA STACK, NOINIT, READWRITE, ALIGN=3 75Unused_Stack SPACE Unused_Stack_Size 76Unused_Stack_Top 77 78 79; Heap 80Heap_Size EQU 0x0000100 81 82 AREA HEAP, NOINIT, READWRITE, ALIGN=3 83 EXPORT Heap_Mem 84__heap_base 85Heap_Mem SPACE Heap_Size 86__heap_limit 87 88 PRESERVE8 89 90; Area Definition and Entry Point 91; Startup Code must be linked first at Address at which it expects to run. 92 93 AREA RESET, CODE, READONLY 94 ARM 95 96; Exception Vectors 97; Mapped to Address 0. 98; Absolute addressing mode must be used. 99; Dummy Handlers are implemented as infinite loops which can be modified. 100 EXPORT Entry_Point 101Entry_Point 102Vectors LDR PC,Reset_Addr 103 LDR PC,Undef_Addr 104 LDR PC,SWI_Addr 105 LDR PC,PAbt_Addr 106 LDR PC,DAbt_Addr 107 NOP ; Reserved Vector 108 LDR PC,IRQ_Addr 109 LDR PC,FIQ_Addr 110 111Reset_Addr DCD Reset_Handler 112Undef_Addr DCD Undef_Handler 113SWI_Addr DCD SWI_Handler 114PAbt_Addr DCD PAbt_Handler 115DAbt_Addr DCD DAbt_Handler 116 DCD 0 ; Reserved Address 117IRQ_Addr DCD IRQ_Handler 118FIQ_Addr DCD FIQ_Handler 119 120Undef_Handler B Undef_Handler 121SWI_Handler B SWI_Handler 122PAbt_Handler B Abort_Handler 123DAbt_Handler B Abort_Handler 124FIQ_Handler B FIQ_Handler 125 126Abort_Handler PROC 127 ARM 128 EXPORT Abort_Handler 129DeadLoop BHI DeadLoop ; Abort happened in irq mode, halt system. 130 ENDP 131 132 133; Reset Handler 134 ;IMPORT __user_initial_stackheap 135 EXPORT Reset_Handler 136Reset_Handler 137 138;**************************************************************** 139;* Shutdown watchdog 140;**************************************************************** 141 LDR R0,=RTC_CTR 142 LDR R1,=0x0 143 STR R1,[R0] 144 145;**************************************************************** 146;* shutdown interrupts 147;**************************************************************** 148 MRS R0, CPSR 149 BIC R0, R0, #MASK_MODE 150 ORR R0, R0, #MODE_SVC32 151 ORR R0, R0, #I_Bit 152 ORR R0, R0, #F_Bit 153 MSR CPSR_c, r0 154 155 LDR R0,=INTC_IER 156 LDR R1,=0x0 157 STR R1,[R0] 158 LDR R0,=INTC_IMR 159 LDR R1,=0xFFFFFFFF 160 STR R1,[R0] 161 162 LDR R0,=INTC_FIER 163 LDR R1,=0x0 164 STR R1,[R0] 165 LDR R0,=INTC_FIMR 166 LDR R1,=0x0F 167 STR R1,[R0] 168 169;**************************************************************** 170;* Initialize Stack Pointer 171;**************************************************************** 172 173 LDR SP, =Svc_Stack_Top ;init SP_svc 174 175 MOV R4, #0xD2 ;chmod to irq and init SP_irq 176 MSR cpsr_c, R4 177 LDR SP, =Irq_Stack_Top 178 179 MOV R4, #0XD1 ;chomod to fiq and init SP_fiq 180 MSR cpsr_c, R4 181 LDR SP, =Unused_Stack_Top 182 183 MOV R4, #0XD7 ;chomod to abt and init SP_ABT 184 MSR cpsr_c, R4 185 LDR SP, =Unused_Stack_Top 186 187 MOV R4, #0XDB ;chomod to undf and init SP_UNDF 188 MSR cpsr_c, R4 189 LDR SP, =Unused_Stack_Top 190 191 ;chomod to abt and init SP_sys 192 MOV R4, #0xDF ;all interrupts disabled 193 MSR cpsr_c, R4 ;SYSTEM mode, @32-bit code mode 194 LDR SP, =Unused_Stack_Top 195 196 MOV R4, #0XD3 ;chmod to svc modle, CPSR IRQ bit is disable 197 MSR cpsr_c, R4 198 199 200 201;**************************************************************** 202;* Initialize PMU & System Clock 203;**************************************************************** 204 205 LDR R4, =PMU_PCSR ; ������ģ��ʱ�� 206 LDR R5, =0x0001ffff 207 STR R5, [ R4 ] 208 209 LDR R4, =PMU_PLTR ; ����PLL�ȶ�����ʱ��Ϊ����ֵ50us*100M. 210 LDR R5, =0x00fa00fa 211 STR R5, [ R4 ] 212 213 LDR R4, =PMU_PMDR ; ��SLOWģʽ����NORMALģʽ 214 LDR R5, =0x00000001 215 STR R5, [ R4 ] 216 217 LDR R4, =PMU_PMCR ; ����ϵͳʱ��Ϊ80MHz 218 LDR R5, =0x00004009 ; 400b -- 88M 219 STR R5, [ R4 ] 220 221 ;PMU_PMCR�Ĵ�����15λ��Ҫ�дӵ͵��ߵķ�ת�����ܴ���PLL��ʱ������ 222 LDR R4, =PMU_PMCR 223 LDR R5, =0x0000c009 224 STR R5, [ R4 ] 225 226;**************************************************************** 227;* ��ʼ��EMI 228;**************************************************************** 229 230 IF :DEF:INIT_EMI 231 232 LDR R4, =EMI_CSACONF ; CSAƬѡʱ��������� 233 LDR R5, =0x08a6a6a1 234 STR R5, [ R4 ] 235 236 LDR R4, =EMI_CSECONF ; CSEƬѡʱ���������,������� 237 LDR R5, =0x8cfffff1 238 STR R5, [ R4 ] 239 240 LDR R4, =EMI_SDCONF1 ; SDRAM��������1 241 LDR R5, =0x1E104177 242 STR R5, [ R4 ] 243 244 LDR R4, =EMI_SDCONF2 ; SDRAM��������2 245 LDR R5, =0x80001860 246 STR R5, [ R4 ] 247 248 ENDIF 249 250; Copy Exception Vectors to Internal RAM 251 252 IF :DEF:RAM_INTVEC 253 254 ADR R8, Vectors ; Source 255 LDR R9, =RAM_BASE ; Destination 256 LDMIA R8!, {R0-R7} ; Load Vectors 257 STMIA R9!, {R0-R7} ; Store Vectors 258 LDMIA R8!, {R0-R7} ; Load Handler Addresses 259 STMIA R9!, {R0-R7} ; Store Handler Addresses 260 261 ENDIF 262 263; Remap on-chip RAM to address 0 264 265 IF :DEF:REMAP 266 267 LDR R0, =EMI_REMAPCONF 268 IF :DEF:RAM_INTVEC 269 MOV R1, #0x80000000 270 ELSE 271 MOV R1, #0x0000000b 272 ENDIF 273 STR R1, [R0, #0] ; Remap 274 275 ENDIF 276 277;*************************************************************** 278;* Open irq interrupt 279;*************************************************************** 280 281 MRS R4, cpsr 282 BIC R4, R4, #0x80 ; set bit7 to zero 283 MSR cpsr_c, R4 284 285; Enter the C code 286 IMPORT __main 287 LDR R0,=__main 288 BX R0 289 290 291 IMPORT rt_interrupt_enter 292 IMPORT rt_interrupt_leave 293 IMPORT rt_thread_switch_interrupt_flag 294 IMPORT rt_interrupt_from_thread 295 IMPORT rt_interrupt_to_thread 296 IMPORT rt_hw_trap_irq 297 298IRQ_Handler PROC 299 EXPORT IRQ_Handler 300 STMFD sp!, {r0-r12,lr} 301 BL rt_interrupt_enter 302 BL rt_hw_trap_irq 303 BL rt_interrupt_leave 304 305 ; if rt_thread_switch_interrupt_flag set, jump to 306 ; rt_hw_context_switch_interrupt_do and don't return 307 LDR r0, =rt_thread_switch_interrupt_flag 308 LDR r1, [r0] 309 CMP r1, #1 310 BEQ rt_hw_context_switch_interrupt_do 311 312 LDMFD sp!, {r0-r12,lr} 313 SUBS pc, lr, #4 314 ENDP 315 316; /* 317; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) 318; */ 319rt_hw_context_switch_interrupt_do PROC 320 EXPORT rt_hw_context_switch_interrupt_do 321 MOV r1, #0 ; clear flag 322 STR r1, [r0] 323 324 LDMFD sp!, {r0-r12,lr}; reload saved registers 325 STMFD sp!, {r0-r3} ; save r0-r3 326 MOV r1, sp 327 ADD sp, sp, #16 ; restore sp 328 SUB r2, lr, #4 ; save old task's pc to r2 329 330 MRS r3, spsr ; get cpsr of interrupt thread 331 332 ; switch to SVC mode and no interrupt 333 MSR cpsr_c, #I_Bit :OR F_Bit :OR Mode_SVC 334 335 STMFD sp!, {r2} ; push old task's pc 336 STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 337 MOV r4, r1 ; Special optimised code below 338 MOV r5, r3 339 LDMFD r4!, {r0-r3} 340 STMFD sp!, {r0-r3} ; push old task's r3-r0 341 STMFD sp!, {r5} ; push old task's cpsr 342 MRS r4, spsr 343 STMFD sp!, {r4} ; push old task's spsr 344 345 LDR r4, =rt_interrupt_from_thread 346 LDR r5, [r4] 347 STR sp, [r5] ; store sp in preempted tasks's TCB 348 349 LDR r6, =rt_interrupt_to_thread 350 LDR r6, [r6] 351 LDR sp, [r6] ; get new task's stack pointer 352 353 LDMFD sp!, {r4} ; pop new task's spsr 354 MSR spsr_cxsf, r4 355 LDMFD sp!, {r4} ; pop new task's psr 356 MSR cpsr_cxsf, r4 357 358 LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc 359 ENDP 360 361 362 363 ALIGN 364 IF :DEF:__MICROLIB 365 366 EXPORT __heap_base 367 EXPORT __heap_limit 368 EXPORT __initial_sp 369 370 ELSE ;__MICROLIB 371; User Initial Stack & Heap 372 AREA |.text|, CODE, READONLY 373 374 IMPORT __use_two_region_memory 375 EXPORT __user_initial_stackheap 376__user_initial_stackheap 377 378 LDR R0, = Heap_Mem 379 LDR R1, = (Svc_Stack + Svc_Stack_Size) 380 LDR R2, = (Heap_Mem + Heap_Size) 381 LDR R3, = Svc_Stack 382 BX LR 383 ALIGN 384 ENDIF 385 END 386