xref: /nrf52832-nimble/rt-thread/libcpu/arm/s3c44b0/interrupt.c (revision 104654410c56c573564690304ae786df310c91fc)
1 /*
2  * Copyright (c) 2006-2018, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2006-09-06     XuXinming    first version
9  * 2006-09-15     Bernard      add interrupt bank 0..3 for more effective
10  *                             in irq trap
11  */
12 
13 #include <rtthread.h>
14 #include "s3c44b0.h"
15 
16 #define MAX_HANDLERS	26
17 
18 extern rt_uint32_t rt_interrupt_nest;
19 
20 /* exception and interrupt handler table */
21 rt_isr_handler_t isr_table[MAX_HANDLERS];
22 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
23 rt_uint32_t rt_thread_switch_interrupt_flag;
24 
25 unsigned char interrupt_bank0[256];
26 unsigned char interrupt_bank1[256];
27 unsigned char interrupt_bank2[256];
28 unsigned char interrupt_bank3[256];
29 
30 /**
31  * @addtogroup S3C44B0
32  */
33 /*@{*/
34 
rt_hw_interrupt_handle(int vector)35 void rt_hw_interrupt_handle(int vector)
36 {
37 	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
38 }
39 
40 /**
41  * This function will initialize hardware interrupt
42  */
rt_hw_interrupt_init()43 void rt_hw_interrupt_init()
44 {
45 	register int i;
46 
47 	/* all interrupt disabled include global bit */
48 	INTMSK = 0x07ffffff;
49 
50 	/* clear pending register */
51    	I_ISPC = 0x03ffffff;
52 
53 	/* non-vector mode IRQ enable */
54 	INTCON = 0x5;
55 
56 	/* all IRQ mode */
57 	INTMOD = 0x0;
58 
59 	/* init exceptions table */
60 	for(i=0; i<MAX_HANDLERS; i++)
61 	{
62 		isr_table[i] = rt_hw_interrupt_handle;
63 	}
64 
65 	for ( i = 0; i < 256; i++)
66 	{
67 		interrupt_bank0[i] = 0;
68 		interrupt_bank1[i] = 0;
69 		interrupt_bank2[i] = 0;
70 		interrupt_bank3[i] = 0;
71 	}
72 
73 	/* setup interrupt bank table */
74 	interrupt_bank0[1]	= 0;
75 	interrupt_bank0[2]	= 1;
76 	interrupt_bank0[4]	= 2;
77 	interrupt_bank0[8]	= 3;
78 	interrupt_bank0[16]	= 4;
79 	interrupt_bank0[32]	= 5;
80 	interrupt_bank0[64]	= 6;
81 	interrupt_bank0[128]= 7;
82 
83 	interrupt_bank1[1]	= 8;
84 	interrupt_bank1[2]	= 9;
85 	interrupt_bank1[4]	= 10;
86 	interrupt_bank1[8]	= 11;
87 	interrupt_bank1[16]	= 12;
88 	interrupt_bank1[32]	= 13;
89 	interrupt_bank1[64]	= 14;
90 	interrupt_bank1[128]= 15;
91 
92 	interrupt_bank2[1]	= 16;
93 	interrupt_bank2[2]	= 17;
94 	interrupt_bank2[4]	= 18;
95 	interrupt_bank2[8]	= 19;
96 	interrupt_bank2[16]	= 20;
97 	interrupt_bank2[32]	= 21;
98 	interrupt_bank2[64]	= 22;
99 	interrupt_bank2[128]= 23;
100 
101 	interrupt_bank3[1]	= 24;
102 	interrupt_bank3[2]	= 25;
103 
104 	/* init interrupt nest, and context in thread sp */
105 	rt_interrupt_nest = 0;
106 	rt_interrupt_from_thread = 0;
107 	rt_interrupt_to_thread = 0;
108 	rt_thread_switch_interrupt_flag = 0;
109 }
110 
111 /**
112  * This function will mask a interrupt.
113  * @param vector the interrupt number
114  */
rt_hw_interrupt_mask(int vector)115 void rt_hw_interrupt_mask(int vector)
116 {
117 	INTMSK |= 1 << vector;
118 }
119 
120 /**
121  * This function will un-mask a interrupt.
122  * @param vector the interrupt number
123  */
rt_hw_interrupt_umask(int vector)124 void rt_hw_interrupt_umask(int vector)
125 {
126 	INTMSK &= ~(1 << vector);
127 }
128 
129 /**
130  * This function will install a interrupt service routine to a interrupt.
131  * @param vector the interrupt number
132  * @param new_handler the interrupt service routine to be installed
133  * @param old_handler the old interrupt service routine
134  */
rt_hw_interrupt_install(int vector,rt_isr_handler_t new_handler,rt_isr_handler_t * old_handler)135 void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
136 {
137 	if(vector < MAX_HANDLERS)
138 	{
139 		if (old_handler != RT_NULL) *old_handler = isr_table[vector];
140 		if (new_handler != RT_NULL) isr_table[vector] = new_handler;
141 	}
142 }
143 
144 /*@}*/
145