1/* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2013-07-05 Bernard the first version 9 */ 10 11.globl rt_cpu_get_smp_id 12rt_cpu_get_smp_id: 13 mrc p15, #0, r0, c0, c0, #5 14 bx lr 15 16.globl rt_cpu_vector_set_base 17rt_cpu_vector_set_base: 18 mcr p15, #0, r0, c12, c0, #0 19 dsb 20 bx lr 21 22.globl rt_hw_cpu_dcache_enable 23rt_hw_cpu_dcache_enable: 24 mrc p15, #0, r0, c1, c0, #0 25 orr r0, r0, #0x00000004 26 mcr p15, #0, r0, c1, c0, #0 27 bx lr 28 29.globl rt_hw_cpu_icache_enable 30rt_hw_cpu_icache_enable: 31 mrc p15, #0, r0, c1, c0, #0 32 orr r0, r0, #0x00001000 33 mcr p15, #0, r0, c1, c0, #0 34 bx lr 35 36_FLD_MAX_WAY: 37 .word 0x3ff 38_FLD_MAX_IDX: 39 .word 0x7ff 40 41.globl rt_cpu_dcache_clean_flush 42rt_cpu_dcache_clean_flush: 43 push {r4-r11} 44 dmb 45 mrc p15, #1, r0, c0, c0, #1 @ read clid register 46 ands r3, r0, #0x7000000 @ get level of coherency 47 mov r3, r3, lsr #23 48 beq finished 49 mov r10, #0 50loop1: 51 add r2, r10, r10, lsr #1 52 mov r1, r0, lsr r2 53 and r1, r1, #7 54 cmp r1, #2 55 blt skip 56 mcr p15, #2, r10, c0, c0, #0 57 isb 58 mrc p15, #1, r1, c0, c0, #0 59 and r2, r1, #7 60 add r2, r2, #4 61 ldr r4, _FLD_MAX_WAY 62 ands r4, r4, r1, lsr #3 63 clz r5, r4 64 ldr r7, _FLD_MAX_IDX 65 ands r7, r7, r1, lsr #13 66loop2: 67 mov r9, r4 68loop3: 69 orr r11, r10, r9, lsl r5 70 orr r11, r11, r7, lsl r2 71 mcr p15, #0, r11, c7, c14, #2 72 subs r9, r9, #1 73 bge loop3 74 subs r7, r7, #1 75 bge loop2 76skip: 77 add r10, r10, #2 78 cmp r3, r10 79 bgt loop1 80 81finished: 82 dsb 83 isb 84 pop {r4-r11} 85 bx lr 86 87.globl rt_hw_cpu_dcache_disable 88rt_hw_cpu_dcache_disable: 89 push {r4-r11, lr} 90 bl rt_cpu_dcache_clean_flush 91 mrc p15, #0, r0, c1, c0, #0 92 bic r0, r0, #0x00000004 93 mcr p15, #0, r0, c1, c0, #0 94 pop {r4-r11, lr} 95 bx lr 96 97.globl rt_hw_cpu_icache_disable 98rt_hw_cpu_icache_disable: 99 mrc p15, #0, r0, c1, c0, #0 100 bic r0, r0, #0x00001000 101 mcr p15, #0, r0, c1, c0, #0 102 bx lr 103 104.globl rt_cpu_mmu_disable 105rt_cpu_mmu_disable: 106 mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb 107 mrc p15, #0, r0, c1, c0, #0 108 bic r0, r0, #1 109 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit 110 dsb 111 bx lr 112 113.globl rt_cpu_mmu_enable 114rt_cpu_mmu_enable: 115 mrc p15, #0, r0, c1, c0, #0 116 orr r0, r0, #0x001 117 mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit 118 dsb 119 bx lr 120 121.globl rt_cpu_tlb_set 122rt_cpu_tlb_set: 123 mcr p15, #0, r0, c2, c0, #0 124 dmb 125 bx lr 126