1;/* 2; * Copyright (c) 2006-2018, RT-Thread Development Team 3; * 4; * SPDX-License-Identifier: Apache-2.0 5; * 6; * Change Logs: 7; * Date Author Notes 8; * 2009-01-20 Bernard first version 9; * 2011-07-22 Bernard added thumb mode porting 10; */ 11 12Mode_USR EQU 0x10 13Mode_FIQ EQU 0x11 14Mode_IRQ EQU 0x12 15Mode_SVC EQU 0x13 16Mode_ABT EQU 0x17 17Mode_UND EQU 0x1B 18Mode_SYS EQU 0x1F 19 20I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled 21F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled 22 23NOINT EQU 0xc0 ; disable interrupt in psr 24 25 AREA |.text|, CODE, READONLY, ALIGN=2 26 ARM 27 REQUIRE8 28 PRESERVE8 29 30;/* 31; * rt_base_t rt_hw_interrupt_disable(); 32; */ 33rt_hw_interrupt_disable PROC 34 EXPORT rt_hw_interrupt_disable 35 MRS r0, cpsr 36 ORR r1, r0, #NOINT 37 MSR cpsr_c, r1 38 BX lr 39 ENDP 40 41;/* 42; * void rt_hw_interrupt_enable(rt_base_t level); 43; */ 44rt_hw_interrupt_enable PROC 45 EXPORT rt_hw_interrupt_enable 46 MSR cpsr_c, r0 47 BX lr 48 ENDP 49 50;/* 51; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); 52; * r0 --> from 53; * r1 --> to 54; */ 55rt_hw_context_switch PROC 56 EXPORT rt_hw_context_switch 57 STMFD sp!, {lr} ; push pc (lr should be pushed in place of PC) 58 STMFD sp!, {r0-r12, lr} ; push lr & register file 59 60 MRS r4, cpsr 61 TST lr, #0x01 62 BEQ _ARM_MODE 63 ORR r4, r4, #0x20 ; it's thumb code 64_ARM_MODE 65 STMFD sp!, {r4} ; push cpsr 66 67 STR sp, [r0] ; store sp in preempted tasks TCB 68 LDR sp, [r1] ; get new task stack pointer 69 70 LDMFD sp!, {r4} ; pop new task cpsr to spsr 71 MSR spsr_cxsf, r4 72 BIC r4, r4, #0x20 ; must be ARM mode 73 MSR cpsr_cxsf, r4 74 75 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr 76 ENDP 77 78;/* 79; * void rt_hw_context_switch_to(rt_uint32 to); 80; * r0 --> to 81; */ 82rt_hw_context_switch_to PROC 83 EXPORT rt_hw_context_switch_to 84 LDR sp, [r0] ; get new task stack pointer 85 86 LDMFD sp!, {r4} ; pop new task cpsr to spsr 87 MSR spsr_cxsf, r4 88 BIC r4, r4, #0x20 ; must be ARM mode 89 MSR cpsr_cxsf, r4 90 91 LDMFD sp!, {r0-r12, lr, pc}^ ; pop new task r0-r12, lr & pc, copy spsr to cpsr 92 ENDP 93 94;/* 95; * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); 96; */ 97 IMPORT rt_thread_switch_interrupt_flag 98 IMPORT rt_interrupt_from_thread 99 IMPORT rt_interrupt_to_thread 100 101rt_hw_context_switch_interrupt PROC 102 EXPORT rt_hw_context_switch_interrupt 103 LDR r2, =rt_thread_switch_interrupt_flag 104 LDR r3, [r2] 105 CMP r3, #1 106 BEQ _reswitch 107 MOV r3, #1 ; set rt_thread_switch_interrupt_flag to 1 108 STR r3, [r2] 109 LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread 110 STR r0, [r2] 111_reswitch 112 LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread 113 STR r1, [r2] 114 BX lr 115 ENDP 116 117; /* 118; * void rt_hw_context_switch_interrupt_do(rt_base_t flag) 119; */ 120rt_hw_context_switch_interrupt_do PROC 121 EXPORT rt_hw_context_switch_interrupt_do 122 MOV r1, #0 ; clear flag 123 STR r1, [r0] 124 125 LDMFD sp!, {r0-r12,lr}; reload saved registers 126 STMFD sp!, {r0-r3} ; save r0-r3 127 MOV r1, sp 128 ADD sp, sp, #16 ; restore sp 129 SUB r2, lr, #4 ; save old task's pc to r2 130 131 MRS r3, spsr ; get cpsr of interrupt thread 132 133 ; switch to SVC mode and no interrupt 134 MSR cpsr_c, #I_Bit:OR:F_Bit:OR:Mode_SVC 135 136 STMFD sp!, {r2} ; push old task's pc 137 STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4 138 MOV r4, r1 ; Special optimised code below 139 MOV r5, r3 140 LDMFD r4!, {r0-r3} 141 STMFD sp!, {r0-r3} ; push old task's r3-r0 142 STMFD sp!, {r5} ; push old task's cpsr 143 144 LDR r4, =rt_interrupt_from_thread 145 LDR r5, [r4] 146 STR sp, [r5] ; store sp in preempted tasks's TCB 147 148 LDR r6, =rt_interrupt_to_thread 149 LDR r6, [r6] 150 LDR sp, [r6] ; get new task's stack pointer 151 152 LDMFD sp!, {r4} ; pop new task's cpsr to spsr 153 MSR spsr_cxsf, r4 154 BIC r4, r4, #0x20 ; must be ARM mode 155 MSR cpsr_cxsf, r4 156 157 LDMFD sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr 158 ENDP 159 160 END