1*10465441SEvalZero /*
2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team
3*10465441SEvalZero *
4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0
5*10465441SEvalZero *
6*10465441SEvalZero * Change Logs:
7*10465441SEvalZero * Date Author Notes
8*10465441SEvalZero * 2008-12-11 XuXinming first version
9*10465441SEvalZero * 2013-05-24 Grissiom port to RM48x50
10*10465441SEvalZero */
11*10465441SEvalZero
12*10465441SEvalZero #include <rtthread.h>
13*10465441SEvalZero
14*10465441SEvalZero /**
15*10465441SEvalZero * @addtogroup RM48x50
16*10465441SEvalZero */
17*10465441SEvalZero /*@{*/
18*10465441SEvalZero
19*10465441SEvalZero /**
20*10465441SEvalZero * this function will reset CPU
21*10465441SEvalZero *
22*10465441SEvalZero */
rt_hw_cpu_reset()23*10465441SEvalZero void rt_hw_cpu_reset()
24*10465441SEvalZero {
25*10465441SEvalZero }
26*10465441SEvalZero
27*10465441SEvalZero /**
28*10465441SEvalZero * this function will shutdown CPU
29*10465441SEvalZero *
30*10465441SEvalZero */
rt_hw_cpu_shutdown()31*10465441SEvalZero void rt_hw_cpu_shutdown()
32*10465441SEvalZero {
33*10465441SEvalZero rt_kprintf("shutdown...\n");
34*10465441SEvalZero
35*10465441SEvalZero while (1);
36*10465441SEvalZero }
37*10465441SEvalZero
38*10465441SEvalZero #ifdef __TI_COMPILER_VERSION__
39*10465441SEvalZero #ifdef RT_USING_CPU_FFS
__rt_ffs(int value)40*10465441SEvalZero int __rt_ffs(int value)
41*10465441SEvalZero {
42*10465441SEvalZero if (value == 0)
43*10465441SEvalZero return value;
44*10465441SEvalZero
45*10465441SEvalZero __asm(" rsb r1, r0, #0");
46*10465441SEvalZero __asm(" and r1, r1, r0");
47*10465441SEvalZero __asm(" clz r1, r1");
48*10465441SEvalZero __asm(" rsb r0, r1, #32");
49*10465441SEvalZero }
50*10465441SEvalZero #endif
51*10465441SEvalZero
rt_hw_cpu_icache_enable()52*10465441SEvalZero void rt_hw_cpu_icache_enable()
53*10465441SEvalZero {
54*10465441SEvalZero __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
55*10465441SEvalZero __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable");
56*10465441SEvalZero __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored");
57*10465441SEvalZero __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache");
58*10465441SEvalZero __asm(" ISB");
59*10465441SEvalZero }
60*10465441SEvalZero
rt_hw_cpu_icache_disable()61*10465441SEvalZero void rt_hw_cpu_icache_disable()
62*10465441SEvalZero {
63*10465441SEvalZero __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
64*10465441SEvalZero __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable");
65*10465441SEvalZero __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache");
66*10465441SEvalZero __asm(" ISB");
67*10465441SEvalZero }
68*10465441SEvalZero
rt_hw_cpu_dcache_enable()69*10465441SEvalZero void rt_hw_cpu_dcache_enable()
70*10465441SEvalZero {
71*10465441SEvalZero __asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data");
72*10465441SEvalZero __asm(" ORR R1, R1, #0x1 <<2");
73*10465441SEvalZero __asm(" DSB");
74*10465441SEvalZero __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache");
75*10465441SEvalZero __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache");
76*10465441SEvalZero }
77*10465441SEvalZero
rt_hw_cpu_dcache_disable()78*10465441SEvalZero void rt_hw_cpu_dcache_disable()
79*10465441SEvalZero {
80*10465441SEvalZero /* FIXME: Clean entire data cache. This routine depends on the data cache
81*10465441SEvalZero * size. It can be omitted if it is known that the data cache has no dirty
82*10465441SEvalZero * data. */
83*10465441SEvalZero __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
84*10465441SEvalZero __asm(" BIC r1, r1, #0x1 <<2");
85*10465441SEvalZero __asm(" DSB");
86*10465441SEvalZero __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache");
87*10465441SEvalZero }
88*10465441SEvalZero
89*10465441SEvalZero #elif __GNUC__
__rt_ffs(int value)90*10465441SEvalZero int __rt_ffs(int value)
91*10465441SEvalZero {
92*10465441SEvalZero return __builtin_ffs(value);
93*10465441SEvalZero }
94*10465441SEvalZero #endif
95*10465441SEvalZero /*@}*/
96