1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2008-12-11 XuXinming first version
9 * 2013-05-24 Grissiom port to RM48x50
10 */
11
12 #include <rtthread.h>
13
14 /**
15 * @addtogroup RM48x50
16 */
17 /*@{*/
18
19 /**
20 * this function will reset CPU
21 *
22 */
rt_hw_cpu_reset()23 void rt_hw_cpu_reset()
24 {
25 }
26
27 /**
28 * this function will shutdown CPU
29 *
30 */
rt_hw_cpu_shutdown()31 void rt_hw_cpu_shutdown()
32 {
33 rt_kprintf("shutdown...\n");
34
35 while (1);
36 }
37
38 #ifdef __TI_COMPILER_VERSION__
39 #ifdef RT_USING_CPU_FFS
__rt_ffs(int value)40 int __rt_ffs(int value)
41 {
42 if (value == 0)
43 return value;
44
45 __asm(" rsb r1, r0, #0");
46 __asm(" and r1, r1, r0");
47 __asm(" clz r1, r1");
48 __asm(" rsb r0, r1, #32");
49 }
50 #endif
51
rt_hw_cpu_icache_enable()52 void rt_hw_cpu_icache_enable()
53 {
54 __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
55 __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable");
56 __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored");
57 __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache");
58 __asm(" ISB");
59 }
60
rt_hw_cpu_icache_disable()61 void rt_hw_cpu_icache_disable()
62 {
63 __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
64 __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable");
65 __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache");
66 __asm(" ISB");
67 }
68
rt_hw_cpu_dcache_enable()69 void rt_hw_cpu_dcache_enable()
70 {
71 __asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data");
72 __asm(" ORR R1, R1, #0x1 <<2");
73 __asm(" DSB");
74 __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache");
75 __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache");
76 }
77
rt_hw_cpu_dcache_disable()78 void rt_hw_cpu_dcache_disable()
79 {
80 /* FIXME: Clean entire data cache. This routine depends on the data cache
81 * size. It can be omitted if it is known that the data cache has no dirty
82 * data. */
83 __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
84 __asm(" BIC r1, r1, #0x1 <<2");
85 __asm(" DSB");
86 __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache");
87 }
88
89 #elif __GNUC__
__rt_ffs(int value)90 int __rt_ffs(int value)
91 {
92 return __builtin_ffs(value);
93 }
94 #endif
95 /*@}*/
96