1;/* 2; * Copyright (c) 2006-2018, RT-Thread Development Team 3; * 4; * SPDX-License-Identifier: Apache-2.0 5; * 6; * Change Logs: 7; * Date Author Notes 8; * 2010-01-25 Bernard first version 9; * 2012-06-01 aozima set pendsv priority to 0xFF. 10; * 2012-08-17 aozima fixed bug: store r8 - r11. 11; * 2013-06-18 aozima add restore MSP feature. 12; */ 13 14;/** 15; * @addtogroup CORTEX-M0 16; */ 17;/*@{*/ 18 19SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register 20NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register 21NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) 22NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) 23NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception 24 25 SECTION .text:CODE(2) 26 THUMB 27 REQUIRE8 28 PRESERVE8 29 30 IMPORT rt_thread_switch_interrupt_flag 31 IMPORT rt_interrupt_from_thread 32 IMPORT rt_interrupt_to_thread 33 34;/* 35; * rt_base_t rt_hw_interrupt_disable(); 36; */ 37 EXPORT rt_hw_interrupt_disable 38rt_hw_interrupt_disable: 39 MRS r0, PRIMASK 40 CPSID I 41 BX LR 42 43;/* 44; * void rt_hw_interrupt_enable(rt_base_t level); 45; */ 46 EXPORT rt_hw_interrupt_enable 47rt_hw_interrupt_enable: 48 MSR PRIMASK, r0 49 BX LR 50 51;/* 52; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); 53; * r0 --> from 54; * r1 --> to 55; */ 56 EXPORT rt_hw_context_switch_interrupt 57 EXPORT rt_hw_context_switch 58rt_hw_context_switch_interrupt: 59rt_hw_context_switch: 60 ; set rt_thread_switch_interrupt_flag to 1 61 LDR r2, =rt_thread_switch_interrupt_flag 62 LDR r3, [r2] 63 CMP r3, #1 64 BEQ _reswitch 65 MOVS r3, #0x1 66 STR r3, [r2] 67 68 LDR r2, =rt_interrupt_from_thread ; set rt_interrupt_from_thread 69 STR r0, [r2] 70 71_reswitch 72 LDR r2, =rt_interrupt_to_thread ; set rt_interrupt_to_thread 73 STR r1, [r2] 74 75 LDR r0, =NVIC_INT_CTRL ; trigger the PendSV exception (causes context switch) 76 LDR r1, =NVIC_PENDSVSET 77 STR r1, [r0] 78 BX LR 79 80; r0 --> switch from thread stack 81; r1 --> switch to thread stack 82; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack 83 EXPORT PendSV_Handler 84PendSV_Handler: 85 86 ; disable interrupt to protect context switch 87 MRS r2, PRIMASK 88 CPSID I 89 90 ; get rt_thread_switch_interrupt_flag 91 LDR r0, =rt_thread_switch_interrupt_flag 92 LDR r1, [r0] 93 CMP r1, #0x00 94 BEQ pendsv_exit ; pendsv already handled 95 96 ; clear rt_thread_switch_interrupt_flag to 0 97 MOVS r1, #0x00 98 STR r1, [r0] 99 100 LDR r0, =rt_interrupt_from_thread 101 LDR r1, [r0] 102 CMP r1, #0x00 103 BEQ switch_to_thread ; skip register save at the first time 104 105 MRS r1, psp ; get from thread stack pointer 106 107 SUBS r1, r1, #0x20 ; space for {r4 - r7} and {r8 - r11} 108 LDR r0, [r0] 109 STR r1, [r0] ; update from thread stack pointer 110 111 STMIA r1!, {r4 - r7} ; push thread {r4 - r7} register to thread stack 112 113 MOV r4, r8 ; mov thread {r8 - r11} to {r4 - r7} 114 MOV r5, r9 115 MOV r6, r10 116 MOV r7, r11 117 STMIA r1!, {r4 - r7} ; push thread {r8 - r11} high register to thread stack 118 119switch_to_thread 120 LDR r1, =rt_interrupt_to_thread 121 LDR r1, [r1] 122 LDR r1, [r1] ; load thread stack pointer 123 124 LDMIA r1!, {r4 - r7} ; pop thread {r4 - r7} register from thread stack 125 PUSH {r4 - r7} ; push {r4 - r7} to MSP for copy {r8 - r11} 126 127 LDMIA r1!, {r4 - r7} ; pop thread {r8 - r11} high register from thread stack to {r4 - r7} 128 MOV r8, r4 ; mov {r4 - r7} to {r8 - r11} 129 MOV r9, r5 130 MOV r10, r6 131 MOV r11, r7 132 133 POP {r4 - r7} ; pop {r4 - r7} from MSP 134 135 MSR psp, r1 ; update stack pointer 136 137pendsv_exit 138 ; restore interrupt 139 MSR PRIMASK, r2 140 141 MOVS r0, #0x04 142 RSBS r0, r0, #0x00 143 BX r0 144 145;/* 146; * void rt_hw_context_switch_to(rt_uint32 to); 147; * r0 --> to 148; * this fucntion is used to perform the first thread switch 149; */ 150 EXPORT rt_hw_context_switch_to 151rt_hw_context_switch_to: 152 ; set to thread 153 LDR r1, =rt_interrupt_to_thread 154 STR r0, [r1] 155 156 ; set from thread to 0 157 LDR r1, =rt_interrupt_from_thread 158 MOVS r0, #0x0 159 STR r0, [r1] 160 161 ; set interrupt flag to 1 162 LDR r1, =rt_thread_switch_interrupt_flag 163 MOVS r0, #1 164 STR r0, [r1] 165 166 ; set the PendSV exception priority 167 LDR r0, =NVIC_SHPR3 168 LDR r1, =NVIC_PENDSV_PRI 169 LDR r2, [r0,#0x00] ; read 170 ORRS r1,r1,r2 ; modify 171 STR r1, [r0] ; write-back 172 173 ; trigger the PendSV exception (causes context switch) 174 LDR r0, =NVIC_INT_CTRL 175 LDR r1, =NVIC_PENDSVSET 176 STR r1, [r0] 177 NOP 178 179 ; restore MSP 180 LDR r0, =SCB_VTOR 181 LDR r0, [r0] 182 LDR r0, [r0] 183 NOP 184 MSR msp, r0 185 186 ; enable interrupts at processor level 187 CPSIE I 188 189 ; never reach here! 190 191; compatible with old version 192 EXPORT rt_hw_interrupt_thread_switch 193rt_hw_interrupt_thread_switch: 194 BX lr 195 196 IMPORT rt_hw_hard_fault_exception 197 EXPORT HardFault_Handler 198HardFault_Handler: 199 200 ; get current context 201 MRS r0, psp ; get fault thread stack pointer 202 PUSH {lr} 203 BL rt_hw_hard_fault_exception 204 POP {pc} 205 206 END 207