1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2014-11-07 weety first version 9 */ 10 11 #ifndef __VFP_H__ 12 #define __VFP_H__ 13 14 /* FPSID register bits */ 15 #define FPSID_IMPLEMENTER_BIT (24) 16 #define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT) 17 #define FPSID_SW (1 << 23) 18 #define FPSID_FORMAT_BIT (21) 19 #define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT) 20 #define FPSID_NODOUBLE (1 << 20) 21 #define FPSID_ARCH_BIT (16) 22 #define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT) 23 #define FPSID_PART_BIT (8) 24 #define FPSID_PART_MASK (0xFF << FPSID_PART_BIT) 25 #define FPSID_VARIANT_BIT (4) 26 #define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT) 27 #define FPSID_REVISION_BIT (0) 28 #define FPSID_REVISION_MASK (0xF << FPSID_REVISION_BIT) 29 30 /* FPSCR register bits */ 31 #define FPSCR_DN (1<<25) /* Default NaN mode enable bit */ 32 #define FPSCR_FZ (1<<24) /* Flush-to-zero mode enable bit */ 33 #define FPSCR_RN (0<<22) /* Round to nearest (RN) mode */ 34 #define FPSCR_RP (1<<22) /* Round towards plus infinity (RP) mode */ 35 #define FPSCR_RM (2<<22) /* Round towards minus infinity (RM) mode */ 36 #define FPSCR_RZ (3<<22) /* Round towards zero (RZ) mode */ 37 #define FPSCR_RMODE_BIT (22) 38 #define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT) 39 #define FPSCR_STRIDE_BIT (20) 40 #define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT) 41 #define FPSCR_LENGTH_BIT (16) 42 #define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT) 43 #define FPSCR_IDE (1<<15) /* Input Subnormal exception trap enable bit */ 44 #define FPSCR_IXE (1<<12) /* Inexact exception trap enable bit */ 45 #define FPSCR_UFE (1<<11) /* Underflow exception trap enable bit */ 46 #define FPSCR_OFE (1<<10) /* Overflow exception trap enable bit */ 47 #define FPSCR_DZE (1<<9) /* Division by Zero exception trap enable bit */ 48 #define FPSCR_IOE (1<<8) /* Invalid Operation exception trap enable bit */ 49 #define FPSCR_IDC (1<<7) /* Input Subnormal cumulative exception flag */ 50 #define FPSCR_IXC (1<<4) /* Inexact cumulative exception flag */ 51 #define FPSCR_UFC (1<<3) /* Underflow cumulative exception flag */ 52 #define FPSCR_OFC (1<<2) /* Overflow cumulative exception flag */ 53 #define FPSCR_DZC (1<<1) /* Division by Zero cumulative exception flag */ 54 #define FPSCR_IOC (1<<0) /* Invalid Operation cumulative exception flag */ 55 56 /* FPEXC register bits */ 57 #define FPEXC_EX (1 << 31) /* When EX is set, the VFP coprocessor is in the exceptional state */ 58 #define FPEXC_EN (1 << 30) /* VFP enable bit */ 59 #define FPEXC_DEX (1 << 29) /* Defined synchronous instruction exceptional flag */ 60 #define FPEXC_FP2V (1 << 28) /* FPINST2 instruction valid flag */ 61 #define FPEXC_LENGTH_BIT (8) 62 #define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT) 63 #define FPEXC_INV (1 << 7) /* Input exception flag */ 64 #define FPEXC_UFC (1 << 3) /* Potential underflow flag */ 65 #define FPEXC_OFC (1 << 2) /* Potential overflow flag */ 66 #define FPEXC_IOC (1 << 0) /* Potential invalid operation flag */ 67 #define FPEXC_TRAP_MASK (FPEXC_INV|FPEXC_UFC|FPEXC_OFC|FPEXC_IOC) 68 69 70 /* MVFR0 register bits */ 71 #define MVFR0_A_SIMD_BIT (0) 72 #define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT) 73 74 75 /* thread switch micro */ 76 #define THREAD_INIT 0 77 #define THREAD_EXIT 1 78 79 /* 80 * get VFP register 81 */ 82 83 #define vmrs(vfp) ({ \ 84 rt_uint32_t var; \ 85 asm("vmrs %0, "#vfp"" : "=r" (var) : : "cc"); \ 86 var; \ 87 }) 88 89 #define vmsr(vfp, var) \ 90 asm("vmsr "#vfp", %0" \ 91 : : "r" (var) : "cc") 92 93 94 #endif 95 96 97