1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 10 #ifndef __MMU_H__ 11 #define __MMU_H__ 12 13 #include <rtthread.h> 14 15 #define CACHE_LINE_SIZE 32 16 17 /* 18 * Hardware page table definitions. 19 * 20 * + Level 1 descriptor (PGD) 21 * - common 22 */ 23 #define PGD_TYPE_MASK (3 << 0) 24 #define PGD_TYPE_FAULT (0 << 0) 25 #define PGD_TYPE_TABLE (1 << 0) 26 #define PGD_TYPE_SECT (2 << 0) 27 #define PGD_BIT4 (1 << 4) 28 #define PGD_DOMAIN(x) ((x) << 5) 29 #define PGD_PROTECTION (1 << 9) /* ARMv5 */ 30 /* 31 * - section 32 */ 33 #define PGD_SECT_BUFFERABLE (1 << 2) 34 #define PGD_SECT_CACHEABLE (1 << 3) 35 #define PGD_SECT_XN (1 << 4) /* ARMv6 */ 36 #define PGD_SECT_AP0 (1 << 10) 37 #define PGD_SECT_AP1 (1 << 11) 38 #define PGD_SECT_TEX(x) ((x) << 12) /* ARMv5 */ 39 #define PGD_SECT_APX (1 << 15) /* ARMv6 */ 40 #define PGD_SECT_S (1 << 16) /* ARMv6 */ 41 #define PGD_SECT_nG (1 << 17) /* ARMv6 */ 42 #define PGD_SECT_SUPER (1 << 18) /* ARMv6 */ 43 44 #define PGD_SECT_UNCACHED (0) 45 #define PGD_SECT_BUFFERED (PGD_SECT_BUFFERABLE) 46 #define PGD_SECT_WT (PGD_SECT_CACHEABLE) 47 #define PGD_SECT_WB (PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) 48 #define PGD_SECT_MINICACHE (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE) 49 #define PGD_SECT_WBWA (PGD_SECT_TEX(1) | PGD_SECT_CACHEABLE | PGD_SECT_BUFFERABLE) 50 #define PGD_SECT_NONSHARED_DEV (PGD_SECT_TEX(2)) 51 52 53 /* 54 * + Level 2 descriptor (PTE) 55 * - common 56 */ 57 #define PTE_TYPE_MASK (3 << 0) 58 #define PTE_TYPE_FAULT (0 << 0) 59 #define PTE_TYPE_LARGE (1 << 0) 60 #define PTE_TYPE_SMALL (2 << 0) 61 #define PTE_TYPE_EXT (3 << 0) /* ARMv5 */ 62 #define PTE_BUFFERABLE (1 << 2) 63 #define PTE_CACHEABLE (1 << 3) 64 65 /* 66 * - extended small page/tiny page 67 */ 68 #define PTE_EXT_XN (1 << 0) /* ARMv6 */ 69 #define PTE_EXT_AP_MASK (3 << 4) 70 #define PTE_EXT_AP0 (1 << 4) 71 #define PTE_EXT_AP1 (2 << 4) 72 #define PTE_EXT_AP_UNO_SRO (0 << 4) 73 #define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) 74 #define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) 75 #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) 76 #define PTE_EXT_TEX(x) ((x) << 6) /* ARMv5 */ 77 #define PTE_EXT_APX (1 << 9) /* ARMv6 */ 78 #define PTE_EXT_SHARED (1 << 10) /* ARMv6 */ 79 #define PTE_EXT_NG (1 << 11) /* ARMv6 */ 80 81 /* 82 * - small page 83 */ 84 #define PTE_SMALL_AP_MASK (0xff << 4) 85 #define PTE_SMALL_AP_UNO_SRO (0x00 << 4) 86 #define PTE_SMALL_AP_UNO_SRW (0x55 << 4) 87 #define PTE_SMALL_AP_URO_SRW (0xaa << 4) 88 #define PTE_SMALL_AP_URW_SRW (0xff << 4) 89 90 91 /* 92 * sector table properities 93 */ 94 #define SECT_CB (PGD_SECT_CACHEABLE|PGD_SECT_BUFFERABLE) //cache_on, write_back 95 #define SECT_CNB (PGD_SECT_CACHEABLE) //cache_on, write_through 96 #define SECT_NCB (PGD_SECT_BUFFERABLE) //cache_off,WR_BUF on 97 #define SECT_NCNB (0 << 2) //cache_off,WR_BUF off 98 99 #define SECT_AP_RW (PGD_SECT_AP0|PGD_SECT_AP1) //supervisor=RW, user=RW 100 #define SECT_AP_RO (PGD_SECT_AP0|PGD_SECT_AP1|PGD_SECT_APX) //supervisor=RO, user=RO 101 102 #define SECT_RWX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read/Write/executable, cache, write back */ 103 #define SECT_RWX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read/Write/executable, cache, write through */ 104 #define SECT_RWX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read/Write/executable without cache and write buffer */ 105 #define SECT_RWX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read/Write without cache and write buffer */ 106 107 #define SECT_RWNX_CB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write back */ 108 #define SECT_RWNX_CNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write, cache, write through */ 109 #define SECT_RWNX_NCNB (SECT_AP_RW|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */ 110 #define SECT_RWNX_FAULT (SECT_AP_RW|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read/Write without cache and write buffer */ 111 112 113 #define SECT_ROX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT) /* Read Only/executable, cache, write back */ 114 #define SECT_ROX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT) /* Read Only/executable, cache, write through */ 115 #define SECT_ROX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT) /* Read Only/executable without cache and write buffer */ 116 #define SECT_ROX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT) /* Read Only without cache and write buffer */ 117 118 #define SECT_RONX_CB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WB|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write back */ 119 #define SECT_RONX_CNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_SECT_WT|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only, cache, write through */ 120 #define SECT_RONX_NCNB (SECT_AP_RO|PGD_DOMAIN(0)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */ 121 #define SECT_RONX_FAULT (SECT_AP_RO|PGD_DOMAIN(1)|PGD_TYPE_SECT|PGD_SECT_XN) /* Read Only without cache and write buffer */ 122 123 #define SECT_TO_PAGE (PGD_DOMAIN(0)|PGD_TYPE_TABLE) /* Level 2 descriptor (PTE) entry properity */ 124 125 /* 126 * page table properities 127 */ 128 #define PAGE_CB (PTE_BUFFERABLE|PTE_CACHEABLE) //cache_on, write_back 129 #define PAGE_CNB (PTE_CACHEABLE) //cache_on, write_through 130 #define PAGE_NCB (PTE_BUFFERABLE) //cache_off,WR_BUF on 131 #define PAGE_NCNB (0 << 2) //cache_off,WR_BUF off 132 133 #define PAGE_AP_RW (PTE_EXT_AP0|PTE_EXT_AP1) //supervisor=RW, user=RW 134 #define PAGE_AP_RO (PTE_EXT_AP0|PTE_EXT_AP1|PTE_EXT_APX) //supervisor=RO, user=RO 135 136 #define PAGE_RWX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write back */ 137 #define PAGE_RWX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL) /* Read/Write/executable, cache, write through */ 138 #define PAGE_RWX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write/executable without cache and write buffer */ 139 #define PAGE_RWX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL) /* Read/Write without cache and write buffer */ 140 141 #define PAGE_RWNX_CB (PAGE_AP_RW|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write back */ 142 #define PAGE_RWNX_CNB (PAGE_AP_RW|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write, cache, write through */ 143 #define PAGE_RWNX_NCNB (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */ 144 #define PAGE_RWNX_FAULT (PAGE_AP_RW|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read/Write without cache and write buffer */ 145 146 147 #define PAGE_ROX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write back */ 148 #define PAGE_ROX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL) /* Read Only/executable, cache, write through */ 149 #define PAGE_ROX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only/executable without cache and write buffer */ 150 #define PAGE_ROX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ 151 152 #define PAGE_RONX_CB (PAGE_AP_RO|PAGE_CB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write back */ 153 #define PAGE_RONX_CNB (PAGE_AP_RO|PAGE_CNB|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only, cache, write through */ 154 #define PAGE_RONX_NCNB (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ 155 #define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ 156 157 158 #define DESC_SEC (0x2|(1<<4)) 159 #define CB (3<<2) //cache_on, write_back 160 #define CNB (2<<2) //cache_on, write_through 161 #define NCB (1<<2) //cache_off,WR_BUF on 162 #define NCNB (0<<2) //cache_off,WR_BUF off 163 #define AP_RW (3<<10) //supervisor=RW, user=RW 164 #define AP_RO (2<<10) //supervisor=RW, user=RO 165 166 #define DOMAIN_FAULT (0x0) 167 #define DOMAIN_CHK (0x1) 168 #define DOMAIN_NOTCHK (0x3) 169 #define DOMAIN0 (0x0<<5) 170 #define DOMAIN1 (0x1<<5) 171 172 #define DOMAIN0_ATTR (DOMAIN_CHK<<0) 173 #define DOMAIN1_ATTR (DOMAIN_FAULT<<2) 174 175 #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ 176 #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ 177 #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 178 #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 179 180 struct mem_desc { 181 rt_uint32_t vaddr_start; 182 rt_uint32_t vaddr_end; 183 rt_uint32_t paddr_start; 184 rt_uint32_t sect_attr; /* when page mapped */ 185 rt_uint32_t page_attr; /* only sector mapped valid */ 186 rt_uint32_t mapped_mode; 187 #define SECT_MAPPED 0 188 #define PAGE_MAPPED 1 189 }; 190 191 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); 192 193 #endif 194 195