1*10465441SEvalZero /* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero */ 9*10465441SEvalZero 10*10465441SEvalZero #ifndef __MMU_H__ 11*10465441SEvalZero #define __MMU_H__ 12*10465441SEvalZero 13*10465441SEvalZero #include <rtthread.h> 14*10465441SEvalZero 15*10465441SEvalZero #define CACHE_LINE_SIZE 32 16*10465441SEvalZero 17*10465441SEvalZero #define DESC_SEC (0x2|(1<<4)) 18*10465441SEvalZero #define CB (3<<2) //cache_on, write_back 19*10465441SEvalZero #define CNB (2<<2) //cache_on, write_through 20*10465441SEvalZero #define NCB (1<<2) //cache_off,WR_BUF on 21*10465441SEvalZero #define NCNB (0<<2) //cache_off,WR_BUF off 22*10465441SEvalZero #define AP_RW (3<<10) //supervisor=RW, user=RW 23*10465441SEvalZero #define AP_RO (2<<10) //supervisor=RW, user=RO 24*10465441SEvalZero 25*10465441SEvalZero #define DOMAIN_FAULT (0x0) 26*10465441SEvalZero #define DOMAIN_CHK (0x1) 27*10465441SEvalZero #define DOMAIN_NOTCHK (0x3) 28*10465441SEvalZero #define DOMAIN0 (0x0<<5) 29*10465441SEvalZero #define DOMAIN1 (0x1<<5) 30*10465441SEvalZero 31*10465441SEvalZero #define DOMAIN0_ATTR (DOMAIN_CHK<<0) 32*10465441SEvalZero #define DOMAIN1_ATTR (DOMAIN_FAULT<<2) 33*10465441SEvalZero 34*10465441SEvalZero #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ 35*10465441SEvalZero #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ 36*10465441SEvalZero #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 37*10465441SEvalZero #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 38*10465441SEvalZero 39*10465441SEvalZero struct mem_desc 40*10465441SEvalZero { 41*10465441SEvalZero rt_uint32_t vaddr_start; 42*10465441SEvalZero rt_uint32_t vaddr_end; 43*10465441SEvalZero rt_uint32_t paddr_start; 44*10465441SEvalZero rt_uint32_t attr; 45*10465441SEvalZero }; 46*10465441SEvalZero 47*10465441SEvalZero void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); 48*10465441SEvalZero 49*10465441SEvalZero #endif 50