1 /* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 */ 9 10 #ifndef __MMU_H__ 11 #define __MMU_H__ 12 13 #include <rtthread.h> 14 15 #define CACHE_LINE_SIZE 32 16 17 #define DESC_SEC (0x2|(1<<4)) 18 #define CB (3<<2) //cache_on, write_back 19 #define CNB (2<<2) //cache_on, write_through 20 #define NCB (1<<2) //cache_off,WR_BUF on 21 #define NCNB (0<<2) //cache_off,WR_BUF off 22 #define AP_RW (3<<10) //supervisor=RW, user=RW 23 #define AP_RO (2<<10) //supervisor=RW, user=RO 24 25 #define DOMAIN_FAULT (0x0) 26 #define DOMAIN_CHK (0x1) 27 #define DOMAIN_NOTCHK (0x3) 28 #define DOMAIN0 (0x0<<5) 29 #define DOMAIN1 (0x1<<5) 30 31 #define DOMAIN0_ATTR (DOMAIN_CHK<<0) 32 #define DOMAIN1_ATTR (DOMAIN_FAULT<<2) 33 34 #define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ 35 #define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ 36 #define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 37 #define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ 38 39 struct mem_desc 40 { 41 rt_uint32_t vaddr_start; 42 rt_uint32_t vaddr_end; 43 rt_uint32_t paddr_start; 44 rt_uint32_t attr; 45 }; 46 47 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size); 48 49 #endif 50