1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2012-01-10 bernard porting to AM1808
9 */
10
11 #include <rtthread.h>
12 #include "am33xx.h"
13 #include <mmu.h>
14
15 extern void rt_cpu_dcache_disable(void);
16 extern void rt_hw_cpu_dcache_enable(void);
17 extern void rt_cpu_icache_disable(void);
18 extern void rt_hw_cpu_icache_enable(void);
19 extern void rt_cpu_mmu_disable(void);
20 extern void rt_cpu_mmu_enable(void);
21 extern void rt_cpu_tlb_set(register rt_uint32_t i);
22
mmu_disable_dcache()23 void mmu_disable_dcache()
24 {
25 rt_cpu_dcache_disable();
26 }
27
mmu_enable_dcache()28 void mmu_enable_dcache()
29 {
30 rt_hw_cpu_dcache_enable();
31 }
32
mmu_disable_icache()33 void mmu_disable_icache()
34 {
35 rt_cpu_icache_disable();
36 }
37
mmu_enable_icache()38 void mmu_enable_icache()
39 {
40 rt_hw_cpu_icache_enable();
41 }
42
mmu_disable()43 void mmu_disable()
44 {
45 rt_cpu_mmu_disable();
46 }
47
mmu_enable()48 void mmu_enable()
49 {
50 rt_cpu_mmu_enable();
51 }
52
mmu_setttbase(register rt_uint32_t i)53 void mmu_setttbase(register rt_uint32_t i)
54 {
55 register rt_uint32_t value;
56
57 /* Invalidates all TLBs.Domain access is selected as
58 * client by configuring domain access register,
59 * in that case access controlled by permission value
60 * set by page table entry
61 */
62 value = 0;
63 asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
64
65 value = 0x55555555;
66 asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
67
68 rt_cpu_tlb_set(i);
69 }
70
mmu_set_domain(register rt_uint32_t i)71 void mmu_set_domain(register rt_uint32_t i)
72 {
73 asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i));
74 }
75
mmu_enable_alignfault()76 void mmu_enable_alignfault()
77 {
78 register rt_uint32_t i;
79
80 /* read control register */
81 asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
82
83 i |= (1 << 1);
84
85 /* write back to control register */
86 asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
87 }
88
mmu_disable_alignfault()89 void mmu_disable_alignfault()
90 {
91 register rt_uint32_t i;
92
93 /* read control register */
94 asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
95
96 i &= ~(1 << 1);
97
98 /* write back to control register */
99 asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
100 }
101
mmu_clean_invalidated_cache_index(int index)102 void mmu_clean_invalidated_cache_index(int index)
103 {
104 asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
105 }
106
mmu_clean_dcache(rt_uint32_t buffer,rt_uint32_t size)107 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
108 {
109 unsigned int ptr;
110
111 ptr = buffer & ~0x1f;
112
113 while (ptr < buffer + size)
114 {
115 asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
116 ptr += 32;
117 }
118 }
119
mmu_invalidate_dcache(rt_uint32_t buffer,rt_uint32_t size)120 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
121 {
122 unsigned int ptr;
123
124 ptr = buffer & ~0x1f;
125
126 while (ptr < buffer + size)
127 {
128 asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
129 ptr += 32;
130 }
131 }
132
mmu_invalidate_tlb()133 void mmu_invalidate_tlb()
134 {
135 asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
136 }
137
mmu_invalidate_icache()138 void mmu_invalidate_icache()
139 {
140 asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
141 }
142
143 /* level1 page table */
144 static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)));
mmu_setmtt(rt_uint32_t vaddrStart,rt_uint32_t vaddrEnd,rt_uint32_t paddrStart,rt_uint32_t attr)145 void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
146 {
147 volatile rt_uint32_t *pTT;
148 volatile int i,nSec;
149 pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
150 nSec=(vaddrEnd>>20)-(vaddrStart>>20);
151 for(i=0;i<=nSec;i++)
152 {
153 *pTT = attr |(((paddrStart>>20)+i)<<20);
154 pTT++;
155 }
156 }
157
158 /* set page table */
mmu_setmtts(void)159 RT_WEAK void mmu_setmtts(void)
160 {
161 mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */
162 mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */
163 mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */
164 mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */
165 }
166
rt_hw_mmu_init(void)167 void rt_hw_mmu_init(void)
168 {
169 /* disable I/D cache */
170 mmu_disable_dcache();
171 mmu_disable_icache();
172 mmu_disable();
173 mmu_invalidate_tlb();
174
175 mmu_setmtts();
176
177 /* set MMU table address */
178 mmu_setttbase((rt_uint32_t)_page_table);
179
180 /* enables MMU */
181 mmu_enable();
182
183 /* enable Instruction Cache */
184 mmu_enable_icache();
185
186 /* enable Data Cache */
187 mmu_enable_dcache();
188 }
189
190