1*10465441SEvalZero/* 2*10465441SEvalZero * Copyright (c) 2006-2018, RT-Thread Development Team 3*10465441SEvalZero * 4*10465441SEvalZero * SPDX-License-Identifier: Apache-2.0 5*10465441SEvalZero * 6*10465441SEvalZero * Change Logs: 7*10465441SEvalZero * Date Author Notes 8*10465441SEvalZero * 2013-07-05 Bernard the first version 9*10465441SEvalZero */ 10*10465441SEvalZero 11*10465441SEvalZero.globl rt_cpu_vector_set_base 12*10465441SEvalZerort_cpu_vector_set_base: 13*10465441SEvalZero mcr p15, #0, r0, c12, c0, #0 14*10465441SEvalZero dsb 15*10465441SEvalZero bx lr 16*10465441SEvalZero 17*10465441SEvalZero.globl rt_cpu_vector_get_base 18*10465441SEvalZerort_cpu_vector_get_base: 19*10465441SEvalZero mrc p15, #0, r0, c12, c0, #0 20*10465441SEvalZero bx lr 21*10465441SEvalZero 22*10465441SEvalZero.globl rt_cpu_get_sctlr 23*10465441SEvalZerort_cpu_get_sctlr: 24*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 25*10465441SEvalZero bx lr 26*10465441SEvalZero 27*10465441SEvalZero.globl rt_cpu_dcache_enable 28*10465441SEvalZerort_cpu_dcache_enable: 29*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 30*10465441SEvalZero orr r0, r0, #0x00000004 31*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 32*10465441SEvalZero bx lr 33*10465441SEvalZero 34*10465441SEvalZero.globl rt_cpu_icache_enable 35*10465441SEvalZerort_cpu_icache_enable: 36*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 37*10465441SEvalZero orr r0, r0, #0x00001000 38*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 39*10465441SEvalZero bx lr 40*10465441SEvalZero 41*10465441SEvalZero_FLD_MAX_WAY: 42*10465441SEvalZero .word 0x3ff 43*10465441SEvalZero_FLD_MAX_IDX: 44*10465441SEvalZero .word 0x7ff 45*10465441SEvalZero 46*10465441SEvalZero.globl rt_cpu_dcache_clean_flush 47*10465441SEvalZerort_cpu_dcache_clean_flush: 48*10465441SEvalZero push {r4-r11} 49*10465441SEvalZero dmb 50*10465441SEvalZero mrc p15, #1, r0, c0, c0, #1 @ read clid register 51*10465441SEvalZero ands r3, r0, #0x7000000 @ get level of coherency 52*10465441SEvalZero mov r3, r3, lsr #23 53*10465441SEvalZero beq finished 54*10465441SEvalZero mov r10, #0 55*10465441SEvalZeroloop1: 56*10465441SEvalZero add r2, r10, r10, lsr #1 57*10465441SEvalZero mov r1, r0, lsr r2 58*10465441SEvalZero and r1, r1, #7 59*10465441SEvalZero cmp r1, #2 60*10465441SEvalZero blt skip 61*10465441SEvalZero mcr p15, #2, r10, c0, c0, #0 62*10465441SEvalZero isb 63*10465441SEvalZero mrc p15, #1, r1, c0, c0, #0 64*10465441SEvalZero and r2, r1, #7 65*10465441SEvalZero add r2, r2, #4 66*10465441SEvalZero ldr r4, _FLD_MAX_WAY 67*10465441SEvalZero ands r4, r4, r1, lsr #3 68*10465441SEvalZero clz r5, r4 69*10465441SEvalZero ldr r7, _FLD_MAX_IDX 70*10465441SEvalZero ands r7, r7, r1, lsr #13 71*10465441SEvalZeroloop2: 72*10465441SEvalZero mov r9, r4 73*10465441SEvalZeroloop3: 74*10465441SEvalZero orr r11, r10, r9, lsl r5 75*10465441SEvalZero orr r11, r11, r7, lsl r2 76*10465441SEvalZero mcr p15, #0, r11, c7, c14, #2 77*10465441SEvalZero subs r9, r9, #1 78*10465441SEvalZero bge loop3 79*10465441SEvalZero subs r7, r7, #1 80*10465441SEvalZero bge loop2 81*10465441SEvalZeroskip: 82*10465441SEvalZero add r10, r10, #2 83*10465441SEvalZero cmp r3, r10 84*10465441SEvalZero bgt loop1 85*10465441SEvalZero 86*10465441SEvalZerofinished: 87*10465441SEvalZero dsb 88*10465441SEvalZero isb 89*10465441SEvalZero pop {r4-r11} 90*10465441SEvalZero bx lr 91*10465441SEvalZero 92*10465441SEvalZero.globl rt_cpu_dcache_disable 93*10465441SEvalZerort_cpu_dcache_disable: 94*10465441SEvalZero push {r4-r11, lr} 95*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 96*10465441SEvalZero bic r0, r0, #0x00000004 97*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 98*10465441SEvalZero bl rt_cpu_dcache_clean_flush 99*10465441SEvalZero pop {r4-r11, lr} 100*10465441SEvalZero bx lr 101*10465441SEvalZero 102*10465441SEvalZero.globl rt_cpu_icache_disable 103*10465441SEvalZerort_cpu_icache_disable: 104*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 105*10465441SEvalZero bic r0, r0, #0x00001000 106*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 107*10465441SEvalZero bx lr 108*10465441SEvalZero 109*10465441SEvalZero.globl rt_cpu_mmu_disable 110*10465441SEvalZerort_cpu_mmu_disable: 111*10465441SEvalZero mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb 112*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 113*10465441SEvalZero bic r0, r0, #1 114*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit 115*10465441SEvalZero dsb 116*10465441SEvalZero bx lr 117*10465441SEvalZero 118*10465441SEvalZero.globl rt_cpu_mmu_enable 119*10465441SEvalZerort_cpu_mmu_enable: 120*10465441SEvalZero mrc p15, #0, r0, c1, c0, #0 121*10465441SEvalZero orr r0, r0, #0x001 122*10465441SEvalZero mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit 123*10465441SEvalZero dsb 124*10465441SEvalZero bx lr 125*10465441SEvalZero 126*10465441SEvalZero.globl rt_cpu_tlb_set 127*10465441SEvalZerort_cpu_tlb_set: 128*10465441SEvalZero mcr p15, #0, r0, c2, c0, #0 129*10465441SEvalZero dmb 130*10465441SEvalZero bx lr 131