1/* 2 * Copyright (c) 2006-2018, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2013-07-05 Bernard the first version 9 */ 10 11.globl rt_cpu_vector_set_base 12rt_cpu_vector_set_base: 13 mcr p15, #0, r0, c12, c0, #0 14 dsb 15 bx lr 16 17.globl rt_cpu_vector_get_base 18rt_cpu_vector_get_base: 19 mrc p15, #0, r0, c12, c0, #0 20 bx lr 21 22.globl rt_cpu_get_sctlr 23rt_cpu_get_sctlr: 24 mrc p15, #0, r0, c1, c0, #0 25 bx lr 26 27.globl rt_cpu_dcache_enable 28rt_cpu_dcache_enable: 29 mrc p15, #0, r0, c1, c0, #0 30 orr r0, r0, #0x00000004 31 mcr p15, #0, r0, c1, c0, #0 32 bx lr 33 34.globl rt_cpu_icache_enable 35rt_cpu_icache_enable: 36 mrc p15, #0, r0, c1, c0, #0 37 orr r0, r0, #0x00001000 38 mcr p15, #0, r0, c1, c0, #0 39 bx lr 40 41_FLD_MAX_WAY: 42 .word 0x3ff 43_FLD_MAX_IDX: 44 .word 0x7ff 45 46.globl rt_cpu_dcache_clean_flush 47rt_cpu_dcache_clean_flush: 48 push {r4-r11} 49 dmb 50 mrc p15, #1, r0, c0, c0, #1 @ read clid register 51 ands r3, r0, #0x7000000 @ get level of coherency 52 mov r3, r3, lsr #23 53 beq finished 54 mov r10, #0 55loop1: 56 add r2, r10, r10, lsr #1 57 mov r1, r0, lsr r2 58 and r1, r1, #7 59 cmp r1, #2 60 blt skip 61 mcr p15, #2, r10, c0, c0, #0 62 isb 63 mrc p15, #1, r1, c0, c0, #0 64 and r2, r1, #7 65 add r2, r2, #4 66 ldr r4, _FLD_MAX_WAY 67 ands r4, r4, r1, lsr #3 68 clz r5, r4 69 ldr r7, _FLD_MAX_IDX 70 ands r7, r7, r1, lsr #13 71loop2: 72 mov r9, r4 73loop3: 74 orr r11, r10, r9, lsl r5 75 orr r11, r11, r7, lsl r2 76 mcr p15, #0, r11, c7, c14, #2 77 subs r9, r9, #1 78 bge loop3 79 subs r7, r7, #1 80 bge loop2 81skip: 82 add r10, r10, #2 83 cmp r3, r10 84 bgt loop1 85 86finished: 87 dsb 88 isb 89 pop {r4-r11} 90 bx lr 91 92.globl rt_cpu_dcache_disable 93rt_cpu_dcache_disable: 94 push {r4-r11, lr} 95 mrc p15, #0, r0, c1, c0, #0 96 bic r0, r0, #0x00000004 97 mcr p15, #0, r0, c1, c0, #0 98 bl rt_cpu_dcache_clean_flush 99 pop {r4-r11, lr} 100 bx lr 101 102.globl rt_cpu_icache_disable 103rt_cpu_icache_disable: 104 mrc p15, #0, r0, c1, c0, #0 105 bic r0, r0, #0x00001000 106 mcr p15, #0, r0, c1, c0, #0 107 bx lr 108 109.globl rt_cpu_mmu_disable 110rt_cpu_mmu_disable: 111 mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb 112 mrc p15, #0, r0, c1, c0, #0 113 bic r0, r0, #1 114 mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit 115 dsb 116 bx lr 117 118.globl rt_cpu_mmu_enable 119rt_cpu_mmu_enable: 120 mrc p15, #0, r0, c1, c0, #0 121 orr r0, r0, #0x001 122 mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit 123 dsb 124 bx lr 125 126.globl rt_cpu_tlb_set 127rt_cpu_tlb_set: 128 mcr p15, #0, r0, c2, c0, #0 129 dmb 130 bx lr 131