xref: /nrf52832-nimble/rt-thread/libcpu/arm/am335x/context_iar.S (revision 104654410c56c573564690304ae786df310c91fc)
1;/*
2; * File      : context_iar.S
3; * This file is part of RT-Thread RTOS
4; * COPYRIGHT (C) 2006, RT-Thread Development Team
5; *
6; *  This program is free software; you can redistribute it and/or modify
7; *  it under the terms of the GNU General Public License as published by
8; *  the Free Software Foundation; either version 2 of the License, or
9; *  (at your option) any later version.
10; *
11; *  This program is distributed in the hope that it will be useful,
12; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
13; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14; *  GNU General Public License for more details.
15; *
16; *  You should have received a copy of the GNU General Public License along
17; *  with this program; if not, write to the Free Software Foundation, Inc.,
18; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19; *
20; * Change Logs:
21; * Date           Author       Notes
22; * 2011-08-14     weety      copy from mini2440
23; * 2015-04-15     ArdaFu     convert from context_gcc.s
24; */
25
26#define NOINT            0xc0
27
28    SECTION    .text:CODE(6)
29/*
30 * rt_base_t rt_hw_interrupt_disable();
31 */
32    PUBLIC rt_hw_interrupt_disable
33rt_hw_interrupt_disable:
34    MRS     R0, CPSR
35    ORR     R1, R0, #NOINT
36    MSR     CPSR_C, R1
37    MOV     PC, LR
38
39/*
40 * void rt_hw_interrupt_enable(rt_base_t level);
41 */
42    PUBLIC rt_hw_interrupt_enable
43rt_hw_interrupt_enable:
44    MSR     CPSR_CXSF, R0
45    MOV     PC, LR
46
47/*
48 * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
49 * r0 --> from
50 * r1 --> to
51 */
52    PUBLIC rt_hw_context_switch
53rt_hw_context_switch:
54    STMFD   SP!, {LR}               ; push pc (lr should be pushed in place of PC)
55    STMFD   SP!, {R0-R12, LR}       ; push lr & register file
56    MRS     R4, CPSR
57    STMFD   SP!, {R4}               ; push cpsr
58    STR     SP, [R0]                ; store sp in preempted tasks TCB
59    LDR     SP, [R1]                ; get new task stack pointer
60    LDMFD   SP!, {R4}               ; pop new task spsr
61    MSR     SPSR_cxsf, R4
62    LDMFD   SP!, {R0-R12, LR, PC}^  ; pop new task r0-r12, lr & pc
63
64/*
65 * void rt_hw_context_switch_to(rt_uint32 to);
66 * r0 --> to
67 */
68    PUBLIC rt_hw_context_switch_to
69rt_hw_context_switch_to:
70    LDR     SP, [R0]                ; get new task stack pointer
71    LDMFD   SP!, {R4}               ; pop new task spsr
72    MSR     SPSR_cxsf, R4
73    LDMFD   SP!, {R0-R12, LR, PC}^  ; pop new task r0-r12, lr & pc
74
75/*
76 * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
77 */
78    IMPORT rt_thread_switch_interrupt_flag
79    IMPORT rt_interrupt_from_thread
80    IMPORT rt_interrupt_to_thread
81    PUBLIC rt_hw_context_switch_interrupt
82rt_hw_context_switch_interrupt:
83    LDR     R2, =rt_thread_switch_interrupt_flag
84    LDR     R3, [R2]
85    CMP     R3, #1
86    BEQ     _reswitch
87    MOV     R3, #1                          ; set flag to 1
88    STR     R3, [R2]
89    LDR     R2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
90    STR     R0, [R2]
91_reswitch:
92    LDR     R2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
93    STR     R1, [R2]
94    MOV     PC, LR
95    END
96
97