1 /*
2 * Copyright (c) 2006-2018, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 */
9 #include "enc28j60.h"
10
11 /* #define NET_TRACE */
12 /* #define ETH_RX_DUMP */
13 /* #define ETH_TX_DUMP */
14
15 #ifdef NET_TRACE
16 #define NET_DEBUG rt_kprintf
17 #else
18 #define NET_DEBUG(...)
19 #endif /* #ifdef NET_TRACE */
20
21 struct enc28j60_tx_list_typedef
22 {
23 struct enc28j60_tx_list_typedef *prev;
24 struct enc28j60_tx_list_typedef *next;
25 rt_uint32_t addr; /* pkt addr in buffer */
26 rt_uint32_t len; /* pkt len */
27 volatile rt_bool_t free; /* 0:busy, 1:free */
28 };
29 static struct enc28j60_tx_list_typedef enc28j60_tx_list[2];
30 static volatile struct enc28j60_tx_list_typedef *tx_current;
31 static volatile struct enc28j60_tx_list_typedef *tx_ack;
32 static struct rt_event tx_event;
33
34 /* private enc28j60 define */
35 /* enc28j60 spi interface function */
36 static uint8_t spi_read_op(struct rt_spi_device *spi_device, uint8_t op, uint8_t address);
37 static void spi_write_op(struct rt_spi_device *spi_device, uint8_t op, uint8_t address, uint8_t data);
38
39 static uint8_t spi_read(struct rt_spi_device *spi_device, uint8_t address);
40 static void spi_write(struct rt_spi_device *spi_device, rt_uint8_t address, rt_uint8_t data);
41
42 static void enc28j60_clkout(struct rt_spi_device *spi_device, rt_uint8_t clk);
43 static void enc28j60_set_bank(struct rt_spi_device *spi_device, uint8_t address);
44 static uint32_t enc28j60_interrupt_disable(struct rt_spi_device *spi_device);
45 static void enc28j60_interrupt_enable(struct rt_spi_device *spi_device, uint32_t level);
46
47 static uint16_t enc28j60_phy_read(struct rt_spi_device *spi_device, rt_uint8_t address);
48 static void enc28j60_phy_write(struct rt_spi_device *spi_device, rt_uint8_t address, uint16_t data);
49 static rt_bool_t enc28j60_check_link_status(struct rt_spi_device *spi_device);
50
51 #define enc28j60_lock(dev) rt_mutex_take(&((struct net_device*)dev)->lock, RT_WAITING_FOREVER);
52 #define enc28j60_unlock(dev) rt_mutex_release(&((struct net_device*)dev)->lock);
53
54 static struct net_device enc28j60_dev;
55 static uint8_t Enc28j60Bank;
56 //struct rt_spi_device * spi_device;
57 static uint16_t NextPacketPtr;
58
_delay_us(uint32_t us)59 static void _delay_us(uint32_t us)
60 {
61 volatile uint32_t len;
62 for (; us > 0; us --)
63 for (len = 0; len < 20; len++);
64 }
65
66 /* enc28j60 spi interface function */
spi_read_op(struct rt_spi_device * spi_device,uint8_t op,uint8_t address)67 static uint8_t spi_read_op(struct rt_spi_device *spi_device, uint8_t op, uint8_t address)
68 {
69 uint8_t send_buffer[2];
70 uint8_t recv_buffer[1];
71 uint32_t send_size = 1;
72
73 send_buffer[0] = op | (address & ADDR_MASK);
74 send_buffer[1] = 0xFF;
75
76 /* do dummy read if needed (for mac and mii, see datasheet page 29). */
77 if (address & 0x80)
78 {
79 send_size = 2;
80 }
81
82 rt_spi_send_then_recv(spi_device, send_buffer, send_size, recv_buffer, 1);
83 return (recv_buffer[0]);
84 }
85
spi_write_op(struct rt_spi_device * spi_device,uint8_t op,uint8_t address,uint8_t data)86 static void spi_write_op(struct rt_spi_device *spi_device, uint8_t op, uint8_t address, uint8_t data)
87 {
88 uint32_t level;
89 uint8_t buffer[2];
90
91 level = rt_hw_interrupt_disable();
92
93 buffer[0] = op | (address & ADDR_MASK);
94 buffer[1] = data;
95 rt_spi_send(spi_device, buffer, 2);
96
97 rt_hw_interrupt_enable(level);
98 }
99
100 /* enc28j60 function */
enc28j60_clkout(struct rt_spi_device * spi_device,rt_uint8_t clk)101 static void enc28j60_clkout(struct rt_spi_device *spi_device, rt_uint8_t clk)
102 {
103 /* setup clkout: 2 is 12.5MHz: */
104 spi_write(spi_device, ECOCON, clk & 0x7);
105 }
106
enc28j60_set_bank(struct rt_spi_device * spi_device,uint8_t address)107 static void enc28j60_set_bank(struct rt_spi_device *spi_device, uint8_t address)
108 {
109 /* set the bank (if needed) .*/
110 if ((address & BANK_MASK) != Enc28j60Bank)
111 {
112 /* set the bank. */
113 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, (ECON1_BSEL1 | ECON1_BSEL0));
114 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, (address & BANK_MASK) >> 5);
115 Enc28j60Bank = (address & BANK_MASK);
116 }
117 }
118
spi_read(struct rt_spi_device * spi_device,uint8_t address)119 static uint8_t spi_read(struct rt_spi_device *spi_device, uint8_t address)
120 {
121 /* set the bank. */
122 enc28j60_set_bank(spi_device, address);
123 /* do the read. */
124 return spi_read_op(spi_device, ENC28J60_READ_CTRL_REG, address);
125 }
126
spi_write(struct rt_spi_device * spi_device,rt_uint8_t address,rt_uint8_t data)127 static void spi_write(struct rt_spi_device *spi_device, rt_uint8_t address, rt_uint8_t data)
128 {
129 /* set the bank. */
130 enc28j60_set_bank(spi_device, address);
131 /* do the write. */
132 spi_write_op(spi_device, ENC28J60_WRITE_CTRL_REG, address, data);
133 }
134
enc28j60_phy_read(struct rt_spi_device * spi_device,rt_uint8_t address)135 static uint16_t enc28j60_phy_read(struct rt_spi_device *spi_device, rt_uint8_t address)
136 {
137 uint16_t value;
138
139 /* Set the right address and start the register read operation. */
140 spi_write(spi_device, MIREGADR, address);
141 spi_write(spi_device, MICMD, MICMD_MIIRD);
142
143 _delay_us(15);
144
145 /* wait until the PHY read completes. */
146 while (spi_read(spi_device, MISTAT) & MISTAT_BUSY);
147
148 /* reset reading bit */
149 spi_write(spi_device, MICMD, 0x00);
150
151 value = spi_read(spi_device, MIRDL) | spi_read(spi_device, MIRDH) << 8;
152
153 return (value);
154 }
155
enc28j60_phy_write(struct rt_spi_device * spi_device,rt_uint8_t address,uint16_t data)156 static void enc28j60_phy_write(struct rt_spi_device *spi_device, rt_uint8_t address, uint16_t data)
157 {
158 /* set the PHY register address. */
159 spi_write(spi_device, MIREGADR, address);
160
161 /* write the PHY data. */
162 spi_write(spi_device, MIWRL, data);
163 spi_write(spi_device, MIWRH, data >> 8);
164
165 /* wait until the PHY write completes. */
166 while (spi_read(spi_device, MISTAT) & MISTAT_BUSY)
167 {
168 _delay_us(15);
169 }
170 }
171
enc28j60_interrupt_disable(struct rt_spi_device * spi_device)172 static uint32_t enc28j60_interrupt_disable(struct rt_spi_device *spi_device)
173 {
174 uint32_t level;
175
176 /* switch to bank 0 */
177 enc28j60_set_bank(spi_device, EIE);
178
179 /* get last interrupt level */
180 level = spi_read(spi_device, EIE);
181 /* disable interrutps */
182 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIE, level);
183
184 return level;
185 }
186
enc28j60_interrupt_enable(struct rt_spi_device * spi_device,uint32_t level)187 static void enc28j60_interrupt_enable(struct rt_spi_device *spi_device, uint32_t level)
188 {
189 /* switch to bank 0 */
190 enc28j60_set_bank(spi_device, EIE);
191 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, EIE, level);
192 }
193
194 /*
195 * Access the PHY to determine link status
196 */
enc28j60_check_link_status(struct rt_spi_device * spi_device)197 static rt_bool_t enc28j60_check_link_status(struct rt_spi_device *spi_device)
198 {
199 uint16_t reg;
200
201 reg = enc28j60_phy_read(spi_device, PHSTAT2);
202
203 if (reg & PHSTAT2_LSTAT)
204 {
205 /* on */
206 return RT_TRUE;
207 }
208 else
209 {
210 /* off */
211 return RT_FALSE;
212 }
213 }
214
215 /************************* RT-Thread Device Interface *************************/
enc28j60_isr(void)216 void enc28j60_isr(void)
217 {
218 eth_device_ready(&enc28j60_dev.parent);
219 NET_DEBUG("enc28j60_isr\r\n");
220 }
221
_tx_chain_init(void)222 static void _tx_chain_init(void)
223 {
224 enc28j60_tx_list[0].next = &enc28j60_tx_list[1];
225 enc28j60_tx_list[1].next = &enc28j60_tx_list[0];
226
227 enc28j60_tx_list[0].prev = &enc28j60_tx_list[1];
228 enc28j60_tx_list[1].prev = &enc28j60_tx_list[0];
229
230 enc28j60_tx_list[0].addr = TXSTART_INIT;
231 enc28j60_tx_list[1].addr = TXSTART_INIT + MAX_TX_PACKAGE_SIZE;
232
233 enc28j60_tx_list[0].free = RT_TRUE;
234 enc28j60_tx_list[1].free = RT_TRUE;
235
236 tx_current = &enc28j60_tx_list[0];
237 tx_ack = tx_current;
238 }
239
240 /* initialize the interface */
enc28j60_init(rt_device_t dev)241 static rt_err_t enc28j60_init(rt_device_t dev)
242 {
243 struct net_device *enc28j60 = (struct net_device *)dev;
244 struct rt_spi_device *spi_device = enc28j60->spi_device;
245
246 enc28j60_lock(dev);
247
248 _tx_chain_init();
249
250 // perform system reset
251 spi_write_op(spi_device, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
252 rt_thread_delay(RT_TICK_PER_SECOND / 50); /* delay 20ms */
253
254 NextPacketPtr = RXSTART_INIT;
255
256 // Rx start
257 spi_write(spi_device, ERXSTL, RXSTART_INIT & 0xFF);
258 spi_write(spi_device, ERXSTH, RXSTART_INIT >> 8);
259 // set receive pointer address
260 spi_write(spi_device, ERXRDPTL, RXSTOP_INIT & 0xFF);
261 spi_write(spi_device, ERXRDPTH, RXSTOP_INIT >> 8);
262 // RX end
263 spi_write(spi_device, ERXNDL, RXSTOP_INIT & 0xFF);
264 spi_write(spi_device, ERXNDH, RXSTOP_INIT >> 8);
265
266 // TX start
267 spi_write(spi_device, ETXSTL, TXSTART_INIT & 0xFF);
268 spi_write(spi_device, ETXSTH, TXSTART_INIT >> 8);
269 // set transmission pointer address
270 spi_write(spi_device, EWRPTL, TXSTART_INIT & 0xFF);
271 spi_write(spi_device, EWRPTH, TXSTART_INIT >> 8);
272 // TX end
273 spi_write(spi_device, ETXNDL, TXSTOP_INIT & 0xFF);
274 spi_write(spi_device, ETXNDH, TXSTOP_INIT >> 8);
275
276 // do bank 1 stuff, packet filter:
277 // For broadcast packets we allow only ARP packtets
278 // All other packets should be unicast only for our mac (MAADR)
279 //
280 // The pattern to match on is therefore
281 // Type ETH.DST
282 // ARP BROADCAST
283 // 06 08 -- ff ff ff ff ff ff -> ip checksum for theses bytes=f7f9
284 // in binary these poitions are:11 0000 0011 1111
285 // This is hex 303F->EPMM0=0x3f,EPMM1=0x30
286 spi_write(spi_device, ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
287
288 // do bank 2 stuff
289 // enable MAC receive
290 spi_write(spi_device, MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
291 // enable automatic padding to 60bytes and CRC operations
292 // spi_write_op(ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0|MACON3_TXCRCEN|MACON3_FRMLNEN);
293 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX);
294 // bring MAC out of reset
295
296 // set inter-frame gap (back-to-back)
297 // spi_write(MABBIPG, 0x12);
298 spi_write(spi_device, MABBIPG, 0x15);
299
300 spi_write(spi_device, MACON4, MACON4_DEFER);
301 spi_write(spi_device, MACLCON2, 63);
302
303 // set inter-frame gap (non-back-to-back)
304 spi_write(spi_device, MAIPGL, 0x12);
305 spi_write(spi_device, MAIPGH, 0x0C);
306
307 // Set the maximum packet size which the controller will accept
308 // Do not send packets longer than MAX_FRAMELEN:
309 spi_write(spi_device, MAMXFLL, MAX_FRAMELEN & 0xFF);
310 spi_write(spi_device, MAMXFLH, MAX_FRAMELEN >> 8);
311
312 // do bank 3 stuff
313 // write MAC address
314 // NOTE: MAC address in ENC28J60 is byte-backward
315 spi_write(spi_device, MAADR0, enc28j60->dev_addr[5]);
316 spi_write(spi_device, MAADR1, enc28j60->dev_addr[4]);
317 spi_write(spi_device, MAADR2, enc28j60->dev_addr[3]);
318 spi_write(spi_device, MAADR3, enc28j60->dev_addr[2]);
319 spi_write(spi_device, MAADR4, enc28j60->dev_addr[1]);
320 spi_write(spi_device, MAADR5, enc28j60->dev_addr[0]);
321
322 /* output off */
323 spi_write(spi_device, ECOCON, 0x00);
324
325 // enc28j60_phy_write(PHCON1, 0x00);
326 enc28j60_phy_write(spi_device, PHCON1, PHCON1_PDPXMD); // full duplex
327 // no loopback of transmitted frames
328 enc28j60_phy_write(spi_device, PHCON2, PHCON2_HDLDIS);
329 /* enable PHY link changed interrupt. */
330 enc28j60_phy_write(spi_device, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
331
332 enc28j60_set_bank(spi_device, ECON2);
333 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_AUTOINC);
334
335 // switch to bank 0
336 enc28j60_set_bank(spi_device, ECON1);
337 // enable all interrutps
338 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, EIE, 0xFF);
339 // enable packet reception
340 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
341
342 /* clock out */
343 enc28j60_clkout(spi_device, 2);
344
345 enc28j60_phy_write(spi_device, PHLCON, 0xD76); //0x476
346 rt_thread_delay(RT_TICK_PER_SECOND / 50); /* delay 20ms */
347
348 enc28j60_unlock(dev);
349 return RT_EOK;
350 }
351
352 /* control the interface */
enc28j60_control(rt_device_t dev,int cmd,void * args)353 static rt_err_t enc28j60_control(rt_device_t dev, int cmd, void *args)
354 {
355 struct net_device *enc28j60 = (struct net_device *)dev;
356 switch (cmd)
357 {
358 case NIOCTL_GADDR:
359 /* get mac address */
360 if (args) rt_memcpy(args, enc28j60->dev_addr, 6);
361 else return -RT_ERROR;
362 break;
363
364 default :
365 break;
366 }
367
368 return RT_EOK;
369 }
370
371 /* Open the ethernet interface */
enc28j60_open(rt_device_t dev,uint16_t oflag)372 static rt_err_t enc28j60_open(rt_device_t dev, uint16_t oflag)
373 {
374 return RT_EOK;
375 }
376
377 /* Close the interface */
enc28j60_close(rt_device_t dev)378 static rt_err_t enc28j60_close(rt_device_t dev)
379 {
380 return RT_EOK;
381 }
382
383 /* Read */
enc28j60_read(rt_device_t dev,rt_off_t pos,void * buffer,rt_size_t size)384 static rt_size_t enc28j60_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
385 {
386 rt_set_errno(-RT_ENOSYS);
387 return RT_EOK;
388 }
389
390 /* Write */
enc28j60_write(rt_device_t dev,rt_off_t pos,const void * buffer,rt_size_t size)391 static rt_size_t enc28j60_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
392 {
393 rt_set_errno(-RT_ENOSYS);
394 return 0;
395 }
396
397 /* ethernet device interface */
398 /* Transmit packet. */
enc28j60_tx(rt_device_t dev,struct pbuf * p)399 static rt_err_t enc28j60_tx(rt_device_t dev, struct pbuf *p)
400 {
401 struct net_device *enc28j60 = (struct net_device *)dev;
402 struct rt_spi_device *spi_device = enc28j60->spi_device;
403 struct pbuf *q;
404 rt_uint32_t level;
405 #ifdef ETH_TX_DUMP
406 rt_size_t dump_count = 0;
407 rt_uint8_t *dump_ptr;
408 rt_size_t dump_i;
409 #endif
410
411 if (tx_current->free == RT_FALSE)
412 {
413 NET_DEBUG("[Tx] no empty buffer!\r\n");
414 while (tx_current->free == RT_FALSE)
415 {
416 rt_err_t result;
417 rt_uint32_t recved;
418
419 /* there is no block yet, wait a flag */
420 result = rt_event_recv(&tx_event, 0x01,
421 RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
422
423 RT_ASSERT(result == RT_EOK);
424 }
425 NET_DEBUG("[Tx] wait empty buffer done!\r\n");
426 }
427
428 enc28j60_lock(dev);
429
430 /* disable enc28j60 interrupt */
431 level = enc28j60_interrupt_disable(spi_device);
432
433 // Set the write pointer to start of transmit buffer area
434 // spi_write(EWRPTL, TXSTART_INIT&0xFF);
435 // spi_write(EWRPTH, TXSTART_INIT>>8);
436 spi_write(spi_device, EWRPTL, (tx_current->addr) & 0xFF);
437 spi_write(spi_device, EWRPTH, (tx_current->addr) >> 8);
438 // Set the TXND pointer to correspond to the packet size given
439 tx_current->len = p->tot_len;
440 // spi_write(ETXNDL, (TXSTART_INIT+ p->tot_len + 1)&0xFF);
441 // spi_write(ETXNDH, (TXSTART_INIT+ p->tot_len + 1)>>8);
442
443 // write per-packet control byte (0x00 means use macon3 settings)
444 spi_write_op(spi_device, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
445
446 #ifdef ETH_TX_DUMP
447 NET_DEBUG("tx_dump, size:%d\r\n", p->tot_len);
448 #endif
449 for (q = p; q != NULL; q = q->next)
450 {
451 uint8_t cmd = ENC28J60_WRITE_BUF_MEM;
452 rt_spi_send_then_send(enc28j60->spi_device, &cmd, 1, q->payload, q->len);
453 #ifdef ETH_RX_DUMP
454 dump_ptr = q->payload;
455 for (dump_i = 0; dump_i < q->len; dump_i++)
456 {
457 NET_DEBUG("%02x ", *dump_ptr);
458 if (((dump_count + 1) % 8) == 0)
459 {
460 NET_DEBUG(" ");
461 }
462 if (((dump_count + 1) % 16) == 0)
463 {
464 NET_DEBUG("\r\n");
465 }
466 dump_count++;
467 dump_ptr++;
468 }
469 #endif
470 }
471 #ifdef ETH_RX_DUMP
472 NET_DEBUG("\r\n");
473 #endif
474
475 // send the contents of the transmit buffer onto the network
476 if (tx_current == tx_ack)
477 {
478 NET_DEBUG("[Tx] stop, restart!\r\n");
479 // TX start
480 spi_write(spi_device, ETXSTL, (tx_current->addr) & 0xFF);
481 spi_write(spi_device, ETXSTH, (tx_current->addr) >> 8);
482 // TX end
483 spi_write(spi_device, ETXNDL, (tx_current->addr + tx_current->len) & 0xFF);
484 spi_write(spi_device, ETXNDH, (tx_current->addr + tx_current->len) >> 8);
485
486 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
487 }
488 else
489 {
490 NET_DEBUG("[Tx] busy, add to chain!\r\n");
491 }
492
493 tx_current->free = RT_FALSE;
494 tx_current = tx_current->next;
495
496 /* Reset the transmit logic problem. See Rev. B4 Silicon Errata point 12. */
497 if ((spi_read(spi_device, EIR) & EIR_TXERIF))
498 {
499 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
500 }
501
502 /* enable enc28j60 interrupt */
503 enc28j60_interrupt_enable(spi_device, level);
504
505 enc28j60_unlock(dev);
506
507 return RT_EOK;
508 }
509
510 /* recv packet. */
enc28j60_rx(rt_device_t dev)511 static struct pbuf *enc28j60_rx(rt_device_t dev)
512 {
513 struct net_device *enc28j60 = (struct net_device *)dev;
514 struct rt_spi_device *spi_device = enc28j60->spi_device;
515 struct pbuf *p = RT_NULL;
516
517 uint8_t eir, eir_clr;
518 uint32_t pk_counter;
519 rt_uint32_t level;
520 rt_uint32_t len;
521 rt_uint16_t rxstat;
522
523 enc28j60_lock(dev);
524
525 /* disable enc28j60 interrupt */
526 level = enc28j60_interrupt_disable(spi_device);
527
528 /* get EIR */
529 eir = spi_read(spi_device, EIR);
530
531 while (eir & ~EIR_PKTIF)
532 {
533 eir_clr = 0;
534
535 /* clear PKTIF */
536 if (eir & EIR_PKTIF)
537 {
538 NET_DEBUG("EIR_PKTIF\r\n");
539
540 /* switch to bank 0. */
541 enc28j60_set_bank(spi_device, EIE);
542 /* disable rx interrutps. */
543 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIE, EIE_PKTIE);
544 eir_clr |= EIR_PKTIF;
545 // enc28j60_set_bank(spi_device, EIR);
546 // spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_PKTIF);
547 }
548
549 /* clear DMAIF */
550 if (eir & EIR_DMAIF)
551 {
552 NET_DEBUG("EIR_DMAIF\r\n");
553 eir_clr |= EIR_DMAIF;
554 // enc28j60_set_bank(spi_device, EIR);
555 // spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_DMAIF);
556 }
557
558 /* LINK changed handler */
559 if (eir & EIR_LINKIF)
560 {
561 rt_bool_t link_status;
562
563 NET_DEBUG("EIR_LINKIF\r\n");
564 link_status = enc28j60_check_link_status(spi_device);
565
566 /* read PHIR to clear the flag */
567 enc28j60_phy_read(spi_device, PHIR);
568 eir_clr |= EIR_LINKIF;
569 // enc28j60_set_bank(spi_device, EIR);
570 // spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_LINKIF);
571
572 eth_device_linkchange(&(enc28j60->parent), link_status);
573 }
574
575 if (eir & EIR_TXIF)
576 {
577 /* A frame has been transmitted. */
578 enc28j60_set_bank(spi_device, EIR);
579 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXIF);
580
581 tx_ack->free = RT_TRUE;
582 tx_ack = tx_ack->next;
583 if (tx_ack->free == RT_FALSE)
584 {
585 NET_DEBUG("[tx isr] Tx chain not empty, continue send the next pkt!\r\n");
586 // TX start
587 spi_write(spi_device, ETXSTL, (tx_ack->addr) & 0xFF);
588 spi_write(spi_device, ETXSTH, (tx_ack->addr) >> 8);
589 // TX end
590 spi_write(spi_device, ETXNDL, (tx_ack->addr + tx_ack->len) & 0xFF);
591 spi_write(spi_device, ETXNDH, (tx_ack->addr + tx_ack->len) >> 8);
592
593 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRTS);
594 }
595 else
596 {
597 NET_DEBUG("[tx isr] Tx chain empty, stop!\r\n");
598 }
599
600 /* set event */
601 rt_event_send(&tx_event, 0x01);
602 }
603
604 /* wake up handler */
605 if (eir & EIR_WOLIF)
606 {
607 NET_DEBUG("EIR_WOLIF\r\n");
608 eir_clr |= EIR_WOLIF;
609 // enc28j60_set_bank(spi_device, EIR);
610 // spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_WOLIF);
611 }
612
613 /* TX Error handler */
614 if ((eir & EIR_TXERIF) != 0)
615 {
616 NET_DEBUG("EIR_TXERIF re-start tx chain!\r\n");
617 enc28j60_set_bank(spi_device, ECON1);
618 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_TXRST);
619 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_TXRST);
620 eir_clr |= EIR_TXERIF;
621 // enc28j60_set_bank(spi_device, EIR);
622 // spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_TXERIF);
623
624 /* re-init tx chain */
625 _tx_chain_init();
626 }
627
628 /* RX Error handler */
629 if ((eir & EIR_RXERIF) != 0)
630 {
631 NET_DEBUG("EIR_RXERIF re-start rx!\r\n");
632
633 NextPacketPtr = RXSTART_INIT;
634 enc28j60_set_bank(spi_device, ECON1);
635 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXRST);
636 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, ECON1, ECON1_RXRST);
637 /* switch to bank 0. */
638 enc28j60_set_bank(spi_device, ECON1);
639 /* enable packet reception. */
640 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
641 eir_clr |= EIR_RXERIF;
642 // enc28j60_set_bank(spi_device, EIR);
643 // spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, EIR_RXERIF);
644 }
645
646 enc28j60_set_bank(spi_device, EIR);
647 spi_write_op(spi_device, ENC28J60_BIT_FIELD_CLR, EIR, eir_clr);
648
649 eir = spi_read(spi_device, EIR);
650 }
651
652 /* read pkt */
653 pk_counter = spi_read(spi_device, EPKTCNT);
654 if (pk_counter)
655 {
656 /* Set the read pointer to the start of the received packet. */
657 spi_write(spi_device, ERDPTL, (NextPacketPtr));
658 spi_write(spi_device, ERDPTH, (NextPacketPtr) >> 8);
659
660 /* read the next packet pointer. */
661 NextPacketPtr = spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0);
662 NextPacketPtr |= spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0) << 8;
663
664 /* read the packet length (see datasheet page 43). */
665 len = spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0); //0x54
666 len |= spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0) << 8; //5554
667
668 len -= 4; //remove the CRC count
669
670 // read the receive status (see datasheet page 43)
671 rxstat = spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0);
672 rxstat |= ((rt_uint16_t)spi_read_op(spi_device, ENC28J60_READ_BUF_MEM, 0)) << 8;
673
674 // check CRC and symbol errors (see datasheet page 44, table 7-3):
675 // The ERXFCON.CRCEN is set by default. Normally we should not
676 // need to check this.
677 if ((rxstat & 0x80) == 0)
678 {
679 // invalid
680 len = 0;
681 }
682 else
683 {
684 /* allocation pbuf */
685 p = pbuf_alloc(PBUF_LINK, len, PBUF_POOL);
686 if (p != RT_NULL)
687 {
688 struct pbuf *q;
689 #ifdef ETH_RX_DUMP
690 rt_size_t dump_count = 0;
691 rt_uint8_t *dump_ptr;
692 rt_size_t dump_i;
693 NET_DEBUG("rx_dump, size:%d\r\n", len);
694 #endif
695 for (q = p; q != RT_NULL; q = q->next)
696 {
697 uint8_t cmd = ENC28J60_READ_BUF_MEM;
698 rt_spi_send_then_recv(spi_device, &cmd, 1, q->payload, q->len);
699 #ifdef ETH_RX_DUMP
700 dump_ptr = q->payload;
701 for (dump_i = 0; dump_i < q->len; dump_i++)
702 {
703 NET_DEBUG("%02x ", *dump_ptr);
704 if (((dump_count + 1) % 8) == 0)
705 {
706 NET_DEBUG(" ");
707 }
708 if (((dump_count + 1) % 16) == 0)
709 {
710 NET_DEBUG("\r\n");
711 }
712 dump_count++;
713 dump_ptr++;
714 }
715 #endif
716 }
717 #ifdef ETH_RX_DUMP
718 NET_DEBUG("\r\n");
719 #endif
720 }
721 }
722
723 /* Move the RX read pointer to the start of the next received packet. */
724 /* This frees the memory we just read out. */
725 spi_write(spi_device, ERXRDPTL, (NextPacketPtr));
726 spi_write(spi_device, ERXRDPTH, (NextPacketPtr) >> 8);
727
728 /* decrement the packet counter indicate we are done with this packet. */
729 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON2, ECON2_PKTDEC);
730 }
731 else
732 {
733 /* switch to bank 0. */
734 enc28j60_set_bank(spi_device, ECON1);
735 /* enable packet reception. */
736 spi_write_op(spi_device, ENC28J60_BIT_FIELD_SET, ECON1, ECON1_RXEN);
737
738 level |= EIE_PKTIE;
739 }
740
741 /* enable enc28j60 interrupt */
742 enc28j60_interrupt_enable(spi_device, level);
743
744 enc28j60_unlock(dev);
745
746 return p;
747 }
748
749 #ifdef RT_USING_DEVICE_OPS
750 const static struct rt_device_ops enc28j60_ops =
751 {
752 enc28j60_init,
753 enc28j60_open,
754 enc28j60_close,
755 enc28j60_read,
756 enc28j60_write,
757 enc28j60_control
758 };
759 #endif
760
enc28j60_attach(const char * spi_device_name)761 rt_err_t enc28j60_attach(const char *spi_device_name)
762 {
763 struct rt_spi_device *spi_device;
764
765 spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name);
766 if (spi_device == RT_NULL)
767 {
768 NET_DEBUG("spi device %s not found!\r\n", spi_device_name);
769 return -RT_ENOSYS;
770 }
771
772 /* config spi */
773 {
774 struct rt_spi_configuration cfg;
775 cfg.data_width = 8;
776 cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible Modes 0 */
777 cfg.max_hz = 20 * 1000 * 1000; /* SPI Interface with Clock Speeds Up to 20 MHz */
778 rt_spi_configure(spi_device, &cfg);
779 } /* config spi */
780
781 memset(&enc28j60_dev, 0, sizeof(enc28j60_dev));
782
783 rt_event_init(&tx_event, "eth_tx", RT_IPC_FLAG_FIFO);
784 enc28j60_dev.spi_device = spi_device;
785
786 /* detect device */
787 {
788 uint16_t value;
789
790 /* perform system reset. */
791 spi_write_op(spi_device, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
792 rt_thread_delay(1); /* delay 20ms */
793
794 enc28j60_dev.emac_rev = spi_read(spi_device, EREVID);
795 value = enc28j60_phy_read(spi_device, PHHID2);
796 enc28j60_dev.phy_rev = value & 0x0F;
797 enc28j60_dev.phy_pn = (value >> 4) & 0x3F;
798 enc28j60_dev.phy_id = (enc28j60_phy_read(spi_device, PHHID1) | ((value >> 10) << 16)) << 3;
799
800 if (enc28j60_dev.phy_id != 0x00280418)
801 {
802 NET_DEBUG("ENC28J60 PHY ID not correct!\r\n");
803 NET_DEBUG("emac_rev:%d\r\n", enc28j60_dev.emac_rev);
804 NET_DEBUG("phy_rev:%02X\r\n", enc28j60_dev.phy_rev);
805 NET_DEBUG("phy_pn:%02X\r\n", enc28j60_dev.phy_pn);
806 NET_DEBUG("phy_id:%08X\r\n", enc28j60_dev.phy_id);
807 return RT_EIO;
808 }
809 }
810
811 /* OUI 00-04-A3 (hex): Microchip Technology, Inc. */
812 enc28j60_dev.dev_addr[0] = 0x00;
813 enc28j60_dev.dev_addr[1] = 0x04;
814 enc28j60_dev.dev_addr[2] = 0xA3;
815 /* set MAC address, only for test */
816 enc28j60_dev.dev_addr[3] = 0x12;
817 enc28j60_dev.dev_addr[4] = 0x34;
818 enc28j60_dev.dev_addr[5] = 0x56;
819
820 /* init rt-thread device struct */
821 enc28j60_dev.parent.parent.type = RT_Device_Class_NetIf;
822 #ifdef RT_USING_DEVICE_OPS
823 enc28j60_dev.parent.parent.ops = &enc28j60_ops;
824 #else
825 enc28j60_dev.parent.parent.init = enc28j60_init;
826 enc28j60_dev.parent.parent.open = enc28j60_open;
827 enc28j60_dev.parent.parent.close = enc28j60_close;
828 enc28j60_dev.parent.parent.read = enc28j60_read;
829 enc28j60_dev.parent.parent.write = enc28j60_write;
830 enc28j60_dev.parent.parent.control = enc28j60_control;
831 #endif
832
833 /* init rt-thread ethernet device struct */
834 enc28j60_dev.parent.eth_rx = enc28j60_rx;
835 enc28j60_dev.parent.eth_tx = enc28j60_tx;
836
837 rt_mutex_init(&enc28j60_dev.lock, "enc28j60", RT_IPC_FLAG_FIFO);
838
839 eth_device_init(&(enc28j60_dev.parent), "e0");
840
841 return RT_EOK;
842 }
843
844 #ifdef RT_USING_FINSH
845 #include <finsh.h>
846 /*
847 * Debug routine to dump useful register contents
848 */
enc28j60(void)849 static void enc28j60(void)
850 {
851 struct rt_spi_device *spi_device = enc28j60_dev.spi_device;
852 enc28j60_lock(&enc28j60_dev);
853
854 rt_kprintf("-- enc28j60 registers:\n");
855 rt_kprintf("HwRevID: 0x%02X\n", spi_read(spi_device, EREVID));
856
857 rt_kprintf("Cntrl: ECON1 ECON2 ESTAT EIR EIE\n");
858 rt_kprintf(" 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X\n",
859 spi_read(spi_device, ECON1),
860 spi_read(spi_device, ECON2),
861 spi_read(spi_device, ESTAT),
862 spi_read(spi_device, EIR),
863 spi_read(spi_device, EIE));
864
865 rt_kprintf("MAC : MACON1 MACON3 MACON4\n");
866 rt_kprintf(" 0x%02X 0x%02X 0x%02X\n",
867 spi_read(spi_device, MACON1),
868 spi_read(spi_device, MACON3),
869 spi_read(spi_device, MACON4));
870
871 rt_kprintf("Rx : ERXST ERXND ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n");
872 rt_kprintf(" 0x%04X 0x%04X 0x%04X 0x%04X ",
873 (spi_read(spi_device, ERXSTH) << 8) | spi_read(spi_device, ERXSTL),
874 (spi_read(spi_device, ERXNDH) << 8) | spi_read(spi_device, ERXNDL),
875 (spi_read(spi_device, ERXWRPTH) << 8) | spi_read(spi_device, ERXWRPTL),
876 (spi_read(spi_device, ERXRDPTH) << 8) | spi_read(spi_device, ERXRDPTL));
877
878 rt_kprintf("0x%02X 0x%02X 0x%04X\n",
879 spi_read(spi_device, ERXFCON),
880 spi_read(spi_device, EPKTCNT),
881 (spi_read(spi_device, MAMXFLH) << 8) | spi_read(spi_device, MAMXFLL));
882
883 rt_kprintf("Tx : ETXST ETXND MACLCON1 MACLCON2 MAPHSUP\n");
884 rt_kprintf(" 0x%04X 0x%04X 0x%02X 0x%02X 0x%02X\n",
885 (spi_read(spi_device, ETXSTH) << 8) | spi_read(spi_device, ETXSTL),
886 (spi_read(spi_device, ETXNDH) << 8) | spi_read(spi_device, ETXNDL),
887 spi_read(spi_device, MACLCON1),
888 spi_read(spi_device, MACLCON2),
889 spi_read(spi_device, MAPHSUP));
890
891 rt_kprintf("PHY : PHCON1 PHSTAT1\r\n");
892 rt_kprintf(" 0x%04X 0x%04X\r\n",
893 enc28j60_phy_read(spi_device, PHCON1),
894 enc28j60_phy_read(spi_device, PHSTAT1));
895
896 enc28j60_unlock(&enc28j60_dev);
897 }
898 FINSH_FUNCTION_EXPORT(enc28j60, dump enc28j60 registers);
899 #endif
900