1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2021, Red Hat, Inc.
4 */
5
6 #ifndef SELFTEST_KVM_HYPERV_H
7 #define SELFTEST_KVM_HYPERV_H
8
9 #include "processor.h"
10
11 #define HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS 0x40000000
12 #define HYPERV_CPUID_INTERFACE 0x40000001
13 #define HYPERV_CPUID_VERSION 0x40000002
14 #define HYPERV_CPUID_FEATURES 0x40000003
15 #define HYPERV_CPUID_ENLIGHTMENT_INFO 0x40000004
16 #define HYPERV_CPUID_IMPLEMENT_LIMITS 0x40000005
17 #define HYPERV_CPUID_CPU_MANAGEMENT_FEATURES 0x40000007
18 #define HYPERV_CPUID_NESTED_FEATURES 0x4000000A
19 #define HYPERV_CPUID_SYNDBG_VENDOR_AND_MAX_FUNCTIONS 0x40000080
20 #define HYPERV_CPUID_SYNDBG_INTERFACE 0x40000081
21 #define HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES 0x40000082
22
23 #define HV_X64_MSR_GUEST_OS_ID 0x40000000
24 #define HV_X64_MSR_HYPERCALL 0x40000001
25 #define HV_X64_MSR_VP_INDEX 0x40000002
26 #define HV_X64_MSR_RESET 0x40000003
27 #define HV_X64_MSR_VP_RUNTIME 0x40000010
28 #define HV_X64_MSR_TIME_REF_COUNT 0x40000020
29 #define HV_X64_MSR_REFERENCE_TSC 0x40000021
30 #define HV_X64_MSR_TSC_FREQUENCY 0x40000022
31 #define HV_X64_MSR_APIC_FREQUENCY 0x40000023
32 #define HV_X64_MSR_EOI 0x40000070
33 #define HV_X64_MSR_ICR 0x40000071
34 #define HV_X64_MSR_TPR 0x40000072
35 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073
36 #define HV_X64_MSR_SCONTROL 0x40000080
37 #define HV_X64_MSR_SVERSION 0x40000081
38 #define HV_X64_MSR_SIEFP 0x40000082
39 #define HV_X64_MSR_SIMP 0x40000083
40 #define HV_X64_MSR_EOM 0x40000084
41 #define HV_X64_MSR_SINT0 0x40000090
42 #define HV_X64_MSR_SINT1 0x40000091
43 #define HV_X64_MSR_SINT2 0x40000092
44 #define HV_X64_MSR_SINT3 0x40000093
45 #define HV_X64_MSR_SINT4 0x40000094
46 #define HV_X64_MSR_SINT5 0x40000095
47 #define HV_X64_MSR_SINT6 0x40000096
48 #define HV_X64_MSR_SINT7 0x40000097
49 #define HV_X64_MSR_SINT8 0x40000098
50 #define HV_X64_MSR_SINT9 0x40000099
51 #define HV_X64_MSR_SINT10 0x4000009A
52 #define HV_X64_MSR_SINT11 0x4000009B
53 #define HV_X64_MSR_SINT12 0x4000009C
54 #define HV_X64_MSR_SINT13 0x4000009D
55 #define HV_X64_MSR_SINT14 0x4000009E
56 #define HV_X64_MSR_SINT15 0x4000009F
57 #define HV_X64_MSR_STIMER0_CONFIG 0x400000B0
58 #define HV_X64_MSR_STIMER0_COUNT 0x400000B1
59 #define HV_X64_MSR_STIMER1_CONFIG 0x400000B2
60 #define HV_X64_MSR_STIMER1_COUNT 0x400000B3
61 #define HV_X64_MSR_STIMER2_CONFIG 0x400000B4
62 #define HV_X64_MSR_STIMER2_COUNT 0x400000B5
63 #define HV_X64_MSR_STIMER3_CONFIG 0x400000B6
64 #define HV_X64_MSR_STIMER3_COUNT 0x400000B7
65 #define HV_X64_MSR_GUEST_IDLE 0x400000F0
66 #define HV_X64_MSR_CRASH_P0 0x40000100
67 #define HV_X64_MSR_CRASH_P1 0x40000101
68 #define HV_X64_MSR_CRASH_P2 0x40000102
69 #define HV_X64_MSR_CRASH_P3 0x40000103
70 #define HV_X64_MSR_CRASH_P4 0x40000104
71 #define HV_X64_MSR_CRASH_CTL 0x40000105
72 #define HV_X64_MSR_REENLIGHTENMENT_CONTROL 0x40000106
73 #define HV_X64_MSR_TSC_EMULATION_CONTROL 0x40000107
74 #define HV_X64_MSR_TSC_EMULATION_STATUS 0x40000108
75 #define HV_X64_MSR_TSC_INVARIANT_CONTROL 0x40000118
76
77 #define HV_X64_MSR_SYNDBG_CONTROL 0x400000F1
78 #define HV_X64_MSR_SYNDBG_STATUS 0x400000F2
79 #define HV_X64_MSR_SYNDBG_SEND_BUFFER 0x400000F3
80 #define HV_X64_MSR_SYNDBG_RECV_BUFFER 0x400000F4
81 #define HV_X64_MSR_SYNDBG_PENDING_BUFFER 0x400000F5
82 #define HV_X64_MSR_SYNDBG_OPTIONS 0x400000FF
83
84 /* HYPERV_CPUID_FEATURES.EAX */
85 #define HV_MSR_VP_RUNTIME_AVAILABLE \
86 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 0)
87 #define HV_MSR_TIME_REF_COUNT_AVAILABLE \
88 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 1)
89 #define HV_MSR_SYNIC_AVAILABLE \
90 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 2)
91 #define HV_MSR_SYNTIMER_AVAILABLE \
92 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 3)
93 #define HV_MSR_APIC_ACCESS_AVAILABLE \
94 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 4)
95 #define HV_MSR_HYPERCALL_AVAILABLE \
96 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 5)
97 #define HV_MSR_VP_INDEX_AVAILABLE \
98 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 6)
99 #define HV_MSR_RESET_AVAILABLE \
100 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 7)
101 #define HV_MSR_STAT_PAGES_AVAILABLE \
102 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 8)
103 #define HV_MSR_REFERENCE_TSC_AVAILABLE \
104 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 9)
105 #define HV_MSR_GUEST_IDLE_AVAILABLE \
106 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 10)
107 #define HV_ACCESS_FREQUENCY_MSRS \
108 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 11)
109 #define HV_ACCESS_REENLIGHTENMENT \
110 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 13)
111 #define HV_ACCESS_TSC_INVARIANT \
112 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EAX, 15)
113
114 /* HYPERV_CPUID_FEATURES.EBX */
115 #define HV_CREATE_PARTITIONS \
116 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 0)
117 #define HV_ACCESS_PARTITION_ID \
118 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 1)
119 #define HV_ACCESS_MEMORY_POOL \
120 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 2)
121 #define HV_ADJUST_MESSAGE_BUFFERS \
122 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 3)
123 #define HV_POST_MESSAGES \
124 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 4)
125 #define HV_SIGNAL_EVENTS \
126 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 5)
127 #define HV_CREATE_PORT \
128 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 6)
129 #define HV_CONNECT_PORT \
130 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 7)
131 #define HV_ACCESS_STATS \
132 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 8)
133 #define HV_DEBUGGING \
134 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 11)
135 #define HV_CPU_MANAGEMENT \
136 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 12)
137 #define HV_ENABLE_EXTENDED_HYPERCALLS \
138 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 20)
139 #define HV_ISOLATION \
140 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EBX, 22)
141
142 /* HYPERV_CPUID_FEATURES.EDX */
143 #define HV_X64_MWAIT_AVAILABLE \
144 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 0)
145 #define HV_X64_GUEST_DEBUGGING_AVAILABLE \
146 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 1)
147 #define HV_X64_PERF_MONITOR_AVAILABLE \
148 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 2)
149 #define HV_X64_CPU_DYNAMIC_PARTITIONING_AVAILABLE \
150 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 3)
151 #define HV_X64_HYPERCALL_XMM_INPUT_AVAILABLE \
152 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 4)
153 #define HV_X64_GUEST_IDLE_STATE_AVAILABLE \
154 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 5)
155 #define HV_FEATURE_FREQUENCY_MSRS_AVAILABLE \
156 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 8)
157 #define HV_FEATURE_GUEST_CRASH_MSR_AVAILABLE \
158 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 10)
159 #define HV_FEATURE_DEBUG_MSRS_AVAILABLE \
160 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 11)
161 #define HV_STIMER_DIRECT_MODE_AVAILABLE \
162 KVM_X86_CPU_FEATURE(HYPERV_CPUID_FEATURES, 0, EDX, 19)
163
164 /* HYPERV_CPUID_ENLIGHTMENT_INFO.EAX */
165 #define HV_X64_AS_SWITCH_RECOMMENDED \
166 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 0)
167 #define HV_X64_LOCAL_TLB_FLUSH_RECOMMENDED \
168 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 1)
169 #define HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED \
170 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 2)
171 #define HV_X64_APIC_ACCESS_RECOMMENDED \
172 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 3)
173 #define HV_X64_SYSTEM_RESET_RECOMMENDED \
174 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 4)
175 #define HV_X64_RELAXED_TIMING_RECOMMENDED \
176 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 5)
177 #define HV_DEPRECATING_AEOI_RECOMMENDED \
178 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 9)
179 #define HV_X64_CLUSTER_IPI_RECOMMENDED \
180 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 10)
181 #define HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED \
182 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 11)
183 #define HV_X64_ENLIGHTENED_VMCS_RECOMMENDED \
184 KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EAX, 14)
185
186 /* HYPERV_CPUID_NESTED_FEATURES.EAX */
187 #define HV_X64_NESTED_DIRECT_FLUSH \
188 KVM_X86_CPU_FEATURE(HYPERV_CPUID_NESTED_FEATURES, 0, EAX, 17)
189 #define HV_X64_NESTED_GUEST_MAPPING_FLUSH \
190 KVM_X86_CPU_FEATURE(HYPERV_CPUID_NESTED_FEATURES, 0, EAX, 18)
191 #define HV_X64_NESTED_MSR_BITMAP \
192 KVM_X86_CPU_FEATURE(HYPERV_CPUID_NESTED_FEATURES, 0, EAX, 19)
193
194 /* HYPERV_CPUID_NESTED_FEATURES.EBX */
195 #define HV_X64_NESTED_EVMCS1_PERF_GLOBAL_CTRL \
196 KVM_X86_CPU_FEATURE(HYPERV_CPUID_NESTED_FEATURES, 0, EBX, 0)
197
198 /* HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES.EAX */
199 #define HV_X64_SYNDBG_CAP_ALLOW_KERNEL_DEBUGGING \
200 KVM_X86_CPU_FEATURE(HYPERV_CPUID_SYNDBG_PLATFORM_CAPABILITIES, 0, EAX, 1)
201
202 /* Hypercalls */
203 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE 0x0002
204 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST 0x0003
205 #define HVCALL_NOTIFY_LONG_SPIN_WAIT 0x0008
206 #define HVCALL_SEND_IPI 0x000b
207 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX 0x0013
208 #define HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX 0x0014
209 #define HVCALL_SEND_IPI_EX 0x0015
210 #define HVCALL_GET_PARTITION_ID 0x0046
211 #define HVCALL_DEPOSIT_MEMORY 0x0048
212 #define HVCALL_CREATE_VP 0x004e
213 #define HVCALL_GET_VP_REGISTERS 0x0050
214 #define HVCALL_SET_VP_REGISTERS 0x0051
215 #define HVCALL_POST_MESSAGE 0x005c
216 #define HVCALL_SIGNAL_EVENT 0x005d
217 #define HVCALL_POST_DEBUG_DATA 0x0069
218 #define HVCALL_RETRIEVE_DEBUG_DATA 0x006a
219 #define HVCALL_RESET_DEBUG_SESSION 0x006b
220 #define HVCALL_ADD_LOGICAL_PROCESSOR 0x0076
221 #define HVCALL_MAP_DEVICE_INTERRUPT 0x007c
222 #define HVCALL_UNMAP_DEVICE_INTERRUPT 0x007d
223 #define HVCALL_RETARGET_INTERRUPT 0x007e
224 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE 0x00af
225 #define HVCALL_FLUSH_GUEST_PHYSICAL_ADDRESS_LIST 0x00b0
226
227 /* Extended hypercalls */
228 #define HV_EXT_CALL_QUERY_CAPABILITIES 0x8001
229
230 #define HV_FLUSH_ALL_PROCESSORS BIT(0)
231 #define HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES BIT(1)
232 #define HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY BIT(2)
233 #define HV_FLUSH_USE_EXTENDED_RANGE_FORMAT BIT(3)
234
235 /* hypercall status code */
236 #define HV_STATUS_SUCCESS 0
237 #define HV_STATUS_INVALID_HYPERCALL_CODE 2
238 #define HV_STATUS_INVALID_HYPERCALL_INPUT 3
239 #define HV_STATUS_INVALID_ALIGNMENT 4
240 #define HV_STATUS_INVALID_PARAMETER 5
241 #define HV_STATUS_ACCESS_DENIED 6
242 #define HV_STATUS_OPERATION_DENIED 8
243 #define HV_STATUS_INSUFFICIENT_MEMORY 11
244 #define HV_STATUS_INVALID_PORT_ID 17
245 #define HV_STATUS_INVALID_CONNECTION_ID 18
246 #define HV_STATUS_INSUFFICIENT_BUFFERS 19
247
248 /* hypercall options */
249 #define HV_HYPERCALL_FAST_BIT BIT(16)
250 #define HV_HYPERCALL_VARHEAD_OFFSET 17
251 #define HV_HYPERCALL_REP_COMP_OFFSET 32
252
253 /*
254 * Issue a Hyper-V hypercall. Returns exception vector raised or 0, 'hv_status'
255 * is set to the hypercall status (if no exception occurred).
256 */
__hyperv_hypercall(u64 control,vm_vaddr_t input_address,vm_vaddr_t output_address,uint64_t * hv_status)257 static inline uint8_t __hyperv_hypercall(u64 control, vm_vaddr_t input_address,
258 vm_vaddr_t output_address,
259 uint64_t *hv_status)
260 {
261 uint64_t error_code;
262 uint8_t vector;
263
264 /* Note both the hypercall and the "asm safe" clobber r9-r11. */
265 asm volatile("mov %[output_address], %%r8\n\t"
266 KVM_ASM_SAFE("vmcall")
267 : "=a" (*hv_status),
268 "+c" (control), "+d" (input_address),
269 KVM_ASM_SAFE_OUTPUTS(vector, error_code)
270 : [output_address] "r"(output_address),
271 "a" (-EFAULT)
272 : "cc", "memory", "r8", KVM_ASM_SAFE_CLOBBERS);
273 return vector;
274 }
275
276 /* Issue a Hyper-V hypercall and assert that it succeeded. */
hyperv_hypercall(u64 control,vm_vaddr_t input_address,vm_vaddr_t output_address)277 static inline void hyperv_hypercall(u64 control, vm_vaddr_t input_address,
278 vm_vaddr_t output_address)
279 {
280 uint64_t hv_status;
281 uint8_t vector;
282
283 vector = __hyperv_hypercall(control, input_address, output_address, &hv_status);
284
285 GUEST_ASSERT(!vector);
286 GUEST_ASSERT((hv_status & 0xffff) == 0);
287 }
288
289 /* Write 'Fast' hypercall input 'data' to the first 'n_sse_regs' SSE regs */
hyperv_write_xmm_input(void * data,int n_sse_regs)290 static inline void hyperv_write_xmm_input(void *data, int n_sse_regs)
291 {
292 int i;
293
294 for (i = 0; i < n_sse_regs; i++)
295 write_sse_reg(i, (sse128_t *)(data + sizeof(sse128_t) * i));
296 }
297
298 /* Proper HV_X64_MSR_GUEST_OS_ID value */
299 #define HYPERV_LINUX_OS_ID ((u64)0x8100 << 48)
300
301 #define HV_X64_MSR_VP_ASSIST_PAGE 0x40000073
302 #define HV_X64_MSR_VP_ASSIST_PAGE_ENABLE 0x00000001
303 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT 12
304 #define HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK \
305 (~((1ull << HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_SHIFT) - 1))
306
307 struct hv_nested_enlightenments_control {
308 struct {
309 __u32 directhypercall:1;
310 __u32 reserved:31;
311 } features;
312 struct {
313 __u32 reserved;
314 } hypercallControls;
315 } __packed;
316
317 /* Define virtual processor assist page structure. */
318 struct hv_vp_assist_page {
319 __u32 apic_assist;
320 __u32 reserved1;
321 __u64 vtl_control[3];
322 struct hv_nested_enlightenments_control nested_control;
323 __u8 enlighten_vmentry;
324 __u8 reserved2[7];
325 __u64 current_nested_vmcs;
326 } __packed;
327
328 extern struct hv_vp_assist_page *current_vp_assist;
329
330 int enable_vp_assist(uint64_t vp_assist_pa, void *vp_assist);
331
332 struct hyperv_test_pages {
333 /* VP assist page */
334 void *vp_assist_hva;
335 uint64_t vp_assist_gpa;
336 void *vp_assist;
337
338 /* Partition assist page */
339 void *partition_assist_hva;
340 uint64_t partition_assist_gpa;
341 void *partition_assist;
342
343 /* Enlightened VMCS */
344 void *enlightened_vmcs_hva;
345 uint64_t enlightened_vmcs_gpa;
346 void *enlightened_vmcs;
347 };
348
349 struct hyperv_test_pages *vcpu_alloc_hyperv_test_pages(struct kvm_vm *vm,
350 vm_vaddr_t *p_hv_pages_gva);
351
352 /* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */
353 #define HV_INVARIANT_TSC_EXPOSED BIT_ULL(0)
354
355 const struct kvm_cpuid2 *kvm_get_supported_hv_cpuid(void);
356 const struct kvm_cpuid2 *vcpu_get_supported_hv_cpuid(struct kvm_vcpu *vcpu);
357 void vcpu_set_hv_cpuid(struct kvm_vcpu *vcpu);
358
359 bool kvm_hv_cpu_has(struct kvm_x86_cpu_feature feature);
360
361 #endif /* !SELFTEST_KVM_HYPERV_H */
362