1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * AArch64 processor specific defines
4 *
5 * Copyright (C) 2018, Red Hat, Inc.
6 */
7 #ifndef SELFTEST_KVM_PROCESSOR_H
8 #define SELFTEST_KVM_PROCESSOR_H
9
10 #include "kvm_util.h"
11 #include "ucall_common.h"
12
13 #include <linux/stringify.h>
14 #include <linux/types.h>
15 #include <asm/brk-imm.h>
16 #include <asm/esr.h>
17 #include <asm/sysreg.h>
18
19
20 #define ARM64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
21 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
22
23 /*
24 * KVM_ARM64_SYS_REG(sys_reg_id): Helper macro to convert
25 * SYS_* register definitions in asm/sysreg.h to use in KVM
26 * calls such as vcpu_get_reg() and vcpu_set_reg().
27 */
28 #define KVM_ARM64_SYS_REG(sys_reg_id) \
29 ARM64_SYS_REG(sys_reg_Op0(sys_reg_id), \
30 sys_reg_Op1(sys_reg_id), \
31 sys_reg_CRn(sys_reg_id), \
32 sys_reg_CRm(sys_reg_id), \
33 sys_reg_Op2(sys_reg_id))
34
35 /*
36 * Default MAIR
37 * index attribute
38 * DEVICE_nGnRnE 0 0000:0000
39 * DEVICE_nGnRE 1 0000:0100
40 * DEVICE_GRE 2 0000:1100
41 * NORMAL_NC 3 0100:0100
42 * NORMAL 4 1111:1111
43 * NORMAL_WT 5 1011:1011
44 */
45
46 /* Linux doesn't use these memory types, so let's define them. */
47 #define MAIR_ATTR_DEVICE_GRE UL(0x0c)
48 #define MAIR_ATTR_NORMAL_WT UL(0xbb)
49
50 #define MT_DEVICE_nGnRnE 0
51 #define MT_DEVICE_nGnRE 1
52 #define MT_DEVICE_GRE 2
53 #define MT_NORMAL_NC 3
54 #define MT_NORMAL 4
55 #define MT_NORMAL_WT 5
56
57 #define DEFAULT_MAIR_EL1 \
58 (MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRnE, MT_DEVICE_nGnRnE) | \
59 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_nGnRE, MT_DEVICE_nGnRE) | \
60 MAIR_ATTRIDX(MAIR_ATTR_DEVICE_GRE, MT_DEVICE_GRE) | \
61 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_NC, MT_NORMAL_NC) | \
62 MAIR_ATTRIDX(MAIR_ATTR_NORMAL, MT_NORMAL) | \
63 MAIR_ATTRIDX(MAIR_ATTR_NORMAL_WT, MT_NORMAL_WT))
64
65 void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init);
66 struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
67 struct kvm_vcpu_init *init, void *guest_code);
68
69 struct ex_regs {
70 u64 regs[31];
71 u64 sp;
72 u64 pc;
73 u64 pstate;
74 };
75
76 #define VECTOR_NUM 16
77
78 enum {
79 VECTOR_SYNC_CURRENT_SP0,
80 VECTOR_IRQ_CURRENT_SP0,
81 VECTOR_FIQ_CURRENT_SP0,
82 VECTOR_ERROR_CURRENT_SP0,
83
84 VECTOR_SYNC_CURRENT,
85 VECTOR_IRQ_CURRENT,
86 VECTOR_FIQ_CURRENT,
87 VECTOR_ERROR_CURRENT,
88
89 VECTOR_SYNC_LOWER_64,
90 VECTOR_IRQ_LOWER_64,
91 VECTOR_FIQ_LOWER_64,
92 VECTOR_ERROR_LOWER_64,
93
94 VECTOR_SYNC_LOWER_32,
95 VECTOR_IRQ_LOWER_32,
96 VECTOR_FIQ_LOWER_32,
97 VECTOR_ERROR_LOWER_32,
98 };
99
100 #define VECTOR_IS_SYNC(v) ((v) == VECTOR_SYNC_CURRENT_SP0 || \
101 (v) == VECTOR_SYNC_CURRENT || \
102 (v) == VECTOR_SYNC_LOWER_64 || \
103 (v) == VECTOR_SYNC_LOWER_32)
104
105 /* Access flag */
106 #define PTE_AF (1ULL << 10)
107
108 /* Access flag update enable/disable */
109 #define TCR_EL1_HA (1ULL << 39)
110
111 void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k,
112 uint32_t *ipa16k, uint32_t *ipa64k);
113
114 void vm_init_descriptor_tables(struct kvm_vm *vm);
115 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu);
116
117 typedef void(*handler_fn)(struct ex_regs *);
118 void vm_install_exception_handler(struct kvm_vm *vm,
119 int vector, handler_fn handler);
120 void vm_install_sync_handler(struct kvm_vm *vm,
121 int vector, int ec, handler_fn handler);
122
123 uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva);
124
cpu_relax(void)125 static inline void cpu_relax(void)
126 {
127 asm volatile("yield" ::: "memory");
128 }
129
130 #define isb() asm volatile("isb" : : : "memory")
131 #define dsb(opt) asm volatile("dsb " #opt : : : "memory")
132 #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
133
134 #define dma_wmb() dmb(oshst)
135 #define __iowmb() dma_wmb()
136
137 #define dma_rmb() dmb(oshld)
138
139 #define __iormb(v) \
140 ({ \
141 unsigned long tmp; \
142 \
143 dma_rmb(); \
144 \
145 /* \
146 * Courtesy of arch/arm64/include/asm/io.h: \
147 * Create a dummy control dependency from the IO read to any \
148 * later instructions. This ensures that a subsequent call \
149 * to udelay() will be ordered due to the ISB in __delay(). \
150 */ \
151 asm volatile("eor %0, %1, %1\n" \
152 "cbnz %0, ." \
153 : "=r" (tmp) : "r" ((unsigned long)(v)) \
154 : "memory"); \
155 })
156
__raw_writel(u32 val,volatile void * addr)157 static __always_inline void __raw_writel(u32 val, volatile void *addr)
158 {
159 asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
160 }
161
__raw_readl(const volatile void * addr)162 static __always_inline u32 __raw_readl(const volatile void *addr)
163 {
164 u32 val;
165 asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
166 return val;
167 }
168
__raw_writeq(u64 val,volatile void * addr)169 static __always_inline void __raw_writeq(u64 val, volatile void *addr)
170 {
171 asm volatile("str %0, [%1]" : : "rZ" (val), "r" (addr));
172 }
173
__raw_readq(const volatile void * addr)174 static __always_inline u64 __raw_readq(const volatile void *addr)
175 {
176 u64 val;
177 asm volatile("ldr %0, [%1]" : "=r" (val) : "r" (addr));
178 return val;
179 }
180
181 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
182 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
183 #define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c)))
184 #define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; })
185
186 #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));})
187 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
188 #define writeq(v,c) ({ __iowmb(); writeq_relaxed((v),(c));})
189 #define readq(c) ({ u64 __v = readq_relaxed(c); __iormb(__v); __v; })
190
191
local_irq_enable(void)192 static inline void local_irq_enable(void)
193 {
194 asm volatile("msr daifclr, #3" : : : "memory");
195 }
196
local_irq_disable(void)197 static inline void local_irq_disable(void)
198 {
199 asm volatile("msr daifset, #3" : : : "memory");
200 }
201
202 /**
203 * struct arm_smccc_res - Result from SMC/HVC call
204 * @a0-a3 result values from registers 0 to 3
205 */
206 struct arm_smccc_res {
207 unsigned long a0;
208 unsigned long a1;
209 unsigned long a2;
210 unsigned long a3;
211 };
212
213 /**
214 * smccc_hvc - Invoke a SMCCC function using the hvc conduit
215 * @function_id: the SMCCC function to be called
216 * @arg0-arg6: SMCCC function arguments, corresponding to registers x1-x7
217 * @res: pointer to write the return values from registers x0-x3
218 *
219 */
220 void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
221 uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
222 uint64_t arg6, struct arm_smccc_res *res);
223
224 /**
225 * smccc_smc - Invoke a SMCCC function using the smc conduit
226 * @function_id: the SMCCC function to be called
227 * @arg0-arg6: SMCCC function arguments, corresponding to registers x1-x7
228 * @res: pointer to write the return values from registers x0-x3
229 *
230 */
231 void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
232 uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
233 uint64_t arg6, struct arm_smccc_res *res);
234
235 /* Execute a Wait For Interrupt instruction. */
236 void wfi(void);
237
238 #endif /* SELFTEST_KVM_PROCESSOR_H */
239