1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
4
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/platform_device.h>
8 #include <linux/cleanup.h>
9 #include <linux/device.h>
10 #include <linux/wait.h>
11 #include <linux/bitops.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/kernel.h>
16 #include <linux/slimbus.h>
17 #include <sound/soc.h>
18 #include <sound/pcm_params.h>
19 #include <sound/soc-dapm.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <sound/tlv.h>
24 #include <sound/info.h>
25 #include "wcd9335.h"
26 #include "wcd-clsh-v2.h"
27
28 #include <dt-bindings/sound/qcom,wcd9335.h>
29
30 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
31 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
32 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
33 /* Fractional Rates */
34 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
35 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
36 SNDRV_PCM_FMTBIT_S24_LE)
37
38 /* slave port water mark level
39 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
40 */
41 #define SLAVE_PORT_WATER_MARK_6BYTES 0
42 #define SLAVE_PORT_WATER_MARK_9BYTES 1
43 #define SLAVE_PORT_WATER_MARK_12BYTES 2
44 #define SLAVE_PORT_WATER_MARK_15BYTES 3
45 #define SLAVE_PORT_WATER_MARK_SHIFT 1
46 #define SLAVE_PORT_ENABLE 1
47 #define SLAVE_PORT_DISABLE 0
48 #define WCD9335_SLIM_WATER_MARK_VAL \
49 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
50 (SLAVE_PORT_ENABLE))
51
52 #define WCD9335_SLIM_NUM_PORT_REG 3
53 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
54
55 #define WCD9335_MCLK_CLK_12P288MHZ 12288000
56 #define WCD9335_MCLK_CLK_9P6MHZ 9600000
57
58 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
59 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
60 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
61 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
62
63 #define WCD9335_NUM_INTERPOLATORS 9
64 #define WCD9335_RX_START 16
65 #define WCD9335_SLIM_CH_START 128
66 #define WCD9335_MAX_MICBIAS 4
67 #define WCD9335_MAX_VALID_ADC_MUX 13
68 #define WCD9335_INVALID_ADC_MUX 9
69
70 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
71 #define CF_MIN_3DB_4HZ 0x0
72 #define CF_MIN_3DB_75HZ 0x1
73 #define CF_MIN_3DB_150HZ 0x2
74 #define WCD9335_DMIC_CLK_DIV_2 0x0
75 #define WCD9335_DMIC_CLK_DIV_3 0x1
76 #define WCD9335_DMIC_CLK_DIV_4 0x2
77 #define WCD9335_DMIC_CLK_DIV_6 0x3
78 #define WCD9335_DMIC_CLK_DIV_8 0x4
79 #define WCD9335_DMIC_CLK_DIV_16 0x5
80 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
81 #define WCD9335_AMIC_PWR_LEVEL_LP 0
82 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
83 #define WCD9335_AMIC_PWR_LEVEL_HP 2
84 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
85 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
86
87 #define WCD9335_DEC_PWR_LVL_MASK 0x06
88 #define WCD9335_DEC_PWR_LVL_LP 0x02
89 #define WCD9335_DEC_PWR_LVL_HP 0x04
90 #define WCD9335_DEC_PWR_LVL_DF 0x00
91
92 #define WCD9335_SLIM_RX_CH(p) \
93 {.port = p + WCD9335_RX_START, .shift = p,}
94
95 #define WCD9335_SLIM_TX_CH(p) \
96 {.port = p, .shift = p,}
97
98 /* vout step value */
99 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
100
101 #define WCD9335_INTERPOLATOR_PATH(id) \
102 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
103 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
104 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
105 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
106 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
107 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
108 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
109 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
110 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
111 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
112 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
113 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
114 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
115 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
116 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
117 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
118 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
119 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
120 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
121 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
122 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
123 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
124 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
125 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
126 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
127 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
128 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
129 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
130 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
131 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
132 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
133 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
136 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
138 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
139 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
140 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
141
142 #define WCD9335_ADC_MUX_PATH(id) \
143 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
144 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
145 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
146 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
147 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
148 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
149 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
150 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
151 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
152 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
153 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
154 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
155 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
156 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
157 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
158 {"AMIC MUX" #id, "ADC4", "ADC4"}, \
159 {"AMIC MUX" #id, "ADC5", "ADC5"}, \
160 {"AMIC MUX" #id, "ADC6", "ADC6"}
161
162 #define NUM_CODEC_DAIS 7
163
164 enum {
165 WCD9335_RX0 = 0,
166 WCD9335_RX1,
167 WCD9335_RX2,
168 WCD9335_RX3,
169 WCD9335_RX4,
170 WCD9335_RX5,
171 WCD9335_RX6,
172 WCD9335_RX7,
173 WCD9335_RX8,
174 WCD9335_RX9,
175 WCD9335_RX10,
176 WCD9335_RX11,
177 WCD9335_RX12,
178 WCD9335_RX_MAX,
179 };
180
181 enum {
182 WCD9335_TX0 = 0,
183 WCD9335_TX1,
184 WCD9335_TX2,
185 WCD9335_TX3,
186 WCD9335_TX4,
187 WCD9335_TX5,
188 WCD9335_TX6,
189 WCD9335_TX7,
190 WCD9335_TX8,
191 WCD9335_TX9,
192 WCD9335_TX10,
193 WCD9335_TX11,
194 WCD9335_TX12,
195 WCD9335_TX13,
196 WCD9335_TX14,
197 WCD9335_TX15,
198 WCD9335_TX_MAX,
199 };
200
201 enum {
202 SIDO_SOURCE_INTERNAL = 0,
203 SIDO_SOURCE_RCO_BG,
204 };
205
206 enum wcd9335_sido_voltage {
207 SIDO_VOLTAGE_SVS_MV = 950,
208 SIDO_VOLTAGE_NOMINAL_MV = 1100,
209 };
210
211 enum {
212 COMPANDER_1, /* HPH_L */
213 COMPANDER_2, /* HPH_R */
214 COMPANDER_3, /* LO1_DIFF */
215 COMPANDER_4, /* LO2_DIFF */
216 COMPANDER_5, /* LO3_SE */
217 COMPANDER_6, /* LO4_SE */
218 COMPANDER_7, /* SWR SPK CH1 */
219 COMPANDER_8, /* SWR SPK CH2 */
220 COMPANDER_MAX,
221 };
222
223 enum {
224 INTn_2_INP_SEL_ZERO = 0,
225 INTn_2_INP_SEL_RX0,
226 INTn_2_INP_SEL_RX1,
227 INTn_2_INP_SEL_RX2,
228 INTn_2_INP_SEL_RX3,
229 INTn_2_INP_SEL_RX4,
230 INTn_2_INP_SEL_RX5,
231 INTn_2_INP_SEL_RX6,
232 INTn_2_INP_SEL_RX7,
233 INTn_2_INP_SEL_PROXIMITY,
234 };
235
236 enum {
237 INTn_1_MIX_INP_SEL_ZERO = 0,
238 INTn_1_MIX_INP_SEL_DEC0,
239 INTn_1_MIX_INP_SEL_DEC1,
240 INTn_1_MIX_INP_SEL_IIR0,
241 INTn_1_MIX_INP_SEL_IIR1,
242 INTn_1_MIX_INP_SEL_RX0,
243 INTn_1_MIX_INP_SEL_RX1,
244 INTn_1_MIX_INP_SEL_RX2,
245 INTn_1_MIX_INP_SEL_RX3,
246 INTn_1_MIX_INP_SEL_RX4,
247 INTn_1_MIX_INP_SEL_RX5,
248 INTn_1_MIX_INP_SEL_RX6,
249 INTn_1_MIX_INP_SEL_RX7,
250
251 };
252
253 enum {
254 INTERP_EAR = 0,
255 INTERP_HPHL,
256 INTERP_HPHR,
257 INTERP_LO1,
258 INTERP_LO2,
259 INTERP_LO3,
260 INTERP_LO4,
261 INTERP_SPKR1,
262 INTERP_SPKR2,
263 };
264
265 enum wcd_clock_type {
266 WCD_CLK_OFF,
267 WCD_CLK_RCO,
268 WCD_CLK_MCLK,
269 };
270
271 enum {
272 MIC_BIAS_1 = 1,
273 MIC_BIAS_2,
274 MIC_BIAS_3,
275 MIC_BIAS_4
276 };
277
278 enum {
279 MICB_PULLUP_ENABLE,
280 MICB_PULLUP_DISABLE,
281 MICB_ENABLE,
282 MICB_DISABLE,
283 };
284
285 struct wcd9335_slim_ch {
286 u32 ch_num;
287 u16 port;
288 u16 shift;
289 struct list_head list;
290 };
291
292 struct wcd_slim_codec_dai_data {
293 struct list_head slim_ch_list;
294 struct slim_stream_config sconfig;
295 struct slim_stream_runtime *sruntime;
296 };
297
298 struct wcd9335_codec {
299 struct device *dev;
300 struct clk *mclk;
301 struct clk *native_clk;
302 u32 mclk_rate;
303
304 struct slim_device *slim;
305 struct slim_device *slim_ifc_dev;
306 struct regmap *regmap;
307 struct regmap *if_regmap;
308 struct regmap_irq_chip_data *irq_data;
309
310 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
311 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
312 u32 num_rx_port;
313 u32 num_tx_port;
314
315 int sido_input_src;
316 enum wcd9335_sido_voltage sido_voltage;
317
318 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
319 struct snd_soc_component *component;
320
321 int master_bias_users;
322 int clk_mclk_users;
323 int clk_rco_users;
324 int sido_ccl_cnt;
325 enum wcd_clock_type clk_type;
326
327 struct wcd_clsh_ctrl *clsh_ctrl;
328 u32 hph_mode;
329 int prim_int_users[WCD9335_NUM_INTERPOLATORS];
330
331 int comp_enabled[COMPANDER_MAX];
332
333 int intr1;
334 int reset_gpio;
335 struct regulator_bulk_data supplies[WCD9335_MAX_SUPPLY];
336
337 unsigned int rx_port_value[WCD9335_RX_MAX];
338 unsigned int tx_port_value[WCD9335_TX_MAX];
339 int hph_l_gain;
340 int hph_r_gain;
341 u32 rx_bias_count;
342
343 /*TX*/
344 int micb_ref[WCD9335_MAX_MICBIAS];
345 int pullup_ref[WCD9335_MAX_MICBIAS];
346
347 int dmic_0_1_clk_cnt;
348 int dmic_2_3_clk_cnt;
349 int dmic_4_5_clk_cnt;
350 };
351
352 struct wcd9335_irq {
353 int irq;
354 irqreturn_t (*handler)(int irq, void *data);
355 char *name;
356 };
357
358 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
359 WCD9335_SLIM_TX_CH(0),
360 WCD9335_SLIM_TX_CH(1),
361 WCD9335_SLIM_TX_CH(2),
362 WCD9335_SLIM_TX_CH(3),
363 WCD9335_SLIM_TX_CH(4),
364 WCD9335_SLIM_TX_CH(5),
365 WCD9335_SLIM_TX_CH(6),
366 WCD9335_SLIM_TX_CH(7),
367 WCD9335_SLIM_TX_CH(8),
368 WCD9335_SLIM_TX_CH(9),
369 WCD9335_SLIM_TX_CH(10),
370 WCD9335_SLIM_TX_CH(11),
371 WCD9335_SLIM_TX_CH(12),
372 WCD9335_SLIM_TX_CH(13),
373 WCD9335_SLIM_TX_CH(14),
374 WCD9335_SLIM_TX_CH(15),
375 };
376
377 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
378 WCD9335_SLIM_RX_CH(0), /* 16 */
379 WCD9335_SLIM_RX_CH(1), /* 17 */
380 WCD9335_SLIM_RX_CH(2),
381 WCD9335_SLIM_RX_CH(3),
382 WCD9335_SLIM_RX_CH(4),
383 WCD9335_SLIM_RX_CH(5),
384 WCD9335_SLIM_RX_CH(6),
385 WCD9335_SLIM_RX_CH(7),
386 WCD9335_SLIM_RX_CH(8),
387 WCD9335_SLIM_RX_CH(9),
388 WCD9335_SLIM_RX_CH(10),
389 WCD9335_SLIM_RX_CH(11),
390 WCD9335_SLIM_RX_CH(12),
391 };
392
393 struct interp_sample_rate {
394 int rate;
395 int rate_val;
396 };
397
398 static const struct interp_sample_rate int_mix_rate_val[] = {
399 {48000, 0x4}, /* 48K */
400 {96000, 0x5}, /* 96K */
401 {192000, 0x6}, /* 192K */
402 };
403
404 static const struct interp_sample_rate int_prim_rate_val[] = {
405 {8000, 0x0}, /* 8K */
406 {16000, 0x1}, /* 16K */
407 {24000, -EINVAL},/* 24K */
408 {32000, 0x3}, /* 32K */
409 {48000, 0x4}, /* 48K */
410 {96000, 0x5}, /* 96K */
411 {192000, 0x6}, /* 192K */
412 {384000, 0x7}, /* 384K */
413 {44100, 0x8}, /* 44.1K */
414 };
415
416 struct wcd9335_reg_mask_val {
417 u16 reg;
418 u8 mask;
419 u8 val;
420 };
421
422 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
423 /* Rbuckfly/R_EAR(32) */
424 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
425 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
426 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
427 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
428 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
429 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
430 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
431 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
432 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
433 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
434 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
435 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
436 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
437 {WCD9335_EAR_CMBUFF, 0x08, 0x00},
438 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
439 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
440 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
441 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
442 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
443 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
444 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
445 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
446 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
447 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
448 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
449 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
450 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
451 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
452 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
453 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
454 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
455 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
456 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
457 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
458 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
459 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
460 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
461 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
462 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
463 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
464 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
465 {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
466 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
467 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
468 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
469 {WCD9335_HPH_L_TEST, 0x01, 0x01},
470 {WCD9335_HPH_R_TEST, 0x01, 0x01},
471 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
472 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
473 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
474 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
475 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
476 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
477 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
478 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
479 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
480 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
481 };
482
483 /* Cutoff frequency for high pass filter */
484 static const char * const cf_text[] = {
485 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
486 };
487
488 static const char * const rx_cf_text[] = {
489 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
490 "CF_NEG_3DB_0P48HZ"
491 };
492
493 static const char * const rx_int0_7_mix_mux_text[] = {
494 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
495 "RX6", "RX7", "PROXIMITY"
496 };
497
498 static const char * const rx_int_mix_mux_text[] = {
499 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
500 "RX6", "RX7"
501 };
502
503 static const char * const rx_prim_mix_text[] = {
504 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
505 "RX3", "RX4", "RX5", "RX6", "RX7"
506 };
507
508 static const char * const rx_int_dem_inp_mux_text[] = {
509 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
510 };
511
512 static const char * const rx_int0_interp_mux_text[] = {
513 "ZERO", "RX INT0 MIX2",
514 };
515
516 static const char * const rx_int1_interp_mux_text[] = {
517 "ZERO", "RX INT1 MIX2",
518 };
519
520 static const char * const rx_int2_interp_mux_text[] = {
521 "ZERO", "RX INT2 MIX2",
522 };
523
524 static const char * const rx_int3_interp_mux_text[] = {
525 "ZERO", "RX INT3 MIX2",
526 };
527
528 static const char * const rx_int4_interp_mux_text[] = {
529 "ZERO", "RX INT4 MIX2",
530 };
531
532 static const char * const rx_int5_interp_mux_text[] = {
533 "ZERO", "RX INT5 MIX2",
534 };
535
536 static const char * const rx_int6_interp_mux_text[] = {
537 "ZERO", "RX INT6 MIX2",
538 };
539
540 static const char * const rx_int7_interp_mux_text[] = {
541 "ZERO", "RX INT7 MIX2",
542 };
543
544 static const char * const rx_int8_interp_mux_text[] = {
545 "ZERO", "RX INT8 SEC MIX"
546 };
547
548 static const char * const rx_hph_mode_mux_text[] = {
549 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
550 "Class-H Hi-Fi Low Power"
551 };
552
553 static const char *const slim_rx_mux_text[] = {
554 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
555 };
556
557 static const char * const adc_mux_text[] = {
558 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
559 };
560
561 static const char * const dmic_mux_text[] = {
562 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
563 "SMIC0", "SMIC1", "SMIC2", "SMIC3"
564 };
565
566 static const char * const dmic_mux_alt_text[] = {
567 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
568 };
569
570 static const char * const amic_mux_text[] = {
571 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
572 };
573
574 static const char * const sb_tx0_mux_text[] = {
575 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
576 };
577
578 static const char * const sb_tx1_mux_text[] = {
579 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
580 };
581
582 static const char * const sb_tx2_mux_text[] = {
583 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
584 };
585
586 static const char * const sb_tx3_mux_text[] = {
587 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
588 };
589
590 static const char * const sb_tx4_mux_text[] = {
591 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
592 };
593
594 static const char * const sb_tx5_mux_text[] = {
595 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
596 };
597
598 static const char * const sb_tx6_mux_text[] = {
599 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
600 };
601
602 static const char * const sb_tx7_mux_text[] = {
603 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
604 };
605
606 static const char * const sb_tx8_mux_text[] = {
607 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
608 };
609
610 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
611 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
612 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
613 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
614
615 static const struct soc_enum cf_dec0_enum =
616 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
617
618 static const struct soc_enum cf_dec1_enum =
619 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
620
621 static const struct soc_enum cf_dec2_enum =
622 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
623
624 static const struct soc_enum cf_dec3_enum =
625 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
626
627 static const struct soc_enum cf_dec4_enum =
628 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
629
630 static const struct soc_enum cf_dec5_enum =
631 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
632
633 static const struct soc_enum cf_dec6_enum =
634 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
635
636 static const struct soc_enum cf_dec7_enum =
637 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
638
639 static const struct soc_enum cf_dec8_enum =
640 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
641
642 static const struct soc_enum cf_int0_1_enum =
643 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
644
645 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
646 rx_cf_text);
647
648 static const struct soc_enum cf_int1_1_enum =
649 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
650
651 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
652 rx_cf_text);
653
654 static const struct soc_enum cf_int2_1_enum =
655 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
656
657 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
658 rx_cf_text);
659
660 static const struct soc_enum cf_int3_1_enum =
661 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
662
663 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
664 rx_cf_text);
665
666 static const struct soc_enum cf_int4_1_enum =
667 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
668
669 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
670 rx_cf_text);
671
672 static const struct soc_enum cf_int5_1_enum =
673 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
674
675 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
676 rx_cf_text);
677
678 static const struct soc_enum cf_int6_1_enum =
679 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
680
681 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
682 rx_cf_text);
683
684 static const struct soc_enum cf_int7_1_enum =
685 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
686
687 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
688 rx_cf_text);
689
690 static const struct soc_enum cf_int8_1_enum =
691 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
692
693 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
694 rx_cf_text);
695
696 static const struct soc_enum rx_hph_mode_mux_enum =
697 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
698 rx_hph_mode_mux_text);
699
700 static const struct soc_enum slim_rx_mux_enum =
701 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
702
703 static const struct soc_enum rx_int0_2_mux_chain_enum =
704 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
705 rx_int0_7_mix_mux_text);
706
707 static const struct soc_enum rx_int1_2_mux_chain_enum =
708 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
709 rx_int_mix_mux_text);
710
711 static const struct soc_enum rx_int2_2_mux_chain_enum =
712 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
713 rx_int_mix_mux_text);
714
715 static const struct soc_enum rx_int3_2_mux_chain_enum =
716 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
717 rx_int_mix_mux_text);
718
719 static const struct soc_enum rx_int4_2_mux_chain_enum =
720 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
721 rx_int_mix_mux_text);
722
723 static const struct soc_enum rx_int5_2_mux_chain_enum =
724 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
725 rx_int_mix_mux_text);
726
727 static const struct soc_enum rx_int6_2_mux_chain_enum =
728 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
729 rx_int_mix_mux_text);
730
731 static const struct soc_enum rx_int7_2_mux_chain_enum =
732 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
733 rx_int0_7_mix_mux_text);
734
735 static const struct soc_enum rx_int8_2_mux_chain_enum =
736 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
737 rx_int_mix_mux_text);
738
739 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
740 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
741 rx_prim_mix_text);
742
743 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
744 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
745 rx_prim_mix_text);
746
747 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
748 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
749 rx_prim_mix_text);
750
751 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
752 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
753 rx_prim_mix_text);
754
755 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
756 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
757 rx_prim_mix_text);
758
759 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
760 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
761 rx_prim_mix_text);
762
763 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
764 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
765 rx_prim_mix_text);
766
767 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
768 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
769 rx_prim_mix_text);
770
771 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
772 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
773 rx_prim_mix_text);
774
775 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
776 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
777 rx_prim_mix_text);
778
779 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
780 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
781 rx_prim_mix_text);
782
783 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
784 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
785 rx_prim_mix_text);
786
787 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
788 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
789 rx_prim_mix_text);
790
791 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
792 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
793 rx_prim_mix_text);
794
795 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
796 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
797 rx_prim_mix_text);
798
799 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
800 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
801 rx_prim_mix_text);
802
803 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
804 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
805 rx_prim_mix_text);
806
807 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
808 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
809 rx_prim_mix_text);
810
811 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
812 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
813 rx_prim_mix_text);
814
815 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
816 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
817 rx_prim_mix_text);
818
819 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
820 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
821 rx_prim_mix_text);
822
823 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
824 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
825 rx_prim_mix_text);
826
827 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
828 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
829 rx_prim_mix_text);
830
831 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
832 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
833 rx_prim_mix_text);
834
835 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
836 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
837 rx_prim_mix_text);
838
839 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
840 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
841 rx_prim_mix_text);
842
843 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
844 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
845 rx_prim_mix_text);
846
847 static const struct soc_enum rx_int0_dem_inp_mux_enum =
848 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
849 ARRAY_SIZE(rx_int_dem_inp_mux_text),
850 rx_int_dem_inp_mux_text);
851
852 static const struct soc_enum rx_int1_dem_inp_mux_enum =
853 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
854 ARRAY_SIZE(rx_int_dem_inp_mux_text),
855 rx_int_dem_inp_mux_text);
856
857 static const struct soc_enum rx_int2_dem_inp_mux_enum =
858 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
859 ARRAY_SIZE(rx_int_dem_inp_mux_text),
860 rx_int_dem_inp_mux_text);
861
862 static const struct soc_enum rx_int0_interp_mux_enum =
863 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
864 rx_int0_interp_mux_text);
865
866 static const struct soc_enum rx_int1_interp_mux_enum =
867 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
868 rx_int1_interp_mux_text);
869
870 static const struct soc_enum rx_int2_interp_mux_enum =
871 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
872 rx_int2_interp_mux_text);
873
874 static const struct soc_enum rx_int3_interp_mux_enum =
875 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
876 rx_int3_interp_mux_text);
877
878 static const struct soc_enum rx_int4_interp_mux_enum =
879 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
880 rx_int4_interp_mux_text);
881
882 static const struct soc_enum rx_int5_interp_mux_enum =
883 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
884 rx_int5_interp_mux_text);
885
886 static const struct soc_enum rx_int6_interp_mux_enum =
887 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
888 rx_int6_interp_mux_text);
889
890 static const struct soc_enum rx_int7_interp_mux_enum =
891 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
892 rx_int7_interp_mux_text);
893
894 static const struct soc_enum rx_int8_interp_mux_enum =
895 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
896 rx_int8_interp_mux_text);
897
898 static const struct soc_enum tx_adc_mux0_chain_enum =
899 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
900 adc_mux_text);
901
902 static const struct soc_enum tx_adc_mux1_chain_enum =
903 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
904 adc_mux_text);
905
906 static const struct soc_enum tx_adc_mux2_chain_enum =
907 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
908 adc_mux_text);
909
910 static const struct soc_enum tx_adc_mux3_chain_enum =
911 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
912 adc_mux_text);
913
914 static const struct soc_enum tx_adc_mux4_chain_enum =
915 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
916 adc_mux_text);
917
918 static const struct soc_enum tx_adc_mux5_chain_enum =
919 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
920 adc_mux_text);
921
922 static const struct soc_enum tx_adc_mux6_chain_enum =
923 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
924 adc_mux_text);
925
926 static const struct soc_enum tx_adc_mux7_chain_enum =
927 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
928 adc_mux_text);
929
930 static const struct soc_enum tx_adc_mux8_chain_enum =
931 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
932 adc_mux_text);
933
934 static const struct soc_enum tx_dmic_mux0_enum =
935 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
936 dmic_mux_text);
937
938 static const struct soc_enum tx_dmic_mux1_enum =
939 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
940 dmic_mux_text);
941
942 static const struct soc_enum tx_dmic_mux2_enum =
943 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
944 dmic_mux_text);
945
946 static const struct soc_enum tx_dmic_mux3_enum =
947 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
948 dmic_mux_text);
949
950 static const struct soc_enum tx_dmic_mux4_enum =
951 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
952 dmic_mux_alt_text);
953
954 static const struct soc_enum tx_dmic_mux5_enum =
955 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
956 dmic_mux_alt_text);
957
958 static const struct soc_enum tx_dmic_mux6_enum =
959 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
960 dmic_mux_alt_text);
961
962 static const struct soc_enum tx_dmic_mux7_enum =
963 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
964 dmic_mux_alt_text);
965
966 static const struct soc_enum tx_dmic_mux8_enum =
967 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
968 dmic_mux_alt_text);
969
970 static const struct soc_enum tx_amic_mux0_enum =
971 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
972 amic_mux_text);
973
974 static const struct soc_enum tx_amic_mux1_enum =
975 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
976 amic_mux_text);
977
978 static const struct soc_enum tx_amic_mux2_enum =
979 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
980 amic_mux_text);
981
982 static const struct soc_enum tx_amic_mux3_enum =
983 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
984 amic_mux_text);
985
986 static const struct soc_enum tx_amic_mux4_enum =
987 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
988 amic_mux_text);
989
990 static const struct soc_enum tx_amic_mux5_enum =
991 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
992 amic_mux_text);
993
994 static const struct soc_enum tx_amic_mux6_enum =
995 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
996 amic_mux_text);
997
998 static const struct soc_enum tx_amic_mux7_enum =
999 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1000 amic_mux_text);
1001
1002 static const struct soc_enum tx_amic_mux8_enum =
1003 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1004 amic_mux_text);
1005
1006 static const struct soc_enum sb_tx0_mux_enum =
1007 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1008 sb_tx0_mux_text);
1009
1010 static const struct soc_enum sb_tx1_mux_enum =
1011 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1012 sb_tx1_mux_text);
1013
1014 static const struct soc_enum sb_tx2_mux_enum =
1015 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1016 sb_tx2_mux_text);
1017
1018 static const struct soc_enum sb_tx3_mux_enum =
1019 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1020 sb_tx3_mux_text);
1021
1022 static const struct soc_enum sb_tx4_mux_enum =
1023 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1024 sb_tx4_mux_text);
1025
1026 static const struct soc_enum sb_tx5_mux_enum =
1027 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1028 sb_tx5_mux_text);
1029
1030 static const struct soc_enum sb_tx6_mux_enum =
1031 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1032 sb_tx6_mux_text);
1033
1034 static const struct soc_enum sb_tx7_mux_enum =
1035 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1036 sb_tx7_mux_text);
1037
1038 static const struct soc_enum sb_tx8_mux_enum =
1039 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1040 sb_tx8_mux_text);
1041
1042 static const struct snd_kcontrol_new rx_int0_2_mux =
1043 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1044
1045 static const struct snd_kcontrol_new rx_int1_2_mux =
1046 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1047
1048 static const struct snd_kcontrol_new rx_int2_2_mux =
1049 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1050
1051 static const struct snd_kcontrol_new rx_int3_2_mux =
1052 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1053
1054 static const struct snd_kcontrol_new rx_int4_2_mux =
1055 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1056
1057 static const struct snd_kcontrol_new rx_int5_2_mux =
1058 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1059
1060 static const struct snd_kcontrol_new rx_int6_2_mux =
1061 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1062
1063 static const struct snd_kcontrol_new rx_int7_2_mux =
1064 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1065
1066 static const struct snd_kcontrol_new rx_int8_2_mux =
1067 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1068
1069 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1070 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1071
1072 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1073 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1074
1075 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1076 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1077
1078 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1079 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1080
1081 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1082 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1083
1084 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1085 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1086
1087 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1088 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1089
1090 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1091 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1092
1093 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1094 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1095
1096 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1097 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1098
1099 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1100 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1101
1102 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1103 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1104
1105 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1106 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1107
1108 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1109 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1110
1111 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1112 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1113
1114 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1115 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1116
1117 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1118 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1119
1120 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1121 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1122
1123 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1124 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1125
1126 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1127 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1128
1129 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1130 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1131
1132 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1133 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1134
1135 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1136 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1137
1138 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1139 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1140
1141 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1142 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1143
1144 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1145 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1146
1147 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1148 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1149
1150 static const struct snd_kcontrol_new rx_int0_interp_mux =
1151 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1152
1153 static const struct snd_kcontrol_new rx_int1_interp_mux =
1154 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1155
1156 static const struct snd_kcontrol_new rx_int2_interp_mux =
1157 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1158
1159 static const struct snd_kcontrol_new rx_int3_interp_mux =
1160 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1161
1162 static const struct snd_kcontrol_new rx_int4_interp_mux =
1163 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1164
1165 static const struct snd_kcontrol_new rx_int5_interp_mux =
1166 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1167
1168 static const struct snd_kcontrol_new rx_int6_interp_mux =
1169 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1170
1171 static const struct snd_kcontrol_new rx_int7_interp_mux =
1172 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1173
1174 static const struct snd_kcontrol_new rx_int8_interp_mux =
1175 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1176
1177 static const struct snd_kcontrol_new tx_dmic_mux0 =
1178 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1179
1180 static const struct snd_kcontrol_new tx_dmic_mux1 =
1181 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1182
1183 static const struct snd_kcontrol_new tx_dmic_mux2 =
1184 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1185
1186 static const struct snd_kcontrol_new tx_dmic_mux3 =
1187 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1188
1189 static const struct snd_kcontrol_new tx_dmic_mux4 =
1190 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1191
1192 static const struct snd_kcontrol_new tx_dmic_mux5 =
1193 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1194
1195 static const struct snd_kcontrol_new tx_dmic_mux6 =
1196 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1197
1198 static const struct snd_kcontrol_new tx_dmic_mux7 =
1199 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1200
1201 static const struct snd_kcontrol_new tx_dmic_mux8 =
1202 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1203
1204 static const struct snd_kcontrol_new tx_amic_mux0 =
1205 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1206
1207 static const struct snd_kcontrol_new tx_amic_mux1 =
1208 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1209
1210 static const struct snd_kcontrol_new tx_amic_mux2 =
1211 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1212
1213 static const struct snd_kcontrol_new tx_amic_mux3 =
1214 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1215
1216 static const struct snd_kcontrol_new tx_amic_mux4 =
1217 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1218
1219 static const struct snd_kcontrol_new tx_amic_mux5 =
1220 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1221
1222 static const struct snd_kcontrol_new tx_amic_mux6 =
1223 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1224
1225 static const struct snd_kcontrol_new tx_amic_mux7 =
1226 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1227
1228 static const struct snd_kcontrol_new tx_amic_mux8 =
1229 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1230
1231 static const struct snd_kcontrol_new sb_tx0_mux =
1232 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1233
1234 static const struct snd_kcontrol_new sb_tx1_mux =
1235 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1236
1237 static const struct snd_kcontrol_new sb_tx2_mux =
1238 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1239
1240 static const struct snd_kcontrol_new sb_tx3_mux =
1241 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1242
1243 static const struct snd_kcontrol_new sb_tx4_mux =
1244 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1245
1246 static const struct snd_kcontrol_new sb_tx5_mux =
1247 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1248
1249 static const struct snd_kcontrol_new sb_tx6_mux =
1250 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1251
1252 static const struct snd_kcontrol_new sb_tx7_mux =
1253 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1254
1255 static const struct snd_kcontrol_new sb_tx8_mux =
1256 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1257
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1258 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1259 struct snd_ctl_elem_value *ucontrol)
1260 {
1261 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1262 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1263 u32 port_id = w->shift;
1264
1265 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
1266
1267 return 0;
1268 }
1269
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1270 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1271 struct snd_ctl_elem_value *ucontrol)
1272 {
1273 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1274 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1275 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1276 struct snd_soc_dapm_update *update = NULL;
1277 u32 port_id = w->shift;
1278
1279 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
1280 return 0;
1281
1282 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
1283
1284 /* Remove channel from any list it's in before adding it to a new one */
1285 list_del_init(&wcd->rx_chs[port_id].list);
1286
1287 switch (wcd->rx_port_value[port_id]) {
1288 case 0:
1289 /* Channel already removed from lists. Nothing to do here */
1290 break;
1291 case 1:
1292 list_add_tail(&wcd->rx_chs[port_id].list,
1293 &wcd->dai[AIF1_PB].slim_ch_list);
1294 break;
1295 case 2:
1296 list_add_tail(&wcd->rx_chs[port_id].list,
1297 &wcd->dai[AIF2_PB].slim_ch_list);
1298 break;
1299 case 3:
1300 list_add_tail(&wcd->rx_chs[port_id].list,
1301 &wcd->dai[AIF3_PB].slim_ch_list);
1302 break;
1303 case 4:
1304 list_add_tail(&wcd->rx_chs[port_id].list,
1305 &wcd->dai[AIF4_PB].slim_ch_list);
1306 break;
1307 default:
1308 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
1309 goto err;
1310 }
1311
1312 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
1313 e, update);
1314
1315 return 0;
1316 err:
1317 return -EINVAL;
1318 }
1319
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1320 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1321 struct snd_ctl_elem_value *ucontrol)
1322 {
1323
1324 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1325 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1326 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1327 struct soc_mixer_control *mixer =
1328 (struct soc_mixer_control *)kc->private_value;
1329 int dai_id = widget->shift;
1330 int port_id = mixer->shift;
1331
1332 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id;
1333
1334 return 0;
1335 }
1336
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1337 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1338 struct snd_ctl_elem_value *ucontrol)
1339 {
1340
1341 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1342 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1343 struct snd_soc_dapm_update *update = NULL;
1344 struct soc_mixer_control *mixer =
1345 (struct soc_mixer_control *)kc->private_value;
1346 int enable = ucontrol->value.integer.value[0];
1347 int dai_id = widget->shift;
1348 int port_id = mixer->shift;
1349
1350 switch (dai_id) {
1351 case AIF1_CAP:
1352 case AIF2_CAP:
1353 case AIF3_CAP:
1354 /* only add to the list if value not set */
1355 if (enable && wcd->tx_port_value[port_id] != dai_id) {
1356 wcd->tx_port_value[port_id] = dai_id;
1357 list_add_tail(&wcd->tx_chs[port_id].list,
1358 &wcd->dai[dai_id].slim_ch_list);
1359 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) {
1360 wcd->tx_port_value[port_id] = -1;
1361 list_del_init(&wcd->tx_chs[port_id].list);
1362 }
1363 break;
1364 default:
1365 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1366 return -EINVAL;
1367 }
1368
1369 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1370
1371 return 0;
1372 }
1373
1374 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1375 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1376 slim_rx_mux_get, slim_rx_mux_put),
1377 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1378 slim_rx_mux_get, slim_rx_mux_put),
1379 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1380 slim_rx_mux_get, slim_rx_mux_put),
1381 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1382 slim_rx_mux_get, slim_rx_mux_put),
1383 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1384 slim_rx_mux_get, slim_rx_mux_put),
1385 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1386 slim_rx_mux_get, slim_rx_mux_put),
1387 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1388 slim_rx_mux_get, slim_rx_mux_put),
1389 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1390 slim_rx_mux_get, slim_rx_mux_put),
1391 };
1392
1393 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1394 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1395 slim_tx_mixer_get, slim_tx_mixer_put),
1396 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1397 slim_tx_mixer_get, slim_tx_mixer_put),
1398 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1399 slim_tx_mixer_get, slim_tx_mixer_put),
1400 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1401 slim_tx_mixer_get, slim_tx_mixer_put),
1402 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1403 slim_tx_mixer_get, slim_tx_mixer_put),
1404 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1405 slim_tx_mixer_get, slim_tx_mixer_put),
1406 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1407 slim_tx_mixer_get, slim_tx_mixer_put),
1408 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1409 slim_tx_mixer_get, slim_tx_mixer_put),
1410 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1411 slim_tx_mixer_get, slim_tx_mixer_put),
1412 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1413 slim_tx_mixer_get, slim_tx_mixer_put),
1414 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1415 slim_tx_mixer_get, slim_tx_mixer_put),
1416 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1417 slim_tx_mixer_get, slim_tx_mixer_put),
1418 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1419 slim_tx_mixer_get, slim_tx_mixer_put),
1420 };
1421
1422 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1423 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1424 slim_tx_mixer_get, slim_tx_mixer_put),
1425 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1426 slim_tx_mixer_get, slim_tx_mixer_put),
1427 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1428 slim_tx_mixer_get, slim_tx_mixer_put),
1429 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1430 slim_tx_mixer_get, slim_tx_mixer_put),
1431 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1432 slim_tx_mixer_get, slim_tx_mixer_put),
1433 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1434 slim_tx_mixer_get, slim_tx_mixer_put),
1435 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1436 slim_tx_mixer_get, slim_tx_mixer_put),
1437 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1438 slim_tx_mixer_get, slim_tx_mixer_put),
1439 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1440 slim_tx_mixer_get, slim_tx_mixer_put),
1441 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1442 slim_tx_mixer_get, slim_tx_mixer_put),
1443 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1444 slim_tx_mixer_get, slim_tx_mixer_put),
1445 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1446 slim_tx_mixer_get, slim_tx_mixer_put),
1447 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1448 slim_tx_mixer_get, slim_tx_mixer_put),
1449 };
1450
1451 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1452 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1453 slim_tx_mixer_get, slim_tx_mixer_put),
1454 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1455 slim_tx_mixer_get, slim_tx_mixer_put),
1456 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1457 slim_tx_mixer_get, slim_tx_mixer_put),
1458 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1459 slim_tx_mixer_get, slim_tx_mixer_put),
1460 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1461 slim_tx_mixer_get, slim_tx_mixer_put),
1462 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1463 slim_tx_mixer_get, slim_tx_mixer_put),
1464 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1465 slim_tx_mixer_get, slim_tx_mixer_put),
1466 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1467 slim_tx_mixer_get, slim_tx_mixer_put),
1468 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1469 slim_tx_mixer_get, slim_tx_mixer_put),
1470 };
1471
wcd9335_put_dec_enum(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1472 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1473 struct snd_ctl_elem_value *ucontrol)
1474 {
1475 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1476 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1477 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1478 unsigned int val, reg, sel;
1479
1480 val = ucontrol->value.enumerated.item[0];
1481
1482 switch (e->reg) {
1483 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1484 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1485 break;
1486 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1487 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1488 break;
1489 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1490 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1491 break;
1492 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1493 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1494 break;
1495 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1496 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1497 break;
1498 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1499 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1500 break;
1501 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1502 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1503 break;
1504 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1505 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1506 break;
1507 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1508 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1509 break;
1510 default:
1511 return -EINVAL;
1512 }
1513
1514 /* AMIC: 0, DMIC: 1 */
1515 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1516 snd_soc_component_update_bits(component, reg,
1517 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1518 sel);
1519
1520 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1521 }
1522
wcd9335_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1523 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1524 struct snd_ctl_elem_value *ucontrol)
1525 {
1526 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1527 struct snd_soc_component *component;
1528 int reg, val;
1529
1530 component = snd_soc_dapm_kcontrol_component(kc);
1531 val = ucontrol->value.enumerated.item[0];
1532
1533 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1534 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1535 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1536 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1537 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1538 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1539 else
1540 return -EINVAL;
1541
1542 /* Set Look Ahead Delay */
1543 snd_soc_component_update_bits(component, reg,
1544 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1545 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1546 /* Set DEM INP Select */
1547 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1548 }
1549
1550 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1551 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1552 snd_soc_dapm_get_enum_double,
1553 wcd9335_int_dem_inp_mux_put);
1554
1555 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1556 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1557 snd_soc_dapm_get_enum_double,
1558 wcd9335_int_dem_inp_mux_put);
1559
1560 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1561 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1562 snd_soc_dapm_get_enum_double,
1563 wcd9335_int_dem_inp_mux_put);
1564
1565 static const struct snd_kcontrol_new tx_adc_mux0 =
1566 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1567 snd_soc_dapm_get_enum_double,
1568 wcd9335_put_dec_enum);
1569
1570 static const struct snd_kcontrol_new tx_adc_mux1 =
1571 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1572 snd_soc_dapm_get_enum_double,
1573 wcd9335_put_dec_enum);
1574
1575 static const struct snd_kcontrol_new tx_adc_mux2 =
1576 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1577 snd_soc_dapm_get_enum_double,
1578 wcd9335_put_dec_enum);
1579
1580 static const struct snd_kcontrol_new tx_adc_mux3 =
1581 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1582 snd_soc_dapm_get_enum_double,
1583 wcd9335_put_dec_enum);
1584
1585 static const struct snd_kcontrol_new tx_adc_mux4 =
1586 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1587 snd_soc_dapm_get_enum_double,
1588 wcd9335_put_dec_enum);
1589
1590 static const struct snd_kcontrol_new tx_adc_mux5 =
1591 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1592 snd_soc_dapm_get_enum_double,
1593 wcd9335_put_dec_enum);
1594
1595 static const struct snd_kcontrol_new tx_adc_mux6 =
1596 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1597 snd_soc_dapm_get_enum_double,
1598 wcd9335_put_dec_enum);
1599
1600 static const struct snd_kcontrol_new tx_adc_mux7 =
1601 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1602 snd_soc_dapm_get_enum_double,
1603 wcd9335_put_dec_enum);
1604
1605 static const struct snd_kcontrol_new tx_adc_mux8 =
1606 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1607 snd_soc_dapm_get_enum_double,
1608 wcd9335_put_dec_enum);
1609
wcd9335_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1610 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1611 int rate_val,
1612 u32 rate)
1613 {
1614 struct snd_soc_component *component = dai->component;
1615 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1616 struct wcd9335_slim_ch *ch;
1617 int val, j;
1618
1619 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1620 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1621 val = snd_soc_component_read(component,
1622 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1623 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1624
1625 if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1626 snd_soc_component_update_bits(component,
1627 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1628 WCD9335_CDC_MIX_PCM_RATE_MASK,
1629 rate_val);
1630 }
1631 }
1632
1633 return 0;
1634 }
1635
wcd9335_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1636 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1637 u8 rate_val,
1638 u32 rate)
1639 {
1640 struct snd_soc_component *comp = dai->component;
1641 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1642 struct wcd9335_slim_ch *ch;
1643 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1644 int inp, j;
1645
1646 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1647 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1648 /*
1649 * Loop through all interpolator MUX inputs and find out
1650 * to which interpolator input, the slim rx port
1651 * is connected
1652 */
1653 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1654 cfg0 = snd_soc_component_read(comp,
1655 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1656 cfg1 = snd_soc_component_read(comp,
1657 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1658
1659 inp0_sel = cfg0 &
1660 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1661 inp1_sel = (cfg0 >> 4) &
1662 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1663 inp2_sel = (cfg1 >> 4) &
1664 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1665
1666 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1667 (inp2_sel == inp)) {
1668 /* rate is in Hz */
1669 if ((j == 0) && (rate == 44100))
1670 dev_info(wcd->dev,
1671 "Cannot set 44.1KHz on INT0\n");
1672 else
1673 snd_soc_component_update_bits(comp,
1674 WCD9335_CDC_RX_PATH_CTL(j),
1675 WCD9335_CDC_MIX_PCM_RATE_MASK,
1676 rate_val);
1677 }
1678 }
1679 }
1680
1681 return 0;
1682 }
1683
wcd9335_set_interpolator_rate(struct snd_soc_dai * dai,u32 rate)1684 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1685 {
1686 int i;
1687
1688 /* set mixing path rate */
1689 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1690 if (rate == int_mix_rate_val[i].rate) {
1691 wcd9335_set_mix_interpolator_rate(dai,
1692 int_mix_rate_val[i].rate_val, rate);
1693 break;
1694 }
1695 }
1696
1697 /* set primary path sample rate */
1698 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1699 if (rate == int_prim_rate_val[i].rate) {
1700 wcd9335_set_prim_interpolator_rate(dai,
1701 int_prim_rate_val[i].rate_val, rate);
1702 break;
1703 }
1704 }
1705
1706 return 0;
1707 }
1708
wcd9335_slim_set_hw_params(struct wcd9335_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1709 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1710 struct wcd_slim_codec_dai_data *dai_data,
1711 int direction)
1712 {
1713 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1714 struct slim_stream_config *cfg = &dai_data->sconfig;
1715 struct wcd9335_slim_ch *ch;
1716 u16 payload = 0;
1717 int ret, i;
1718
1719 cfg->ch_count = 0;
1720 cfg->direction = direction;
1721 cfg->port_mask = 0;
1722
1723 /* Configure slave interface device */
1724 list_for_each_entry(ch, slim_ch_list, list) {
1725 cfg->ch_count++;
1726 payload |= 1 << ch->shift;
1727 cfg->port_mask |= BIT(ch->port);
1728 }
1729
1730 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1731 if (!cfg->chs)
1732 return -ENOMEM;
1733
1734 i = 0;
1735 list_for_each_entry(ch, slim_ch_list, list) {
1736 cfg->chs[i++] = ch->ch_num;
1737 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1738 /* write to interface device */
1739 ret = regmap_write(wcd->if_regmap,
1740 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1741 payload);
1742
1743 if (ret < 0)
1744 goto err;
1745
1746 /* configure the slave port for water mark and enable*/
1747 ret = regmap_write(wcd->if_regmap,
1748 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1749 WCD9335_SLIM_WATER_MARK_VAL);
1750 if (ret < 0)
1751 goto err;
1752 } else {
1753 ret = regmap_write(wcd->if_regmap,
1754 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1755 payload & 0x00FF);
1756 if (ret < 0)
1757 goto err;
1758
1759 /* ports 8,9 */
1760 ret = regmap_write(wcd->if_regmap,
1761 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1762 (payload & 0xFF00)>>8);
1763 if (ret < 0)
1764 goto err;
1765
1766 /* configure the slave port for water mark and enable*/
1767 ret = regmap_write(wcd->if_regmap,
1768 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1769 WCD9335_SLIM_WATER_MARK_VAL);
1770
1771 if (ret < 0)
1772 goto err;
1773 }
1774 }
1775
1776 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1777
1778 return 0;
1779
1780 err:
1781 dev_err(wcd->dev, "Error Setting slim hw params\n");
1782 kfree(cfg->chs);
1783 cfg->chs = NULL;
1784
1785 return ret;
1786 }
1787
wcd9335_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1788 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1789 u8 rate_val, u32 rate)
1790 {
1791 struct snd_soc_component *comp = dai->component;
1792 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1793 u8 shift = 0, shift_val = 0, tx_mux_sel;
1794 struct wcd9335_slim_ch *ch;
1795 int tx_port, tx_port_reg;
1796 int decimator = -1;
1797
1798 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1799 tx_port = ch->port;
1800 if ((tx_port == 12) || (tx_port >= 14)) {
1801 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1802 tx_port, dai->id);
1803 return -EINVAL;
1804 }
1805 /* Find the SB TX MUX input - which decimator is connected */
1806 if (tx_port < 4) {
1807 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1808 shift = (tx_port << 1);
1809 shift_val = 0x03;
1810 } else if (tx_port < 8) {
1811 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1812 shift = ((tx_port - 4) << 1);
1813 shift_val = 0x03;
1814 } else if (tx_port < 11) {
1815 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1816 shift = ((tx_port - 8) << 1);
1817 shift_val = 0x03;
1818 } else if (tx_port == 11) {
1819 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1820 shift = 0;
1821 shift_val = 0x0F;
1822 } else /* (tx_port == 13) */ {
1823 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1824 shift = 4;
1825 shift_val = 0x03;
1826 }
1827
1828 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1829 (shift_val << shift);
1830
1831 tx_mux_sel = tx_mux_sel >> shift;
1832 if (tx_port <= 8) {
1833 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1834 decimator = tx_port;
1835 } else if (tx_port <= 10) {
1836 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1837 decimator = ((tx_port == 9) ? 7 : 6);
1838 } else if (tx_port == 11) {
1839 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1840 decimator = tx_mux_sel - 1;
1841 } else if (tx_port == 13) {
1842 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1843 decimator = 5;
1844 }
1845
1846 if (decimator >= 0) {
1847 snd_soc_component_update_bits(comp,
1848 WCD9335_CDC_TX_PATH_CTL(decimator),
1849 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1850 rate_val);
1851 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1852 /* Check if the TX Mux input is RX MIX TXn */
1853 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1854 tx_port, tx_port);
1855 } else {
1856 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1857 decimator);
1858 return -EINVAL;
1859 }
1860 }
1861
1862 return 0;
1863 }
1864
wcd9335_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1865 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1866 struct snd_pcm_hw_params *params,
1867 struct snd_soc_dai *dai)
1868 {
1869 struct wcd9335_codec *wcd;
1870 int ret, tx_fs_rate = 0;
1871
1872 wcd = snd_soc_component_get_drvdata(dai->component);
1873
1874 switch (substream->stream) {
1875 case SNDRV_PCM_STREAM_PLAYBACK:
1876 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1877 if (ret) {
1878 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1879 params_rate(params));
1880 return ret;
1881 }
1882 switch (params_width(params)) {
1883 case 16 ... 24:
1884 wcd->dai[dai->id].sconfig.bps = params_width(params);
1885 break;
1886 default:
1887 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1888 __func__, params_width(params));
1889 return -EINVAL;
1890 }
1891 break;
1892
1893 case SNDRV_PCM_STREAM_CAPTURE:
1894 switch (params_rate(params)) {
1895 case 8000:
1896 tx_fs_rate = 0;
1897 break;
1898 case 16000:
1899 tx_fs_rate = 1;
1900 break;
1901 case 32000:
1902 tx_fs_rate = 3;
1903 break;
1904 case 48000:
1905 tx_fs_rate = 4;
1906 break;
1907 case 96000:
1908 tx_fs_rate = 5;
1909 break;
1910 case 192000:
1911 tx_fs_rate = 6;
1912 break;
1913 case 384000:
1914 tx_fs_rate = 7;
1915 break;
1916 default:
1917 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1918 __func__, params_rate(params));
1919 return -EINVAL;
1920
1921 }
1922
1923 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1924 params_rate(params));
1925 if (ret < 0) {
1926 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1927 return ret;
1928 }
1929 switch (params_width(params)) {
1930 case 16 ... 32:
1931 wcd->dai[dai->id].sconfig.bps = params_width(params);
1932 break;
1933 default:
1934 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1935 __func__, params_width(params));
1936 return -EINVAL;
1937 }
1938 break;
1939 default:
1940 dev_err(wcd->dev, "Invalid stream type %d\n",
1941 substream->stream);
1942 return -EINVAL;
1943 }
1944
1945 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1946 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1947
1948 return 0;
1949 }
1950
wcd9335_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1951 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1952 struct snd_soc_dai *dai)
1953 {
1954 struct wcd_slim_codec_dai_data *dai_data;
1955 struct wcd9335_codec *wcd;
1956 struct slim_stream_config *cfg;
1957
1958 wcd = snd_soc_component_get_drvdata(dai->component);
1959
1960 dai_data = &wcd->dai[dai->id];
1961
1962 switch (cmd) {
1963 case SNDRV_PCM_TRIGGER_START:
1964 case SNDRV_PCM_TRIGGER_RESUME:
1965 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1966 cfg = &dai_data->sconfig;
1967 slim_stream_prepare(dai_data->sruntime, cfg);
1968 slim_stream_enable(dai_data->sruntime);
1969 break;
1970 case SNDRV_PCM_TRIGGER_STOP:
1971 case SNDRV_PCM_TRIGGER_SUSPEND:
1972 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1973 slim_stream_disable(dai_data->sruntime);
1974 slim_stream_unprepare(dai_data->sruntime);
1975 break;
1976 default:
1977 break;
1978 }
1979
1980 return 0;
1981 }
1982
wcd9335_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,const unsigned int * tx_slot,unsigned int rx_num,const unsigned int * rx_slot)1983 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1984 unsigned int tx_num,
1985 const unsigned int *tx_slot,
1986 unsigned int rx_num,
1987 const unsigned int *rx_slot)
1988 {
1989 struct wcd9335_codec *wcd;
1990 int i;
1991
1992 wcd = snd_soc_component_get_drvdata(dai->component);
1993
1994 if (!tx_slot || !rx_slot) {
1995 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1996 tx_slot, rx_slot);
1997 return -EINVAL;
1998 }
1999
2000 wcd->num_rx_port = rx_num;
2001 for (i = 0; i < rx_num; i++) {
2002 wcd->rx_chs[i].ch_num = rx_slot[i];
2003 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2004 }
2005
2006 wcd->num_tx_port = tx_num;
2007 for (i = 0; i < tx_num; i++) {
2008 wcd->tx_chs[i].ch_num = tx_slot[i];
2009 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2010 }
2011
2012 return 0;
2013 }
2014
wcd9335_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)2015 static int wcd9335_get_channel_map(const struct snd_soc_dai *dai,
2016 unsigned int *tx_num, unsigned int *tx_slot,
2017 unsigned int *rx_num, unsigned int *rx_slot)
2018 {
2019 struct wcd9335_slim_ch *ch;
2020 struct wcd9335_codec *wcd;
2021 int i = 0;
2022
2023 wcd = snd_soc_component_get_drvdata(dai->component);
2024
2025 switch (dai->id) {
2026 case AIF1_PB:
2027 case AIF2_PB:
2028 case AIF3_PB:
2029 case AIF4_PB:
2030 if (!rx_slot || !rx_num) {
2031 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2032 rx_slot, rx_num);
2033 return -EINVAL;
2034 }
2035
2036 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2037 rx_slot[i++] = ch->ch_num;
2038
2039 *rx_num = i;
2040 break;
2041 case AIF1_CAP:
2042 case AIF2_CAP:
2043 case AIF3_CAP:
2044 if (!tx_slot || !tx_num) {
2045 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2046 tx_slot, tx_num);
2047 return -EINVAL;
2048 }
2049 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2050 tx_slot[i++] = ch->ch_num;
2051
2052 *tx_num = i;
2053 break;
2054 default:
2055 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2056 break;
2057 }
2058
2059 return 0;
2060 }
2061
2062 static const struct snd_soc_dai_ops wcd9335_dai_ops = {
2063 .hw_params = wcd9335_hw_params,
2064 .trigger = wcd9335_trigger,
2065 .set_channel_map = wcd9335_set_channel_map,
2066 .get_channel_map = wcd9335_get_channel_map,
2067 };
2068
2069 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2070 [0] = {
2071 .name = "wcd9335_rx1",
2072 .id = AIF1_PB,
2073 .playback = {
2074 .stream_name = "AIF1 Playback",
2075 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2076 SNDRV_PCM_RATE_384000,
2077 .formats = WCD9335_FORMATS_S16_S24_LE,
2078 .rate_max = 384000,
2079 .rate_min = 8000,
2080 .channels_min = 1,
2081 .channels_max = 2,
2082 },
2083 .ops = &wcd9335_dai_ops,
2084 },
2085 [1] = {
2086 .name = "wcd9335_tx1",
2087 .id = AIF1_CAP,
2088 .capture = {
2089 .stream_name = "AIF1 Capture",
2090 .rates = WCD9335_RATES_MASK,
2091 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2092 .rate_min = 8000,
2093 .rate_max = 192000,
2094 .channels_min = 1,
2095 .channels_max = 4,
2096 },
2097 .ops = &wcd9335_dai_ops,
2098 },
2099 [2] = {
2100 .name = "wcd9335_rx2",
2101 .id = AIF2_PB,
2102 .playback = {
2103 .stream_name = "AIF2 Playback",
2104 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2105 SNDRV_PCM_RATE_384000,
2106 .formats = WCD9335_FORMATS_S16_S24_LE,
2107 .rate_min = 8000,
2108 .rate_max = 384000,
2109 .channels_min = 1,
2110 .channels_max = 2,
2111 },
2112 .ops = &wcd9335_dai_ops,
2113 },
2114 [3] = {
2115 .name = "wcd9335_tx2",
2116 .id = AIF2_CAP,
2117 .capture = {
2118 .stream_name = "AIF2 Capture",
2119 .rates = WCD9335_RATES_MASK,
2120 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2121 .rate_min = 8000,
2122 .rate_max = 192000,
2123 .channels_min = 1,
2124 .channels_max = 4,
2125 },
2126 .ops = &wcd9335_dai_ops,
2127 },
2128 [4] = {
2129 .name = "wcd9335_rx3",
2130 .id = AIF3_PB,
2131 .playback = {
2132 .stream_name = "AIF3 Playback",
2133 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2134 SNDRV_PCM_RATE_384000,
2135 .formats = WCD9335_FORMATS_S16_S24_LE,
2136 .rate_min = 8000,
2137 .rate_max = 384000,
2138 .channels_min = 1,
2139 .channels_max = 2,
2140 },
2141 .ops = &wcd9335_dai_ops,
2142 },
2143 [5] = {
2144 .name = "wcd9335_tx3",
2145 .id = AIF3_CAP,
2146 .capture = {
2147 .stream_name = "AIF3 Capture",
2148 .rates = WCD9335_RATES_MASK,
2149 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2150 .rate_min = 8000,
2151 .rate_max = 192000,
2152 .channels_min = 1,
2153 .channels_max = 4,
2154 },
2155 .ops = &wcd9335_dai_ops,
2156 },
2157 [6] = {
2158 .name = "wcd9335_rx4",
2159 .id = AIF4_PB,
2160 .playback = {
2161 .stream_name = "AIF4 Playback",
2162 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2163 SNDRV_PCM_RATE_384000,
2164 .formats = WCD9335_FORMATS_S16_S24_LE,
2165 .rate_min = 8000,
2166 .rate_max = 384000,
2167 .channels_min = 1,
2168 .channels_max = 2,
2169 },
2170 .ops = &wcd9335_dai_ops,
2171 },
2172 };
2173
wcd9335_get_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2174 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2175 struct snd_ctl_elem_value *ucontrol)
2176 {
2177
2178 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2179 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2180 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2181
2182 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2183 return 0;
2184 }
2185
wcd9335_set_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2186 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2187 struct snd_ctl_elem_value *ucontrol)
2188 {
2189 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2190 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2191 int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2192 int value = ucontrol->value.integer.value[0];
2193 int sel;
2194
2195 wcd->comp_enabled[comp] = value;
2196 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2197 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2198
2199 /* Any specific register configuration for compander */
2200 switch (comp) {
2201 case COMPANDER_1:
2202 /* Set Gain Source Select based on compander enable/disable */
2203 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2204 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2205 break;
2206 case COMPANDER_2:
2207 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2208 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2209 break;
2210 case COMPANDER_5:
2211 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2212 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2213 break;
2214 case COMPANDER_6:
2215 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2216 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2217 break;
2218 default:
2219 break;
2220 }
2221
2222 return 0;
2223 }
2224
wcd9335_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2225 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2226 struct snd_ctl_elem_value *ucontrol)
2227 {
2228 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2229 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2230
2231 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2232
2233 return 0;
2234 }
2235
wcd9335_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2236 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2237 struct snd_ctl_elem_value *ucontrol)
2238 {
2239 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2240 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2241 u32 mode_val;
2242
2243 mode_val = ucontrol->value.enumerated.item[0];
2244
2245 if (mode_val == 0) {
2246 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2247 mode_val = CLS_H_HIFI;
2248 }
2249 wcd->hph_mode = mode_val;
2250
2251 return 0;
2252 }
2253
2254 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2255 /* -84dB min - 40dB max */
2256 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2257 -84, 40, digital_gain),
2258 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2259 -84, 40, digital_gain),
2260 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2261 -84, 40, digital_gain),
2262 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2263 -84, 40, digital_gain),
2264 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2265 -84, 40, digital_gain),
2266 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2267 -84, 40, digital_gain),
2268 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2269 -84, 40, digital_gain),
2270 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2271 -84, 40, digital_gain),
2272 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2273 -84, 40, digital_gain),
2274 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2275 -84, 40, digital_gain),
2276 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2277 -84, 40, digital_gain),
2278 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2279 -84, 40, digital_gain),
2280 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2281 -84, 40, digital_gain),
2282 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2283 -84, 40, digital_gain),
2284 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2285 -84, 40, digital_gain),
2286 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2287 -84, 40, digital_gain),
2288 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2289 -84, 40, digital_gain),
2290 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2291 -84, 40, digital_gain),
2292 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2293 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2294 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2295 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2296 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2297 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2298 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2299 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2300 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2301 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2302 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2303 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2304 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2305 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2306 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2307 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2308 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2309 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2310 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2311 wcd9335_get_compander, wcd9335_set_compander),
2312 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2313 wcd9335_get_compander, wcd9335_set_compander),
2314 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2315 wcd9335_get_compander, wcd9335_set_compander),
2316 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2317 wcd9335_get_compander, wcd9335_set_compander),
2318 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2319 wcd9335_get_compander, wcd9335_set_compander),
2320 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2321 wcd9335_get_compander, wcd9335_set_compander),
2322 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2323 wcd9335_get_compander, wcd9335_set_compander),
2324 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2325 wcd9335_get_compander, wcd9335_set_compander),
2326 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2327 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2328
2329 /* Gain Controls */
2330 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2331 ear_pa_gain),
2332 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2333 line_gain),
2334 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2335 line_gain),
2336 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2337 3, 16, 1, line_gain),
2338 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2339 3, 16, 1, line_gain),
2340 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2341 line_gain),
2342 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2343 line_gain),
2344
2345 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2346 analog_gain),
2347 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2348 analog_gain),
2349 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2350 analog_gain),
2351 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2352 analog_gain),
2353 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2354 analog_gain),
2355 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2356 analog_gain),
2357
2358 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2359 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2360 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2361 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2362 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2363 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2364 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2365 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2366 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2367 };
2368
2369 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2370 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2371 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2372 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2373 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2374 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2375 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2376 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2377 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2378
2379 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2380 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2381 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2382 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2383 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2384 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2385 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2386 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2387
2388 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2389 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2390 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2391 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2392 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2393 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2394 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2395 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2396
2397 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2398 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2399 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2400 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2401 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2402 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2403 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2404 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2405
2406 {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2407 {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2408 {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2409 {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2410 {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2411 {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2412 {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2413 {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2414
2415 WCD9335_INTERPOLATOR_PATH(0),
2416 WCD9335_INTERPOLATOR_PATH(1),
2417 WCD9335_INTERPOLATOR_PATH(2),
2418 WCD9335_INTERPOLATOR_PATH(3),
2419 WCD9335_INTERPOLATOR_PATH(4),
2420 WCD9335_INTERPOLATOR_PATH(5),
2421 WCD9335_INTERPOLATOR_PATH(6),
2422 WCD9335_INTERPOLATOR_PATH(7),
2423 WCD9335_INTERPOLATOR_PATH(8),
2424
2425 /* EAR PA */
2426 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2427 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2428 {"RX INT0 DAC", NULL, "RX_BIAS"},
2429 {"EAR PA", NULL, "RX INT0 DAC"},
2430 {"EAR", NULL, "EAR PA"},
2431
2432 /* HPHL */
2433 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2434 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2435 {"RX INT1 DAC", NULL, "RX_BIAS"},
2436 {"HPHL PA", NULL, "RX INT1 DAC"},
2437 {"HPHL", NULL, "HPHL PA"},
2438
2439 /* HPHR */
2440 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2441 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2442 {"RX INT2 DAC", NULL, "RX_BIAS"},
2443 {"HPHR PA", NULL, "RX INT2 DAC"},
2444 {"HPHR", NULL, "HPHR PA"},
2445
2446 /* LINEOUT1 */
2447 {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2448 {"RX INT3 DAC", NULL, "RX_BIAS"},
2449 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2450 {"LINEOUT1", NULL, "LINEOUT1 PA"},
2451
2452 /* LINEOUT2 */
2453 {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2454 {"RX INT4 DAC", NULL, "RX_BIAS"},
2455 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2456 {"LINEOUT2", NULL, "LINEOUT2 PA"},
2457
2458 /* LINEOUT3 */
2459 {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2460 {"RX INT5 DAC", NULL, "RX_BIAS"},
2461 {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2462 {"LINEOUT3", NULL, "LINEOUT3 PA"},
2463
2464 /* LINEOUT4 */
2465 {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2466 {"RX INT6 DAC", NULL, "RX_BIAS"},
2467 {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2468 {"LINEOUT4", NULL, "LINEOUT4 PA"},
2469
2470 /* SLIMBUS Connections */
2471 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2472 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2473 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2474
2475 /* ADC Mux */
2476 WCD9335_ADC_MUX_PATH(0),
2477 WCD9335_ADC_MUX_PATH(1),
2478 WCD9335_ADC_MUX_PATH(2),
2479 WCD9335_ADC_MUX_PATH(3),
2480 WCD9335_ADC_MUX_PATH(4),
2481 WCD9335_ADC_MUX_PATH(5),
2482 WCD9335_ADC_MUX_PATH(6),
2483 WCD9335_ADC_MUX_PATH(7),
2484 WCD9335_ADC_MUX_PATH(8),
2485
2486 /* ADC Connections */
2487 {"ADC1", NULL, "AMIC1"},
2488 {"ADC2", NULL, "AMIC2"},
2489 {"ADC3", NULL, "AMIC3"},
2490 {"ADC4", NULL, "AMIC4"},
2491 {"ADC5", NULL, "AMIC5"},
2492 {"ADC6", NULL, "AMIC6"},
2493 };
2494
wcd9335_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2495 static int wcd9335_micbias_control(struct snd_soc_component *component,
2496 int micb_num, int req, bool is_dapm)
2497 {
2498 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2499 int micb_index = micb_num - 1;
2500 u16 micb_reg;
2501
2502 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2503 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2504 micb_index);
2505 return -EINVAL;
2506 }
2507
2508 switch (micb_num) {
2509 case MIC_BIAS_1:
2510 micb_reg = WCD9335_ANA_MICB1;
2511 break;
2512 case MIC_BIAS_2:
2513 micb_reg = WCD9335_ANA_MICB2;
2514 break;
2515 case MIC_BIAS_3:
2516 micb_reg = WCD9335_ANA_MICB3;
2517 break;
2518 case MIC_BIAS_4:
2519 micb_reg = WCD9335_ANA_MICB4;
2520 break;
2521 default:
2522 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2523 __func__, micb_num);
2524 return -EINVAL;
2525 }
2526
2527 switch (req) {
2528 case MICB_PULLUP_ENABLE:
2529 wcd->pullup_ref[micb_index]++;
2530 if ((wcd->pullup_ref[micb_index] == 1) &&
2531 (wcd->micb_ref[micb_index] == 0))
2532 snd_soc_component_update_bits(component, micb_reg,
2533 0xC0, 0x80);
2534 break;
2535 case MICB_PULLUP_DISABLE:
2536 wcd->pullup_ref[micb_index]--;
2537 if ((wcd->pullup_ref[micb_index] == 0) &&
2538 (wcd->micb_ref[micb_index] == 0))
2539 snd_soc_component_update_bits(component, micb_reg,
2540 0xC0, 0x00);
2541 break;
2542 case MICB_ENABLE:
2543 wcd->micb_ref[micb_index]++;
2544 if (wcd->micb_ref[micb_index] == 1)
2545 snd_soc_component_update_bits(component, micb_reg,
2546 0xC0, 0x40);
2547 break;
2548 case MICB_DISABLE:
2549 wcd->micb_ref[micb_index]--;
2550 if ((wcd->micb_ref[micb_index] == 0) &&
2551 (wcd->pullup_ref[micb_index] > 0))
2552 snd_soc_component_update_bits(component, micb_reg,
2553 0xC0, 0x80);
2554 else if ((wcd->micb_ref[micb_index] == 0) &&
2555 (wcd->pullup_ref[micb_index] == 0)) {
2556 snd_soc_component_update_bits(component, micb_reg,
2557 0xC0, 0x00);
2558 }
2559 break;
2560 }
2561
2562 return 0;
2563 }
2564
__wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,int event)2565 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2566 int event)
2567 {
2568 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2569 int micb_num;
2570
2571 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2572 micb_num = MIC_BIAS_1;
2573 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2574 micb_num = MIC_BIAS_2;
2575 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2576 micb_num = MIC_BIAS_3;
2577 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2578 micb_num = MIC_BIAS_4;
2579 else
2580 return -EINVAL;
2581
2582 switch (event) {
2583 case SND_SOC_DAPM_PRE_PMU:
2584 /*
2585 * MIC BIAS can also be requested by MBHC,
2586 * so use ref count to handle micbias pullup
2587 * and enable requests
2588 */
2589 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2590 break;
2591 case SND_SOC_DAPM_POST_PMU:
2592 /* wait for cnp time */
2593 usleep_range(1000, 1100);
2594 break;
2595 case SND_SOC_DAPM_POST_PMD:
2596 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2597 break;
2598 }
2599
2600 return 0;
2601 }
2602
wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2603 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2604 struct snd_kcontrol *kc, int event)
2605 {
2606 return __wcd9335_codec_enable_micbias(w, event);
2607 }
2608
wcd9335_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)2609 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2610 u16 amic_reg, bool set)
2611 {
2612 u8 mask = 0x20;
2613 u8 val;
2614
2615 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2616 amic_reg == WCD9335_ANA_AMIC5)
2617 mask = 0x40;
2618
2619 val = set ? mask : 0x00;
2620
2621 switch (amic_reg) {
2622 case WCD9335_ANA_AMIC1:
2623 case WCD9335_ANA_AMIC2:
2624 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2625 val);
2626 break;
2627 case WCD9335_ANA_AMIC3:
2628 case WCD9335_ANA_AMIC4:
2629 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2630 val);
2631 break;
2632 case WCD9335_ANA_AMIC5:
2633 case WCD9335_ANA_AMIC6:
2634 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2635 val);
2636 break;
2637 default:
2638 dev_err(comp->dev, "%s: invalid amic: %d\n",
2639 __func__, amic_reg);
2640 break;
2641 }
2642 }
2643
wcd9335_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2644 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2645 struct snd_kcontrol *kc, int event)
2646 {
2647 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2648
2649 switch (event) {
2650 case SND_SOC_DAPM_PRE_PMU:
2651 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2652 break;
2653 default:
2654 break;
2655 }
2656
2657 return 0;
2658 }
2659
wcd9335_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)2660 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2661 int adc_mux_n)
2662 {
2663 int mux_sel, reg, mreg;
2664
2665 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2666 adc_mux_n == WCD9335_INVALID_ADC_MUX)
2667 return 0;
2668
2669 /* Check whether adc mux input is AMIC or DMIC */
2670 if (adc_mux_n < 4) {
2671 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2672 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2673 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2674 } else {
2675 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2676 mreg = reg;
2677 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2678 }
2679
2680 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2681 return 0;
2682
2683 return snd_soc_component_read(comp, mreg) & 0x07;
2684 }
2685
wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)2686 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2687 int amic)
2688 {
2689 u16 pwr_level_reg = 0;
2690
2691 switch (amic) {
2692 case 1:
2693 case 2:
2694 pwr_level_reg = WCD9335_ANA_AMIC1;
2695 break;
2696
2697 case 3:
2698 case 4:
2699 pwr_level_reg = WCD9335_ANA_AMIC3;
2700 break;
2701
2702 case 5:
2703 case 6:
2704 pwr_level_reg = WCD9335_ANA_AMIC5;
2705 break;
2706 default:
2707 dev_err(comp->dev, "invalid amic: %d\n", amic);
2708 break;
2709 }
2710
2711 return pwr_level_reg;
2712 }
2713
wcd9335_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2714 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2715 struct snd_kcontrol *kc, int event)
2716 {
2717 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2718 unsigned int decimator;
2719 char *dec_adc_mux_name = NULL;
2720 char *widget_name;
2721 int ret = 0, amic_n;
2722 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2723 u16 tx_gain_ctl_reg;
2724 char *dec;
2725 u8 hpf_coff_freq;
2726
2727 char *wname __free(kfree) = kmemdup_nul(w->name, 15, GFP_KERNEL);
2728 if (!wname)
2729 return -ENOMEM;
2730
2731 widget_name = wname;
2732 dec_adc_mux_name = strsep(&widget_name, " ");
2733 if (!dec_adc_mux_name) {
2734 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2735 __func__, w->name);
2736 return -EINVAL;
2737 }
2738 dec_adc_mux_name = widget_name;
2739
2740 dec = strpbrk(dec_adc_mux_name, "012345678");
2741 if (!dec) {
2742 dev_err(comp->dev, "%s: decimator index not found\n",
2743 __func__);
2744 return -EINVAL;
2745 }
2746
2747 ret = kstrtouint(dec, 10, &decimator);
2748 if (ret < 0) {
2749 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2750 __func__, wname);
2751 return -EINVAL;
2752 }
2753
2754 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2755 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2756 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2757 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2758
2759 switch (event) {
2760 case SND_SOC_DAPM_PRE_PMU:
2761 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2762 if (amic_n)
2763 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2764 amic_n);
2765
2766 if (pwr_level_reg) {
2767 switch ((snd_soc_component_read(comp, pwr_level_reg) &
2768 WCD9335_AMIC_PWR_LVL_MASK) >>
2769 WCD9335_AMIC_PWR_LVL_SHIFT) {
2770 case WCD9335_AMIC_PWR_LEVEL_LP:
2771 snd_soc_component_update_bits(comp, dec_cfg_reg,
2772 WCD9335_DEC_PWR_LVL_MASK,
2773 WCD9335_DEC_PWR_LVL_LP);
2774 break;
2775
2776 case WCD9335_AMIC_PWR_LEVEL_HP:
2777 snd_soc_component_update_bits(comp, dec_cfg_reg,
2778 WCD9335_DEC_PWR_LVL_MASK,
2779 WCD9335_DEC_PWR_LVL_HP);
2780 break;
2781 case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2782 default:
2783 snd_soc_component_update_bits(comp, dec_cfg_reg,
2784 WCD9335_DEC_PWR_LVL_MASK,
2785 WCD9335_DEC_PWR_LVL_DF);
2786 break;
2787 }
2788 }
2789 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2790 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2791
2792 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2793 snd_soc_component_update_bits(comp, dec_cfg_reg,
2794 TX_HPF_CUT_OFF_FREQ_MASK,
2795 CF_MIN_3DB_150HZ << 5);
2796 /* Enable TX PGA Mute */
2797 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2798 0x10, 0x10);
2799 /* Enable APC */
2800 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2801 break;
2802 case SND_SOC_DAPM_POST_PMU:
2803 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2804
2805 if (decimator == 0) {
2806 snd_soc_component_write(comp,
2807 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2808 snd_soc_component_write(comp,
2809 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2810 snd_soc_component_write(comp,
2811 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2812 snd_soc_component_write(comp,
2813 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2814 }
2815
2816 snd_soc_component_update_bits(comp, hpf_gate_reg,
2817 0x01, 0x01);
2818 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2819 0x10, 0x00);
2820 snd_soc_component_write(comp, tx_gain_ctl_reg,
2821 snd_soc_component_read(comp, tx_gain_ctl_reg));
2822 break;
2823 case SND_SOC_DAPM_PRE_PMD:
2824 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2825 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2826 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2827 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2828 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2829 snd_soc_component_update_bits(comp, dec_cfg_reg,
2830 TX_HPF_CUT_OFF_FREQ_MASK,
2831 hpf_coff_freq << 5);
2832 }
2833 break;
2834 case SND_SOC_DAPM_POST_PMD:
2835 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2836 break;
2837 }
2838
2839 return ret;
2840 }
2841
wcd9335_get_dmic_clk_val(struct snd_soc_component * component,u32 mclk_rate)2842 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2843 u32 mclk_rate)
2844 {
2845 u8 dmic_ctl_val;
2846
2847 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2848 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2849 else
2850 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2851
2852 return dmic_ctl_val;
2853 }
2854
wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2855 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2856 struct snd_kcontrol *kc, int event)
2857 {
2858 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2859 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2860 u8 dmic_clk_en = 0x01;
2861 u16 dmic_clk_reg;
2862 s32 *dmic_clk_cnt;
2863 u8 dmic_rate_val, dmic_rate_shift = 1;
2864 unsigned int dmic;
2865 int ret;
2866 char *wname;
2867
2868 wname = strpbrk(w->name, "012345");
2869 if (!wname) {
2870 dev_err(comp->dev, "%s: widget not found\n", __func__);
2871 return -EINVAL;
2872 }
2873
2874 ret = kstrtouint(wname, 10, &dmic);
2875 if (ret < 0) {
2876 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2877 __func__);
2878 return -EINVAL;
2879 }
2880
2881 switch (dmic) {
2882 case 0:
2883 case 1:
2884 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2885 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2886 break;
2887 case 2:
2888 case 3:
2889 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2890 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2891 break;
2892 case 4:
2893 case 5:
2894 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2895 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2896 break;
2897 default:
2898 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2899 __func__);
2900 return -EINVAL;
2901 }
2902
2903 switch (event) {
2904 case SND_SOC_DAPM_PRE_PMU:
2905 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2906 (*dmic_clk_cnt)++;
2907 if (*dmic_clk_cnt == 1) {
2908 snd_soc_component_update_bits(comp, dmic_clk_reg,
2909 0x07 << dmic_rate_shift,
2910 dmic_rate_val << dmic_rate_shift);
2911 snd_soc_component_update_bits(comp, dmic_clk_reg,
2912 dmic_clk_en, dmic_clk_en);
2913 }
2914
2915 break;
2916 case SND_SOC_DAPM_POST_PMD:
2917 dmic_rate_val = wcd9335_get_dmic_clk_val(comp, wcd->mclk_rate);
2918 (*dmic_clk_cnt)--;
2919 if (*dmic_clk_cnt == 0) {
2920 snd_soc_component_update_bits(comp, dmic_clk_reg,
2921 dmic_clk_en, 0);
2922 snd_soc_component_update_bits(comp, dmic_clk_reg,
2923 0x07 << dmic_rate_shift,
2924 dmic_rate_val << dmic_rate_shift);
2925 }
2926 break;
2927 }
2928
2929 return 0;
2930 }
2931
wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)2932 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2933 struct snd_soc_component *component)
2934 {
2935 int port_num = 0;
2936 unsigned short reg = 0;
2937 unsigned int val = 0;
2938 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2939 struct wcd9335_slim_ch *ch;
2940
2941 list_for_each_entry(ch, &dai->slim_ch_list, list) {
2942 if (ch->port >= WCD9335_RX_START) {
2943 port_num = ch->port - WCD9335_RX_START;
2944 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
2945 } else {
2946 port_num = ch->port;
2947 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
2948 }
2949
2950 regmap_read(wcd->if_regmap, reg, &val);
2951 if (!(val & BIT(port_num % 8)))
2952 regmap_write(wcd->if_regmap, reg,
2953 val | BIT(port_num % 8));
2954 }
2955 }
2956
wcd9335_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2957 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
2958 struct snd_kcontrol *kc,
2959 int event)
2960 {
2961 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2962 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2963 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
2964
2965 switch (event) {
2966 case SND_SOC_DAPM_POST_PMU:
2967 wcd9335_codec_enable_int_port(dai, comp);
2968 break;
2969 case SND_SOC_DAPM_POST_PMD:
2970 kfree(dai->sconfig.chs);
2971
2972 break;
2973 }
2974
2975 return 0;
2976 }
2977
wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2978 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
2979 struct snd_kcontrol *kc, int event)
2980 {
2981 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2982 u16 gain_reg;
2983 int val = 0;
2984
2985 switch (w->reg) {
2986 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
2987 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
2988 break;
2989 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
2990 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
2991 break;
2992 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
2993 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
2994 break;
2995 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
2996 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
2997 break;
2998 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
2999 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3000 break;
3001 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3002 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3003 break;
3004 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3005 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3006 break;
3007 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3008 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3009 break;
3010 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3011 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3012 break;
3013 default:
3014 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3015 __func__, w->name);
3016 return 0;
3017 }
3018
3019 switch (event) {
3020 case SND_SOC_DAPM_POST_PMU:
3021 val = snd_soc_component_read(comp, gain_reg);
3022 snd_soc_component_write(comp, gain_reg, val);
3023 break;
3024 case SND_SOC_DAPM_POST_PMD:
3025 break;
3026 }
3027
3028 return 0;
3029 }
3030
wcd9335_interp_get_primary_reg(u16 reg,u16 * ind)3031 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3032 {
3033 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3034
3035 switch (reg) {
3036 case WCD9335_CDC_RX0_RX_PATH_CTL:
3037 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3038 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3039 *ind = 0;
3040 break;
3041 case WCD9335_CDC_RX1_RX_PATH_CTL:
3042 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3043 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3044 *ind = 1;
3045 break;
3046 case WCD9335_CDC_RX2_RX_PATH_CTL:
3047 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3048 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3049 *ind = 2;
3050 break;
3051 case WCD9335_CDC_RX3_RX_PATH_CTL:
3052 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3053 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3054 *ind = 3;
3055 break;
3056 case WCD9335_CDC_RX4_RX_PATH_CTL:
3057 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3058 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3059 *ind = 4;
3060 break;
3061 case WCD9335_CDC_RX5_RX_PATH_CTL:
3062 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3063 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3064 *ind = 5;
3065 break;
3066 case WCD9335_CDC_RX6_RX_PATH_CTL:
3067 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3068 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3069 *ind = 6;
3070 break;
3071 case WCD9335_CDC_RX7_RX_PATH_CTL:
3072 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3073 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3074 *ind = 7;
3075 break;
3076 case WCD9335_CDC_RX8_RX_PATH_CTL:
3077 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3078 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3079 *ind = 8;
3080 break;
3081 }
3082
3083 return prim_int_reg;
3084 }
3085
wcd9335_codec_hd2_control(struct snd_soc_component * component,u16 prim_int_reg,int event)3086 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3087 u16 prim_int_reg, int event)
3088 {
3089 u16 hd2_scale_reg;
3090 u16 hd2_enable_reg = 0;
3091
3092 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3093 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3094 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3095 }
3096 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3097 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3098 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3099 }
3100
3101 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3102 snd_soc_component_update_bits(component, hd2_scale_reg,
3103 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3104 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3105 snd_soc_component_update_bits(component, hd2_scale_reg,
3106 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3107 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3108 snd_soc_component_update_bits(component, hd2_enable_reg,
3109 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3110 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3111 }
3112
3113 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3114 snd_soc_component_update_bits(component, hd2_enable_reg,
3115 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3116 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3117 snd_soc_component_update_bits(component, hd2_scale_reg,
3118 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3119 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3120 snd_soc_component_update_bits(component, hd2_scale_reg,
3121 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3122 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3123 }
3124 }
3125
wcd9335_codec_enable_prim_interpolator(struct snd_soc_component * comp,u16 reg,int event)3126 static int wcd9335_codec_enable_prim_interpolator(
3127 struct snd_soc_component *comp,
3128 u16 reg, int event)
3129 {
3130 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3131 u16 ind = 0;
3132 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3133
3134 switch (event) {
3135 case SND_SOC_DAPM_PRE_PMU:
3136 wcd->prim_int_users[ind]++;
3137 if (wcd->prim_int_users[ind] == 1) {
3138 snd_soc_component_update_bits(comp, prim_int_reg,
3139 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3140 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3141 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3142 snd_soc_component_update_bits(comp, prim_int_reg,
3143 WCD9335_CDC_RX_CLK_EN_MASK,
3144 WCD9335_CDC_RX_CLK_ENABLE);
3145 }
3146
3147 if ((reg != prim_int_reg) &&
3148 ((snd_soc_component_read(comp, prim_int_reg)) &
3149 WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3150 snd_soc_component_update_bits(comp, reg,
3151 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3152 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3153 break;
3154 case SND_SOC_DAPM_POST_PMD:
3155 wcd->prim_int_users[ind]--;
3156 if (wcd->prim_int_users[ind] == 0) {
3157 snd_soc_component_update_bits(comp, prim_int_reg,
3158 WCD9335_CDC_RX_CLK_EN_MASK,
3159 WCD9335_CDC_RX_CLK_DISABLE);
3160 snd_soc_component_update_bits(comp, prim_int_reg,
3161 WCD9335_CDC_RX_RESET_MASK,
3162 WCD9335_CDC_RX_RESET_ENABLE);
3163 snd_soc_component_update_bits(comp, prim_int_reg,
3164 WCD9335_CDC_RX_RESET_MASK,
3165 WCD9335_CDC_RX_RESET_DISABLE);
3166 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3167 }
3168 break;
3169 }
3170
3171 return 0;
3172 }
3173
wcd9335_config_compander(struct snd_soc_component * component,int interp_n,int event)3174 static int wcd9335_config_compander(struct snd_soc_component *component,
3175 int interp_n, int event)
3176 {
3177 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3178 int comp;
3179 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3180
3181 /* EAR does not have compander */
3182 if (!interp_n)
3183 return 0;
3184
3185 comp = interp_n - 1;
3186 if (!wcd->comp_enabled[comp])
3187 return 0;
3188
3189 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3190 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3191
3192 if (SND_SOC_DAPM_EVENT_ON(event)) {
3193 /* Enable Compander Clock */
3194 snd_soc_component_update_bits(component, comp_ctl0_reg,
3195 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3196 WCD9335_CDC_COMPANDER_CLK_ENABLE);
3197 /* Reset comander */
3198 snd_soc_component_update_bits(component, comp_ctl0_reg,
3199 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3200 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3201 snd_soc_component_update_bits(component, comp_ctl0_reg,
3202 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3203 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3204 /* Enables DRE in this path */
3205 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3206 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3207 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3208 }
3209
3210 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3211 snd_soc_component_update_bits(component, comp_ctl0_reg,
3212 WCD9335_CDC_COMPANDER_HALT_MASK,
3213 WCD9335_CDC_COMPANDER_HALT);
3214 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3215 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3216 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3217
3218 snd_soc_component_update_bits(component, comp_ctl0_reg,
3219 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3220 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3221 snd_soc_component_update_bits(component, comp_ctl0_reg,
3222 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3223 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3224 snd_soc_component_update_bits(component, comp_ctl0_reg,
3225 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3226 WCD9335_CDC_COMPANDER_CLK_DISABLE);
3227 snd_soc_component_update_bits(component, comp_ctl0_reg,
3228 WCD9335_CDC_COMPANDER_HALT_MASK,
3229 WCD9335_CDC_COMPANDER_NOHALT);
3230 }
3231
3232 return 0;
3233 }
3234
wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3235 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3236 struct snd_kcontrol *kc, int event)
3237 {
3238 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3239 u16 gain_reg;
3240 u16 reg;
3241 int val;
3242
3243 if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT0 INTERP"))) {
3244 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3245 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3246 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT1 INTERP"))) {
3247 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3248 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3249 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT2 INTERP"))) {
3250 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3251 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3252 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT3 INTERP"))) {
3253 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3254 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3255 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT4 INTERP"))) {
3256 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3257 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3258 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT5 INTERP"))) {
3259 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3260 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3261 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT6 INTERP"))) {
3262 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3263 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3264 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT7 INTERP"))) {
3265 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3266 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3267 } else if (!(snd_soc_dapm_widget_name_cmp(w, "RX INT8 INTERP"))) {
3268 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3269 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3270 } else {
3271 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3272 __func__);
3273 return -EINVAL;
3274 }
3275
3276 switch (event) {
3277 case SND_SOC_DAPM_PRE_PMU:
3278 /* Reset if needed */
3279 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3280 break;
3281 case SND_SOC_DAPM_POST_PMU:
3282 wcd9335_config_compander(comp, w->shift, event);
3283 val = snd_soc_component_read(comp, gain_reg);
3284 snd_soc_component_write(comp, gain_reg, val);
3285 break;
3286 case SND_SOC_DAPM_POST_PMD:
3287 wcd9335_config_compander(comp, w->shift, event);
3288 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3289 break;
3290 }
3291
3292 return 0;
3293 }
3294
wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component * component,u8 gain)3295 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3296 u8 gain)
3297 {
3298 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3299 u8 hph_l_en, hph_r_en;
3300 u8 l_val, r_val;
3301 u8 hph_pa_status;
3302 bool is_hphl_pa, is_hphr_pa;
3303
3304 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3305 is_hphl_pa = hph_pa_status >> 7;
3306 is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3307
3308 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3309 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3310
3311 l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3312 r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3313
3314 /*
3315 * Set HPH_L & HPH_R gain source selection to REGISTER
3316 * for better click and pop only if corresponding PAs are
3317 * not enabled. Also cache the values of the HPHL/R
3318 * PA gains to be applied after PAs are enabled
3319 */
3320 if ((l_val != hph_l_en) && !is_hphl_pa) {
3321 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3322 wcd->hph_l_gain = hph_l_en & 0x1F;
3323 }
3324
3325 if ((r_val != hph_r_en) && !is_hphr_pa) {
3326 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3327 wcd->hph_r_gain = hph_r_en & 0x1F;
3328 }
3329 }
3330
wcd9335_codec_hph_lohifi_config(struct snd_soc_component * comp,int event)3331 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3332 int event)
3333 {
3334 if (SND_SOC_DAPM_EVENT_ON(event)) {
3335 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3336 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3337 0x06);
3338 snd_soc_component_update_bits(comp,
3339 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3340 0xF0, 0x40);
3341 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3342 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3343 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3344 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3345 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3346 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3347 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3348 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3349 0x0C);
3350 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3351 }
3352
3353 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3354 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3355 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3356 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3357 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3358 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3359 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3360 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3361 0x8A);
3362 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3363 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3364 0x0A);
3365 }
3366 }
3367
wcd9335_codec_hph_lp_config(struct snd_soc_component * comp,int event)3368 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3369 int event)
3370 {
3371 if (SND_SOC_DAPM_EVENT_ON(event)) {
3372 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3373 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3374 0x0C);
3375 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3376 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3377 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3378 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3379 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3380 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3381 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3382 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3383 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3384 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3385 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3386 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3387 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3388 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3389 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3390 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3391 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3392 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3393 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3394 snd_soc_component_update_bits(comp,
3395 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3396 snd_soc_component_update_bits(comp,
3397 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3398 }
3399
3400 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3401 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3402 0x88);
3403 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3404 0x33);
3405 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3406 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3407 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3408 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3409 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3410 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3411 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3412 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3413 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3414 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3415 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3416 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3417 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3418 WCD9335_HPH_CONST_SEL_L_MASK,
3419 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3420 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3421 WCD9335_HPH_CONST_SEL_L_MASK,
3422 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3423 }
3424 }
3425
wcd9335_codec_hph_hifi_config(struct snd_soc_component * comp,int event)3426 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3427 int event)
3428 {
3429 if (SND_SOC_DAPM_EVENT_ON(event)) {
3430 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3431 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3432 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3433 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3434 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3435 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3436 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3437 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3438 0x0C);
3439 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3440 }
3441
3442 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3443 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3444 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3445 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3446 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3447 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3448 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3449 }
3450 }
3451
wcd9335_codec_hph_mode_config(struct snd_soc_component * component,int event,int mode)3452 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3453 int event, int mode)
3454 {
3455 switch (mode) {
3456 case CLS_H_LP:
3457 wcd9335_codec_hph_lp_config(component, event);
3458 break;
3459 case CLS_H_LOHIFI:
3460 wcd9335_codec_hph_lohifi_config(component, event);
3461 break;
3462 case CLS_H_HIFI:
3463 wcd9335_codec_hph_hifi_config(component, event);
3464 break;
3465 }
3466 }
3467
wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3468 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3469 struct snd_kcontrol *kc,
3470 int event)
3471 {
3472 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3473 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3474 int hph_mode = wcd->hph_mode;
3475 u8 dem_inp;
3476
3477 switch (event) {
3478 case SND_SOC_DAPM_PRE_PMU:
3479 /* Read DEM INP Select */
3480 dem_inp = snd_soc_component_read(comp,
3481 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3482 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3483 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3484 dev_err(comp->dev, "Incorrect DEM Input\n");
3485 return -EINVAL;
3486 }
3487 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3488 WCD_CLSH_STATE_HPHL,
3489 ((hph_mode == CLS_H_LOHIFI) ?
3490 CLS_H_HIFI : hph_mode));
3491
3492 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3493
3494 break;
3495 case SND_SOC_DAPM_POST_PMU:
3496 usleep_range(1000, 1100);
3497 break;
3498 case SND_SOC_DAPM_PRE_PMD:
3499 break;
3500 case SND_SOC_DAPM_POST_PMD:
3501 /* 1000us required as per HW requirement */
3502 usleep_range(1000, 1100);
3503
3504 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3505 WCD_CLSH_STATE_HPHR))
3506 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3507
3508 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3509 WCD_CLSH_STATE_HPHL,
3510 ((hph_mode == CLS_H_LOHIFI) ?
3511 CLS_H_HIFI : hph_mode));
3512 break;
3513 }
3514
3515 return 0;
3516 }
3517
wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3518 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3519 struct snd_kcontrol *kc, int event)
3520 {
3521 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3522 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3523
3524 switch (event) {
3525 case SND_SOC_DAPM_PRE_PMU:
3526 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3527 WCD_CLSH_STATE_LO, CLS_AB);
3528 break;
3529 case SND_SOC_DAPM_POST_PMD:
3530 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3531 WCD_CLSH_STATE_LO, CLS_AB);
3532 break;
3533 }
3534
3535 return 0;
3536 }
3537
wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3538 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3539 struct snd_kcontrol *kc, int event)
3540 {
3541 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3542 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3543
3544 switch (event) {
3545 case SND_SOC_DAPM_PRE_PMU:
3546 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3547 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3548
3549 break;
3550 case SND_SOC_DAPM_POST_PMD:
3551 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3552 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3553 break;
3554 }
3555
3556 return 0;
3557 }
3558
wcd9335_codec_hph_post_pa_config(struct wcd9335_codec * wcd,int mode,int event)3559 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3560 int mode, int event)
3561 {
3562 u8 scale_val = 0;
3563
3564 switch (event) {
3565 case SND_SOC_DAPM_POST_PMU:
3566 switch (mode) {
3567 case CLS_H_HIFI:
3568 scale_val = 0x3;
3569 break;
3570 case CLS_H_LOHIFI:
3571 scale_val = 0x1;
3572 break;
3573 }
3574 break;
3575 case SND_SOC_DAPM_PRE_PMD:
3576 scale_val = 0x6;
3577 break;
3578 }
3579
3580 if (scale_val)
3581 snd_soc_component_update_bits(wcd->component,
3582 WCD9335_HPH_PA_CTL1,
3583 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3584 scale_val << 1);
3585 if (SND_SOC_DAPM_EVENT_ON(event)) {
3586 if (wcd->comp_enabled[COMPANDER_1] ||
3587 wcd->comp_enabled[COMPANDER_2]) {
3588 /* GAIN Source Selection */
3589 snd_soc_component_update_bits(wcd->component,
3590 WCD9335_HPH_L_EN,
3591 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3592 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3593 snd_soc_component_update_bits(wcd->component,
3594 WCD9335_HPH_R_EN,
3595 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3596 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3597 snd_soc_component_update_bits(wcd->component,
3598 WCD9335_HPH_AUTO_CHOP,
3599 WCD9335_HPH_AUTO_CHOP_MASK,
3600 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3601 }
3602 snd_soc_component_update_bits(wcd->component,
3603 WCD9335_HPH_L_EN,
3604 WCD9335_HPH_PA_GAIN_MASK,
3605 wcd->hph_l_gain);
3606 snd_soc_component_update_bits(wcd->component,
3607 WCD9335_HPH_R_EN,
3608 WCD9335_HPH_PA_GAIN_MASK,
3609 wcd->hph_r_gain);
3610 }
3611
3612 if (SND_SOC_DAPM_EVENT_OFF(event))
3613 snd_soc_component_update_bits(wcd->component,
3614 WCD9335_HPH_AUTO_CHOP,
3615 WCD9335_HPH_AUTO_CHOP_MASK,
3616 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3617 }
3618
wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3619 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3620 struct snd_kcontrol *kc,
3621 int event)
3622 {
3623 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3624 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3625 int hph_mode = wcd->hph_mode;
3626 u8 dem_inp;
3627
3628 switch (event) {
3629 case SND_SOC_DAPM_PRE_PMU:
3630
3631 /* Read DEM INP Select */
3632 dem_inp = snd_soc_component_read(comp,
3633 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3634 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3635 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3636 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3637 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3638 hph_mode);
3639 return -EINVAL;
3640 }
3641
3642 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3643 WCD_CLSH_EVENT_PRE_DAC,
3644 WCD_CLSH_STATE_HPHR,
3645 ((hph_mode == CLS_H_LOHIFI) ?
3646 CLS_H_HIFI : hph_mode));
3647
3648 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3649
3650 break;
3651 case SND_SOC_DAPM_POST_PMD:
3652 /* 1000us required as per HW requirement */
3653 usleep_range(1000, 1100);
3654
3655 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3656 WCD_CLSH_STATE_HPHL))
3657 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3658
3659 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3660 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3661 CLS_H_HIFI : hph_mode));
3662 break;
3663 }
3664
3665 return 0;
3666 }
3667
wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3668 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3669 struct snd_kcontrol *kc,
3670 int event)
3671 {
3672 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3673 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3674 int hph_mode = wcd->hph_mode;
3675
3676 switch (event) {
3677 case SND_SOC_DAPM_PRE_PMU:
3678 break;
3679 case SND_SOC_DAPM_POST_PMU:
3680 /*
3681 * 7ms sleep is required after PA is enabled as per
3682 * HW requirement
3683 */
3684 usleep_range(7000, 7100);
3685
3686 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3687 snd_soc_component_update_bits(comp,
3688 WCD9335_CDC_RX1_RX_PATH_CTL,
3689 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3690 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3691
3692 /* Remove mix path mute if it is enabled */
3693 if ((snd_soc_component_read(comp,
3694 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3695 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3696 snd_soc_component_update_bits(comp,
3697 WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3698 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3699 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3700
3701 break;
3702 case SND_SOC_DAPM_PRE_PMD:
3703 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3704 break;
3705 case SND_SOC_DAPM_POST_PMD:
3706 /* 5ms sleep is required after PA is disabled as per
3707 * HW requirement
3708 */
3709 usleep_range(5000, 5500);
3710 break;
3711 }
3712
3713 return 0;
3714 }
3715
wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3716 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3717 struct snd_kcontrol *kc,
3718 int event)
3719 {
3720 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3721 int vol_reg = 0, mix_vol_reg = 0;
3722
3723 if (w->reg == WCD9335_ANA_LO_1_2) {
3724 if (w->shift == 7) {
3725 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3726 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3727 } else if (w->shift == 6) {
3728 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3729 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3730 }
3731 } else if (w->reg == WCD9335_ANA_LO_3_4) {
3732 if (w->shift == 7) {
3733 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3734 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3735 } else if (w->shift == 6) {
3736 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3737 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3738 }
3739 } else {
3740 dev_err(comp->dev, "Error enabling lineout PA\n");
3741 return -EINVAL;
3742 }
3743
3744 switch (event) {
3745 case SND_SOC_DAPM_POST_PMU:
3746 /* 5ms sleep is required after PA is enabled as per
3747 * HW requirement
3748 */
3749 usleep_range(5000, 5500);
3750 snd_soc_component_update_bits(comp, vol_reg,
3751 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3752 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3753
3754 /* Remove mix path mute if it is enabled */
3755 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3756 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3757 snd_soc_component_update_bits(comp, mix_vol_reg,
3758 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3759 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3760 break;
3761 case SND_SOC_DAPM_POST_PMD:
3762 /* 5ms sleep is required after PA is disabled as per
3763 * HW requirement
3764 */
3765 usleep_range(5000, 5500);
3766 break;
3767 }
3768
3769 return 0;
3770 }
3771
wcd9335_codec_init_flyback(struct snd_soc_component * component)3772 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3773 {
3774 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3775 WCD9335_HPH_CONST_SEL_L_MASK,
3776 WCD9335_HPH_CONST_SEL_L_BYPASS);
3777 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3778 WCD9335_HPH_CONST_SEL_L_MASK,
3779 WCD9335_HPH_CONST_SEL_L_BYPASS);
3780 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3781 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3782 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3783 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3784 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3785 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3786 }
3787
wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3788 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3789 struct snd_kcontrol *kc, int event)
3790 {
3791 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3792 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3793
3794 switch (event) {
3795 case SND_SOC_DAPM_PRE_PMU:
3796 wcd->rx_bias_count++;
3797 if (wcd->rx_bias_count == 1) {
3798 wcd9335_codec_init_flyback(comp);
3799 snd_soc_component_update_bits(comp,
3800 WCD9335_ANA_RX_SUPPLIES,
3801 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3802 WCD9335_ANA_RX_BIAS_ENABLE);
3803 }
3804 break;
3805 case SND_SOC_DAPM_POST_PMD:
3806 wcd->rx_bias_count--;
3807 if (!wcd->rx_bias_count)
3808 snd_soc_component_update_bits(comp,
3809 WCD9335_ANA_RX_SUPPLIES,
3810 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3811 WCD9335_ANA_RX_BIAS_DISABLE);
3812 break;
3813 }
3814
3815 return 0;
3816 }
3817
wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3818 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3819 struct snd_kcontrol *kc, int event)
3820 {
3821 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3822 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3823 int hph_mode = wcd->hph_mode;
3824
3825 switch (event) {
3826 case SND_SOC_DAPM_PRE_PMU:
3827 break;
3828 case SND_SOC_DAPM_POST_PMU:
3829 /*
3830 * 7ms sleep is required after PA is enabled as per
3831 * HW requirement
3832 */
3833 usleep_range(7000, 7100);
3834 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3835 snd_soc_component_update_bits(comp,
3836 WCD9335_CDC_RX2_RX_PATH_CTL,
3837 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3838 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3839 /* Remove mix path mute if it is enabled */
3840 if ((snd_soc_component_read(comp,
3841 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3842 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3843 snd_soc_component_update_bits(comp,
3844 WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3845 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3846 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3847
3848 break;
3849
3850 case SND_SOC_DAPM_PRE_PMD:
3851 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3852 break;
3853 case SND_SOC_DAPM_POST_PMD:
3854 /* 5ms sleep is required after PA is disabled as per
3855 * HW requirement
3856 */
3857 usleep_range(5000, 5500);
3858 break;
3859 }
3860
3861 return 0;
3862 }
3863
wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3864 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3865 struct snd_kcontrol *kc, int event)
3866 {
3867 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3868
3869 switch (event) {
3870 case SND_SOC_DAPM_POST_PMU:
3871 /* 5ms sleep is required after PA is enabled as per
3872 * HW requirement
3873 */
3874 usleep_range(5000, 5500);
3875 snd_soc_component_update_bits(comp,
3876 WCD9335_CDC_RX0_RX_PATH_CTL,
3877 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3878 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3879 /* Remove mix path mute if it is enabled */
3880 if ((snd_soc_component_read(comp,
3881 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3882 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3883 snd_soc_component_update_bits(comp,
3884 WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3885 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3886 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3887 break;
3888 case SND_SOC_DAPM_POST_PMD:
3889 /* 5ms sleep is required after PA is disabled as per
3890 * HW requirement
3891 */
3892 usleep_range(5000, 5500);
3893
3894 break;
3895 }
3896
3897 return 0;
3898 }
3899
wcd9335_slimbus_irq(int irq,void * data)3900 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3901 {
3902 struct wcd9335_codec *wcd = data;
3903 unsigned long status = 0;
3904 int i, j, port_id;
3905 unsigned int val, int_val = 0;
3906 irqreturn_t ret = IRQ_NONE;
3907 bool tx;
3908 unsigned short reg = 0;
3909
3910 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3911 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3912 regmap_read(wcd->if_regmap, i, &val);
3913 status |= ((u32)val << (8 * j));
3914 }
3915
3916 for_each_set_bit(j, &status, 32) {
3917 tx = (j >= 16);
3918 port_id = (tx ? j - 16 : j);
3919 regmap_read(wcd->if_regmap,
3920 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3921 if (val) {
3922 if (!tx)
3923 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3924 (port_id / 8);
3925 else
3926 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3927 (port_id / 8);
3928 regmap_read(
3929 wcd->if_regmap, reg, &int_val);
3930 /*
3931 * Ignore interrupts for ports for which the
3932 * interrupts are not specifically enabled.
3933 */
3934 if (!(int_val & (1 << (port_id % 8))))
3935 continue;
3936 }
3937
3938 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
3939 dev_err_ratelimited(wcd->dev,
3940 "%s: overflow error on %s port %d, value %x\n",
3941 __func__, (tx ? "TX" : "RX"), port_id, val);
3942
3943 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
3944 dev_err_ratelimited(wcd->dev,
3945 "%s: underflow error on %s port %d, value %x\n",
3946 __func__, (tx ? "TX" : "RX"), port_id, val);
3947
3948 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
3949 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
3950 if (!tx)
3951 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3952 (port_id / 8);
3953 else
3954 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3955 (port_id / 8);
3956 regmap_read(
3957 wcd->if_regmap, reg, &int_val);
3958 if (int_val & (1 << (port_id % 8))) {
3959 int_val = int_val ^ (1 << (port_id % 8));
3960 regmap_write(wcd->if_regmap,
3961 reg, int_val);
3962 }
3963 }
3964
3965 regmap_write(wcd->if_regmap,
3966 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
3967 BIT(j % 8));
3968 ret = IRQ_HANDLED;
3969 }
3970
3971 return ret;
3972 }
3973
3974 static const struct wcd9335_irq wcd9335_irqs[] = {
3975 {
3976 .irq = WCD9335_IRQ_SLIMBUS,
3977 .handler = wcd9335_slimbus_irq,
3978 .name = "SLIM Slave",
3979 },
3980 };
3981
wcd9335_setup_irqs(struct wcd9335_codec * wcd)3982 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
3983 {
3984 int irq, ret, i;
3985
3986 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
3987 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
3988 if (irq < 0) {
3989 dev_err(wcd->dev, "Failed to get %s\n",
3990 wcd9335_irqs[i].name);
3991 return irq;
3992 }
3993
3994 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
3995 wcd9335_irqs[i].handler,
3996 IRQF_TRIGGER_RISING |
3997 IRQF_ONESHOT,
3998 wcd9335_irqs[i].name, wcd);
3999 if (ret) {
4000 dev_err(wcd->dev, "Failed to request %s\n",
4001 wcd9335_irqs[i].name);
4002 return ret;
4003 }
4004 }
4005
4006 /* enable interrupts on all slave ports */
4007 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4008 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4009 0xFF);
4010
4011 return ret;
4012 }
4013
wcd9335_teardown_irqs(struct wcd9335_codec * wcd)4014 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4015 {
4016 int i;
4017
4018 /* disable interrupts on all slave ports */
4019 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4020 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4021 0x00);
4022 }
4023
wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec * wcd,bool ccl_flag)4024 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4025 bool ccl_flag)
4026 {
4027 struct snd_soc_component *comp = wcd->component;
4028
4029 if (ccl_flag) {
4030 if (++wcd->sido_ccl_cnt == 1)
4031 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4032 WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4033 } else {
4034 if (wcd->sido_ccl_cnt == 0) {
4035 dev_err(wcd->dev, "sido_ccl already disabled\n");
4036 return;
4037 }
4038 if (--wcd->sido_ccl_cnt == 0)
4039 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4040 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4041 }
4042 }
4043
wcd9335_enable_master_bias(struct wcd9335_codec * wcd)4044 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4045 {
4046 wcd->master_bias_users++;
4047 if (wcd->master_bias_users == 1) {
4048 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4049 WCD9335_ANA_BIAS_EN_MASK,
4050 WCD9335_ANA_BIAS_ENABLE);
4051 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4052 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4053 WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4054 /*
4055 * 1ms delay is required after pre-charge is enabled
4056 * as per HW requirement
4057 */
4058 usleep_range(1000, 1100);
4059 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4060 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4061 WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4062 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4063 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4064 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4065 }
4066
4067 return 0;
4068 }
4069
wcd9335_enable_mclk(struct wcd9335_codec * wcd)4070 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4071 {
4072 /* Enable mclk requires master bias to be enabled first */
4073 if (wcd->master_bias_users <= 0)
4074 return -EINVAL;
4075
4076 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4077 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4078 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4079 wcd->clk_type);
4080 return -EINVAL;
4081 }
4082
4083 if (++wcd->clk_mclk_users == 1) {
4084 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4085 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4086 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4087 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4088 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4089 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4090 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4091 WCD9335_ANA_CLK_MCLK_EN_MASK,
4092 WCD9335_ANA_CLK_MCLK_ENABLE);
4093 regmap_update_bits(wcd->regmap,
4094 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4095 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4096 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4097 regmap_update_bits(wcd->regmap,
4098 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4099 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4100 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4101 /*
4102 * 10us sleep is required after clock is enabled
4103 * as per HW requirement
4104 */
4105 usleep_range(10, 15);
4106 }
4107
4108 wcd->clk_type = WCD_CLK_MCLK;
4109
4110 return 0;
4111 }
4112
wcd9335_disable_mclk(struct wcd9335_codec * wcd)4113 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4114 {
4115 if (wcd->clk_mclk_users <= 0)
4116 return -EINVAL;
4117
4118 if (--wcd->clk_mclk_users == 0) {
4119 if (wcd->clk_rco_users > 0) {
4120 /* MCLK to RCO switch */
4121 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4122 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4123 WCD9335_ANA_CLK_MCLK_SRC_RCO);
4124 wcd->clk_type = WCD_CLK_RCO;
4125 } else {
4126 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4127 WCD9335_ANA_CLK_MCLK_EN_MASK,
4128 WCD9335_ANA_CLK_MCLK_DISABLE);
4129 wcd->clk_type = WCD_CLK_OFF;
4130 }
4131
4132 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4133 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4134 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4135 }
4136
4137 return 0;
4138 }
4139
wcd9335_disable_master_bias(struct wcd9335_codec * wcd)4140 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4141 {
4142 if (wcd->master_bias_users <= 0)
4143 return -EINVAL;
4144
4145 wcd->master_bias_users--;
4146 if (wcd->master_bias_users == 0) {
4147 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4148 WCD9335_ANA_BIAS_EN_MASK,
4149 WCD9335_ANA_BIAS_DISABLE);
4150 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4151 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4152 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4153 }
4154 return 0;
4155 }
4156
wcd9335_cdc_req_mclk_enable(struct wcd9335_codec * wcd,bool enable)4157 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4158 bool enable)
4159 {
4160 int ret = 0;
4161
4162 if (enable) {
4163 wcd9335_cdc_sido_ccl_enable(wcd, true);
4164 ret = clk_prepare_enable(wcd->mclk);
4165 if (ret) {
4166 dev_err(wcd->dev, "%s: ext clk enable failed\n",
4167 __func__);
4168 goto err;
4169 }
4170 /* get BG */
4171 wcd9335_enable_master_bias(wcd);
4172 /* get MCLK */
4173 wcd9335_enable_mclk(wcd);
4174
4175 } else {
4176 /* put MCLK */
4177 wcd9335_disable_mclk(wcd);
4178 /* put BG */
4179 wcd9335_disable_master_bias(wcd);
4180 clk_disable_unprepare(wcd->mclk);
4181 wcd9335_cdc_sido_ccl_enable(wcd, false);
4182 }
4183 err:
4184 return ret;
4185 }
4186
wcd9335_codec_apply_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4187 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4188 enum wcd9335_sido_voltage req_mv)
4189 {
4190 struct snd_soc_component *comp = wcd->component;
4191 int vout_d_val;
4192
4193 if (req_mv == wcd->sido_voltage)
4194 return;
4195
4196 /* compute the vout_d step value */
4197 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4198 WCD9335_ANA_BUCK_VOUT_MASK;
4199 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4200 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4201 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4202 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4203
4204 /* 1 msec sleep required after SIDO Vout_D voltage change */
4205 usleep_range(1000, 1100);
4206 wcd->sido_voltage = req_mv;
4207 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4208 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4209 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4210 }
4211
wcd9335_codec_update_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4212 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4213 enum wcd9335_sido_voltage req_mv)
4214 {
4215 int ret = 0;
4216
4217 /* enable mclk before setting SIDO voltage */
4218 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4219 if (ret) {
4220 dev_err(wcd->dev, "Ext clk enable failed\n");
4221 goto err;
4222 }
4223
4224 wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4225 wcd9335_cdc_req_mclk_enable(wcd, false);
4226
4227 err:
4228 return ret;
4229 }
4230
_wcd9335_codec_enable_mclk(struct snd_soc_component * component,int enable)4231 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4232 int enable)
4233 {
4234 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4235 int ret;
4236
4237 if (enable) {
4238 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4239 if (ret)
4240 return ret;
4241
4242 wcd9335_codec_apply_sido_voltage(wcd,
4243 SIDO_VOLTAGE_NOMINAL_MV);
4244 } else {
4245 wcd9335_codec_update_sido_voltage(wcd,
4246 wcd->sido_voltage);
4247 wcd9335_cdc_req_mclk_enable(wcd, false);
4248 }
4249
4250 return 0;
4251 }
4252
wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4253 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4254 struct snd_kcontrol *kc, int event)
4255 {
4256 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4257
4258 switch (event) {
4259 case SND_SOC_DAPM_PRE_PMU:
4260 return _wcd9335_codec_enable_mclk(comp, true);
4261 case SND_SOC_DAPM_POST_PMD:
4262 return _wcd9335_codec_enable_mclk(comp, false);
4263 }
4264
4265 return 0;
4266 }
4267
4268 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4269 /* TODO SPK1 & SPK2 OUT*/
4270 SND_SOC_DAPM_OUTPUT("EAR"),
4271 SND_SOC_DAPM_OUTPUT("HPHL"),
4272 SND_SOC_DAPM_OUTPUT("HPHR"),
4273 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4274 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4275 SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4276 SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4277 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4278 AIF1_PB, 0, wcd9335_codec_enable_slim,
4279 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4280 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4281 AIF2_PB, 0, wcd9335_codec_enable_slim,
4282 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4283 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4284 AIF3_PB, 0, wcd9335_codec_enable_slim,
4285 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4286 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4287 AIF4_PB, 0, wcd9335_codec_enable_slim,
4288 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4289 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4290 &slim_rx_mux[WCD9335_RX0]),
4291 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4292 &slim_rx_mux[WCD9335_RX1]),
4293 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4294 &slim_rx_mux[WCD9335_RX2]),
4295 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4296 &slim_rx_mux[WCD9335_RX3]),
4297 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4298 &slim_rx_mux[WCD9335_RX4]),
4299 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4300 &slim_rx_mux[WCD9335_RX5]),
4301 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4302 &slim_rx_mux[WCD9335_RX6]),
4303 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4304 &slim_rx_mux[WCD9335_RX7]),
4305 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4306 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4307 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4308 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4309 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4310 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4311 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4312 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4313 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4314 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4315 SND_SOC_DAPM_POST_PMU),
4316 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4317 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4318 SND_SOC_DAPM_POST_PMU),
4319 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4320 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4321 SND_SOC_DAPM_POST_PMU),
4322 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4323 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4324 SND_SOC_DAPM_POST_PMU),
4325 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4326 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4327 SND_SOC_DAPM_POST_PMU),
4328 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4329 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4330 SND_SOC_DAPM_POST_PMU),
4331 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4332 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4333 SND_SOC_DAPM_POST_PMU),
4334 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4335 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4336 SND_SOC_DAPM_POST_PMU),
4337 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4338 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4339 SND_SOC_DAPM_POST_PMU),
4340 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4341 &rx_int0_1_mix_inp0_mux),
4342 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4343 &rx_int0_1_mix_inp1_mux),
4344 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4345 &rx_int0_1_mix_inp2_mux),
4346 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4347 &rx_int1_1_mix_inp0_mux),
4348 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4349 &rx_int1_1_mix_inp1_mux),
4350 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4351 &rx_int1_1_mix_inp2_mux),
4352 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4353 &rx_int2_1_mix_inp0_mux),
4354 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4355 &rx_int2_1_mix_inp1_mux),
4356 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4357 &rx_int2_1_mix_inp2_mux),
4358 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4359 &rx_int3_1_mix_inp0_mux),
4360 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4361 &rx_int3_1_mix_inp1_mux),
4362 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4363 &rx_int3_1_mix_inp2_mux),
4364 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4365 &rx_int4_1_mix_inp0_mux),
4366 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4367 &rx_int4_1_mix_inp1_mux),
4368 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4369 &rx_int4_1_mix_inp2_mux),
4370 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4371 &rx_int5_1_mix_inp0_mux),
4372 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4373 &rx_int5_1_mix_inp1_mux),
4374 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4375 &rx_int5_1_mix_inp2_mux),
4376 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4377 &rx_int6_1_mix_inp0_mux),
4378 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4379 &rx_int6_1_mix_inp1_mux),
4380 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4381 &rx_int6_1_mix_inp2_mux),
4382 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4383 &rx_int7_1_mix_inp0_mux),
4384 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4385 &rx_int7_1_mix_inp1_mux),
4386 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4387 &rx_int7_1_mix_inp2_mux),
4388 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4389 &rx_int8_1_mix_inp0_mux),
4390 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4391 &rx_int8_1_mix_inp1_mux),
4392 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4393 &rx_int8_1_mix_inp2_mux),
4394
4395 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4396 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4397 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4398 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4399 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4400 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4401 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4402 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4403 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4404 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4405 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4406 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4407 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4408 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4409 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4410 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4411 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4412 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4413
4414 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4415 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4416 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4417 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4418 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4419 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4420 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4421 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4422 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4423
4424 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4425 &rx_int0_dem_inp_mux),
4426 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4427 &rx_int1_dem_inp_mux),
4428 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4429 &rx_int2_dem_inp_mux),
4430
4431 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4432 INTERP_EAR, 0, &rx_int0_interp_mux,
4433 wcd9335_codec_enable_interpolator,
4434 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4435 SND_SOC_DAPM_POST_PMD),
4436 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4437 INTERP_HPHL, 0, &rx_int1_interp_mux,
4438 wcd9335_codec_enable_interpolator,
4439 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4440 SND_SOC_DAPM_POST_PMD),
4441 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4442 INTERP_HPHR, 0, &rx_int2_interp_mux,
4443 wcd9335_codec_enable_interpolator,
4444 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4445 SND_SOC_DAPM_POST_PMD),
4446 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4447 INTERP_LO1, 0, &rx_int3_interp_mux,
4448 wcd9335_codec_enable_interpolator,
4449 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4450 SND_SOC_DAPM_POST_PMD),
4451 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4452 INTERP_LO2, 0, &rx_int4_interp_mux,
4453 wcd9335_codec_enable_interpolator,
4454 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4455 SND_SOC_DAPM_POST_PMD),
4456 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4457 INTERP_LO3, 0, &rx_int5_interp_mux,
4458 wcd9335_codec_enable_interpolator,
4459 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4460 SND_SOC_DAPM_POST_PMD),
4461 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4462 INTERP_LO4, 0, &rx_int6_interp_mux,
4463 wcd9335_codec_enable_interpolator,
4464 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4465 SND_SOC_DAPM_POST_PMD),
4466 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4467 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4468 wcd9335_codec_enable_interpolator,
4469 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4470 SND_SOC_DAPM_POST_PMD),
4471 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4472 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4473 wcd9335_codec_enable_interpolator,
4474 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4475 SND_SOC_DAPM_POST_PMD),
4476
4477 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4478 0, 0, wcd9335_codec_ear_dac_event,
4479 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4480 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4481 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4482 5, 0, wcd9335_codec_hphl_dac_event,
4483 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4484 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4485 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4486 4, 0, wcd9335_codec_hphr_dac_event,
4487 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4488 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4489 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4490 0, 0, wcd9335_codec_lineout_dac_event,
4491 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4492 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4493 0, 0, wcd9335_codec_lineout_dac_event,
4494 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4495 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4496 0, 0, wcd9335_codec_lineout_dac_event,
4497 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4498 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4499 0, 0, wcd9335_codec_lineout_dac_event,
4500 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4501 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4502 wcd9335_codec_enable_hphl_pa,
4503 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4504 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4505 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4506 wcd9335_codec_enable_hphr_pa,
4507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4508 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4509 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4510 wcd9335_codec_enable_ear_pa,
4511 SND_SOC_DAPM_POST_PMU |
4512 SND_SOC_DAPM_POST_PMD),
4513 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4514 wcd9335_codec_enable_lineout_pa,
4515 SND_SOC_DAPM_POST_PMU |
4516 SND_SOC_DAPM_POST_PMD),
4517 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4518 wcd9335_codec_enable_lineout_pa,
4519 SND_SOC_DAPM_POST_PMU |
4520 SND_SOC_DAPM_POST_PMD),
4521 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4522 wcd9335_codec_enable_lineout_pa,
4523 SND_SOC_DAPM_POST_PMU |
4524 SND_SOC_DAPM_POST_PMD),
4525 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4526 wcd9335_codec_enable_lineout_pa,
4527 SND_SOC_DAPM_POST_PMU |
4528 SND_SOC_DAPM_POST_PMD),
4529 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4530 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4531 SND_SOC_DAPM_POST_PMD),
4532 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4533 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4534 SND_SOC_DAPM_POST_PMD),
4535
4536 /* TX */
4537 SND_SOC_DAPM_INPUT("AMIC1"),
4538 SND_SOC_DAPM_INPUT("AMIC2"),
4539 SND_SOC_DAPM_INPUT("AMIC3"),
4540 SND_SOC_DAPM_INPUT("AMIC4"),
4541 SND_SOC_DAPM_INPUT("AMIC5"),
4542 SND_SOC_DAPM_INPUT("AMIC6"),
4543
4544 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4545 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4546 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4547
4548 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4549 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4550 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4551
4552 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4553 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4554 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4555
4556 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4557 wcd9335_codec_enable_micbias,
4558 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4559 SND_SOC_DAPM_POST_PMD),
4560 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4561 wcd9335_codec_enable_micbias,
4562 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4563 SND_SOC_DAPM_POST_PMD),
4564 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4565 wcd9335_codec_enable_micbias,
4566 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4567 SND_SOC_DAPM_POST_PMD),
4568 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4569 wcd9335_codec_enable_micbias,
4570 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4571 SND_SOC_DAPM_POST_PMD),
4572
4573 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4574 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4575 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4576 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4577 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4578 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4579 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4580 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4581 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4582 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4583 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4584 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4585
4586 /* Digital Mic Inputs */
4587 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4588 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4589 SND_SOC_DAPM_POST_PMD),
4590
4591 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4592 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4593 SND_SOC_DAPM_POST_PMD),
4594
4595 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4596 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4597 SND_SOC_DAPM_POST_PMD),
4598
4599 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4600 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4601 SND_SOC_DAPM_POST_PMD),
4602
4603 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4604 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4605 SND_SOC_DAPM_POST_PMD),
4606
4607 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4608 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4609 SND_SOC_DAPM_POST_PMD),
4610
4611 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4612 &tx_dmic_mux0),
4613 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4614 &tx_dmic_mux1),
4615 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4616 &tx_dmic_mux2),
4617 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4618 &tx_dmic_mux3),
4619 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4620 &tx_dmic_mux4),
4621 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4622 &tx_dmic_mux5),
4623 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4624 &tx_dmic_mux6),
4625 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4626 &tx_dmic_mux7),
4627 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4628 &tx_dmic_mux8),
4629
4630 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4631 &tx_amic_mux0),
4632 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4633 &tx_amic_mux1),
4634 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4635 &tx_amic_mux2),
4636 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4637 &tx_amic_mux3),
4638 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4639 &tx_amic_mux4),
4640 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4641 &tx_amic_mux5),
4642 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4643 &tx_amic_mux6),
4644 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4645 &tx_amic_mux7),
4646 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4647 &tx_amic_mux8),
4648
4649 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4650 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4651
4652 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4653 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4654
4655 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4656 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4657
4658 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4659 &sb_tx0_mux),
4660 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4661 &sb_tx1_mux),
4662 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4663 &sb_tx2_mux),
4664 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4665 &sb_tx3_mux),
4666 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4667 &sb_tx4_mux),
4668 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4669 &sb_tx5_mux),
4670 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4671 &sb_tx6_mux),
4672 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4673 &sb_tx7_mux),
4674 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4675 &sb_tx8_mux),
4676
4677 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4678 &tx_adc_mux0, wcd9335_codec_enable_dec,
4679 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4680 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4681
4682 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4683 &tx_adc_mux1, wcd9335_codec_enable_dec,
4684 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4685 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4686
4687 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4688 &tx_adc_mux2, wcd9335_codec_enable_dec,
4689 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4690 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4691
4692 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4693 &tx_adc_mux3, wcd9335_codec_enable_dec,
4694 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4695 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4696
4697 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4698 &tx_adc_mux4, wcd9335_codec_enable_dec,
4699 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4700 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4701
4702 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4703 &tx_adc_mux5, wcd9335_codec_enable_dec,
4704 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4705 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4706
4707 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4708 &tx_adc_mux6, wcd9335_codec_enable_dec,
4709 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4710 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4711
4712 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4713 &tx_adc_mux7, wcd9335_codec_enable_dec,
4714 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4715 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4716
4717 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4718 &tx_adc_mux8, wcd9335_codec_enable_dec,
4719 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4720 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4721 };
4722
wcd9335_enable_sido_buck(struct snd_soc_component * component)4723 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4724 {
4725 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4726
4727 snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4728 WCD9335_ANA_RCO_BG_EN_MASK,
4729 WCD9335_ANA_RCO_BG_ENABLE);
4730 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4731 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4732 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4733 /* 100us sleep needed after IREF settings */
4734 usleep_range(100, 110);
4735 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4736 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4737 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4738 /* 100us sleep needed after VREF settings */
4739 usleep_range(100, 110);
4740 wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4741 }
4742
wcd9335_enable_efuse_sensing(struct snd_soc_component * comp)4743 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4744 {
4745 _wcd9335_codec_enable_mclk(comp, true);
4746 snd_soc_component_update_bits(comp,
4747 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4748 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4749 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4750 /*
4751 * 5ms sleep required after enabling efuse control
4752 * before checking the status.
4753 */
4754 usleep_range(5000, 5500);
4755
4756 if (!(snd_soc_component_read(comp,
4757 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4758 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4759 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4760
4761 wcd9335_enable_sido_buck(comp);
4762 _wcd9335_codec_enable_mclk(comp, false);
4763
4764 return 0;
4765 }
4766
wcd9335_codec_init(struct snd_soc_component * component)4767 static void wcd9335_codec_init(struct snd_soc_component *component)
4768 {
4769 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4770 int i;
4771
4772 /* ungate MCLK and set clk rate */
4773 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4774 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4775
4776 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4777 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4778 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4779
4780 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4781 snd_soc_component_update_bits(component,
4782 wcd9335_codec_reg_init[i].reg,
4783 wcd9335_codec_reg_init[i].mask,
4784 wcd9335_codec_reg_init[i].val);
4785
4786 wcd9335_enable_efuse_sensing(component);
4787 }
4788
wcd9335_codec_probe(struct snd_soc_component * component)4789 static int wcd9335_codec_probe(struct snd_soc_component *component)
4790 {
4791 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4792 int ret;
4793 int i;
4794
4795 snd_soc_component_init_regmap(component, wcd->regmap);
4796 /* Class-H Init*/
4797 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
4798 if (IS_ERR(wcd->clsh_ctrl))
4799 return PTR_ERR(wcd->clsh_ctrl);
4800
4801 /* Default HPH Mode to Class-H HiFi */
4802 wcd->hph_mode = CLS_H_HIFI;
4803 wcd->component = component;
4804
4805 wcd9335_codec_init(component);
4806
4807 for (i = 0; i < NUM_CODEC_DAIS; i++)
4808 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4809
4810 ret = wcd9335_setup_irqs(wcd);
4811 if (ret)
4812 goto free_clsh_ctrl;
4813
4814 return 0;
4815
4816 free_clsh_ctrl:
4817 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4818 return ret;
4819 }
4820
wcd9335_codec_remove(struct snd_soc_component * comp)4821 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4822 {
4823 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4824
4825 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4826 wcd9335_teardown_irqs(wcd);
4827 }
4828
wcd9335_codec_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)4829 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4830 int clk_id, int source,
4831 unsigned int freq, int dir)
4832 {
4833 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4834
4835 wcd->mclk_rate = freq;
4836
4837 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4838 snd_soc_component_update_bits(comp,
4839 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4840 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4841 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4842 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4843 snd_soc_component_update_bits(comp,
4844 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4845 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4846 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4847
4848 return clk_set_rate(wcd->mclk, freq);
4849 }
4850
4851 static const struct snd_soc_component_driver wcd9335_component_drv = {
4852 .probe = wcd9335_codec_probe,
4853 .remove = wcd9335_codec_remove,
4854 .set_sysclk = wcd9335_codec_set_sysclk,
4855 .controls = wcd9335_snd_controls,
4856 .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4857 .dapm_widgets = wcd9335_dapm_widgets,
4858 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4859 .dapm_routes = wcd9335_audio_map,
4860 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4861 .endianness = 1,
4862 };
4863
wcd9335_probe(struct wcd9335_codec * wcd)4864 static int wcd9335_probe(struct wcd9335_codec *wcd)
4865 {
4866 struct device *dev = wcd->dev;
4867
4868 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4869 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4870
4871 wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4872 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4873
4874 return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4875 wcd9335_slim_dais,
4876 ARRAY_SIZE(wcd9335_slim_dais));
4877 }
4878
4879 static const struct regmap_range_cfg wcd9335_ranges[] = {
4880 {
4881 .name = "WCD9335",
4882 .range_min = 0x0,
4883 .range_max = WCD9335_MAX_REGISTER,
4884 .selector_reg = WCD9335_SEL_REGISTER,
4885 .selector_mask = 0xff,
4886 .selector_shift = 0,
4887 .window_start = 0x800,
4888 .window_len = 0x100,
4889 },
4890 };
4891
wcd9335_is_volatile_register(struct device * dev,unsigned int reg)4892 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4893 {
4894 switch (reg) {
4895 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4896 case WCD9335_ANA_MBHC_RESULT_3:
4897 case WCD9335_ANA_MBHC_RESULT_2:
4898 case WCD9335_ANA_MBHC_RESULT_1:
4899 case WCD9335_ANA_MBHC_MECH:
4900 case WCD9335_ANA_MBHC_ELECT:
4901 case WCD9335_ANA_MBHC_ZDET:
4902 case WCD9335_ANA_MICB2:
4903 case WCD9335_ANA_RCO:
4904 case WCD9335_ANA_BIAS:
4905 return true;
4906 default:
4907 return false;
4908 }
4909 }
4910
4911 static const struct regmap_config wcd9335_regmap_config = {
4912 .reg_bits = 16,
4913 .val_bits = 8,
4914 .cache_type = REGCACHE_MAPLE,
4915 .max_register = WCD9335_MAX_REGISTER,
4916 .can_multi_write = true,
4917 .ranges = wcd9335_ranges,
4918 .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4919 .volatile_reg = wcd9335_is_volatile_register,
4920 };
4921
4922 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4923 {
4924 .name = "WCD9335-IFC-DEV",
4925 .range_min = 0x0,
4926 .range_max = WCD9335_MAX_REGISTER,
4927 .selector_reg = WCD9335_SEL_REGISTER,
4928 .selector_mask = 0xfff,
4929 .selector_shift = 0,
4930 .window_start = 0x800,
4931 .window_len = 0x400,
4932 },
4933 };
4934
4935 static const struct regmap_config wcd9335_ifc_regmap_config = {
4936 .reg_bits = 16,
4937 .val_bits = 8,
4938 .can_multi_write = true,
4939 .max_register = WCD9335_MAX_REGISTER,
4940 .ranges = wcd9335_ifc_ranges,
4941 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
4942 };
4943
4944 static const struct regmap_irq wcd9335_codec_irqs[] = {
4945 /* INTR_REG 0 */
4946 [WCD9335_IRQ_SLIMBUS] = {
4947 .reg_offset = 0,
4948 .mask = BIT(0),
4949 .type = {
4950 .type_reg_offset = 0,
4951 .types_supported = IRQ_TYPE_EDGE_BOTH,
4952 .type_reg_mask = BIT(0),
4953 },
4954 },
4955 };
4956
4957 static const unsigned int wcd9335_config_regs[] = {
4958 WCD9335_INTR_LEVEL0,
4959 };
4960
4961 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
4962 .name = "wcd9335_pin1_irq",
4963 .status_base = WCD9335_INTR_PIN1_STATUS0,
4964 .mask_base = WCD9335_INTR_PIN1_MASK0,
4965 .ack_base = WCD9335_INTR_PIN1_CLEAR0,
4966 .num_regs = 4,
4967 .irqs = wcd9335_codec_irqs,
4968 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
4969 .config_base = wcd9335_config_regs,
4970 .num_config_bases = ARRAY_SIZE(wcd9335_config_regs),
4971 .num_config_regs = 4,
4972 .set_type_config = regmap_irq_set_type_config_simple,
4973 };
4974
wcd9335_parse_dt(struct wcd9335_codec * wcd)4975 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
4976 {
4977 struct device *dev = wcd->dev;
4978 struct device_node *np = dev->of_node;
4979 int ret;
4980
4981 wcd->reset_gpio = of_get_named_gpio(np, "reset-gpios", 0);
4982 if (wcd->reset_gpio < 0)
4983 return dev_err_probe(dev, wcd->reset_gpio, "Reset GPIO missing from DT\n");
4984
4985 wcd->mclk = devm_clk_get(dev, "mclk");
4986 if (IS_ERR(wcd->mclk))
4987 return dev_err_probe(dev, PTR_ERR(wcd->mclk), "mclk not found\n");
4988
4989 wcd->native_clk = devm_clk_get(dev, "slimbus");
4990 if (IS_ERR(wcd->native_clk))
4991 return dev_err_probe(dev, PTR_ERR(wcd->native_clk), "slimbus clock not found\n");
4992
4993 wcd->supplies[0].supply = "vdd-buck";
4994 wcd->supplies[1].supply = "vdd-buck-sido";
4995 wcd->supplies[2].supply = "vdd-tx";
4996 wcd->supplies[3].supply = "vdd-rx";
4997 wcd->supplies[4].supply = "vdd-io";
4998
4999 ret = regulator_bulk_get(dev, WCD9335_MAX_SUPPLY, wcd->supplies);
5000 if (ret)
5001 return dev_err_probe(dev, ret, "Failed to get supplies\n");
5002
5003 return 0;
5004 }
5005
wcd9335_power_on_reset(struct wcd9335_codec * wcd)5006 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5007 {
5008 struct device *dev = wcd->dev;
5009 int ret;
5010
5011 ret = regulator_bulk_enable(WCD9335_MAX_SUPPLY, wcd->supplies);
5012 if (ret) {
5013 dev_err(dev, "Failed to get supplies: err = %d\n", ret);
5014 return ret;
5015 }
5016
5017 /*
5018 * For WCD9335, it takes about 600us for the Vout_A and
5019 * Vout_D to be ready after BUCK_SIDO is powered up.
5020 * SYS_RST_N shouldn't be pulled high during this time
5021 * Toggle the reset line to make sure the reset pulse is
5022 * correctly applied
5023 */
5024 usleep_range(600, 650);
5025
5026 gpio_direction_output(wcd->reset_gpio, 0);
5027 msleep(20);
5028 gpio_set_value(wcd->reset_gpio, 1);
5029 msleep(20);
5030
5031 return 0;
5032 }
5033
wcd9335_bring_up(struct wcd9335_codec * wcd)5034 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5035 {
5036 struct regmap *rm = wcd->regmap;
5037 int val, byte0;
5038
5039 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5040 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5041
5042 if ((val < 0) || (byte0 < 0)) {
5043 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5044 return -EINVAL;
5045 }
5046
5047 if (byte0 == 0x1) {
5048 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5049 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5050 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5051 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5052 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5053 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5054 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5055 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5056 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5057 } else {
5058 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5059 return -EINVAL;
5060 }
5061
5062 return 0;
5063 }
5064
wcd9335_irq_init(struct wcd9335_codec * wcd)5065 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5066 {
5067 int ret;
5068
5069 /*
5070 * INTR1 consists of all possible interrupt sources Ear OCP,
5071 * HPH OCP, MBHC, MAD, VBAT, and SVA
5072 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5073 */
5074 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5075 if (wcd->intr1 < 0)
5076 return dev_err_probe(wcd->dev, wcd->intr1,
5077 "Unable to configure IRQ\n");
5078
5079 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5080 IRQF_TRIGGER_HIGH, 0,
5081 &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5082 if (ret)
5083 return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n");
5084
5085 return 0;
5086 }
5087
wcd9335_slim_probe(struct slim_device * slim)5088 static int wcd9335_slim_probe(struct slim_device *slim)
5089 {
5090 struct device *dev = &slim->dev;
5091 struct wcd9335_codec *wcd;
5092 int ret;
5093
5094 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5095 if (!wcd)
5096 return -ENOMEM;
5097
5098 wcd->dev = dev;
5099 ret = wcd9335_parse_dt(wcd);
5100 if (ret)
5101 return ret;
5102
5103 ret = wcd9335_power_on_reset(wcd);
5104 if (ret)
5105 return ret;
5106
5107 dev_set_drvdata(dev, wcd);
5108
5109 return 0;
5110 }
5111
wcd9335_slim_status(struct slim_device * sdev,enum slim_device_status status)5112 static int wcd9335_slim_status(struct slim_device *sdev,
5113 enum slim_device_status status)
5114 {
5115 struct device *dev = &sdev->dev;
5116 struct device_node *ifc_dev_np;
5117 struct wcd9335_codec *wcd;
5118 int ret;
5119
5120 wcd = dev_get_drvdata(dev);
5121
5122 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5123 if (!ifc_dev_np) {
5124 dev_err(dev, "No Interface device found\n");
5125 return -EINVAL;
5126 }
5127
5128 wcd->slim = sdev;
5129 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5130 of_node_put(ifc_dev_np);
5131 if (!wcd->slim_ifc_dev) {
5132 dev_err(dev, "Unable to get SLIM Interface device\n");
5133 return -EINVAL;
5134 }
5135
5136 slim_get_logical_addr(wcd->slim_ifc_dev);
5137
5138 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5139 if (IS_ERR(wcd->regmap))
5140 return dev_err_probe(dev, PTR_ERR(wcd->regmap),
5141 "Failed to allocate slim register map\n");
5142
5143 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5144 &wcd9335_ifc_regmap_config);
5145 if (IS_ERR(wcd->if_regmap))
5146 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5147 "Failed to allocate ifc register map\n");
5148
5149 ret = wcd9335_bring_up(wcd);
5150 if (ret) {
5151 dev_err(dev, "Failed to bringup WCD9335\n");
5152 return ret;
5153 }
5154
5155 ret = wcd9335_irq_init(wcd);
5156 if (ret)
5157 return ret;
5158
5159 wcd9335_probe(wcd);
5160
5161 return 0;
5162 }
5163
5164 static const struct slim_device_id wcd9335_slim_id[] = {
5165 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5166 {}
5167 };
5168 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5169
5170 static struct slim_driver wcd9335_slim_driver = {
5171 .driver = {
5172 .name = "wcd9335-slim",
5173 },
5174 .probe = wcd9335_slim_probe,
5175 .device_status = wcd9335_slim_status,
5176 .id_table = wcd9335_slim_id,
5177 };
5178
5179 module_slim_driver(wcd9335_slim_driver);
5180 MODULE_DESCRIPTION("WCD9335 slim driver");
5181 MODULE_LICENSE("GPL v2");
5182