1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Analog Devices ADAU1373 Audio Codec drive
4 *
5 * Copyright 2011 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <[email protected]>
7 */
8
9 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/delay.h>
13 #include <linux/pm.h>
14 #include <linux/property.h>
15 #include <linux/i2c.h>
16 #include <linux/slab.h>
17
18 #include <sound/core.h>
19 #include <sound/pcm.h>
20 #include <sound/pcm_params.h>
21 #include <sound/tlv.h>
22 #include <sound/soc.h>
23
24 #include "adau1373.h"
25 #include "adau-utils.h"
26
27 struct adau1373_dai {
28 unsigned int clk_src;
29 unsigned int sysclk;
30 bool enable_src;
31 bool clock_provider;
32 };
33
34 enum adau1373_micbias_voltage {
35 ADAU1373_MICBIAS_2_9V,
36 ADAU1373_MICBIAS_2_2V,
37 ADAU1373_MICBIAS_2_6V,
38 ADAU1373_MICBIAS_1_8V,
39 };
40
41 #define ADAU1373_DRC_SIZE 13
42
43 struct adau1373 {
44 struct regmap *regmap;
45 struct adau1373_dai dais[3];
46
47 bool input_differential[4];
48 bool lineout_differential;
49 bool lineout_ground_sense;
50
51 unsigned int num_drc;
52 u8 drc_setting[3][ADAU1373_DRC_SIZE];
53
54 enum adau1373_micbias_voltage micbias1;
55 enum adau1373_micbias_voltage micbias2;
56 };
57
58 #define ADAU1373_INPUT_MODE 0x00
59 #define ADAU1373_AINL_CTRL(x) (0x01 + (x) * 2)
60 #define ADAU1373_AINR_CTRL(x) (0x02 + (x) * 2)
61 #define ADAU1373_LLINE_OUT(x) (0x9 + (x) * 2)
62 #define ADAU1373_RLINE_OUT(x) (0xa + (x) * 2)
63 #define ADAU1373_LSPK_OUT 0x0d
64 #define ADAU1373_RSPK_OUT 0x0e
65 #define ADAU1373_LHP_OUT 0x0f
66 #define ADAU1373_RHP_OUT 0x10
67 #define ADAU1373_ADC_GAIN 0x11
68 #define ADAU1373_LADC_MIXER 0x12
69 #define ADAU1373_RADC_MIXER 0x13
70 #define ADAU1373_LLINE1_MIX 0x14
71 #define ADAU1373_RLINE1_MIX 0x15
72 #define ADAU1373_LLINE2_MIX 0x16
73 #define ADAU1373_RLINE2_MIX 0x17
74 #define ADAU1373_LSPK_MIX 0x18
75 #define ADAU1373_RSPK_MIX 0x19
76 #define ADAU1373_LHP_MIX 0x1a
77 #define ADAU1373_RHP_MIX 0x1b
78 #define ADAU1373_EP_MIX 0x1c
79 #define ADAU1373_HP_CTRL 0x1d
80 #define ADAU1373_HP_CTRL2 0x1e
81 #define ADAU1373_LS_CTRL 0x1f
82 #define ADAU1373_EP_CTRL 0x21
83 #define ADAU1373_MICBIAS_CTRL1 0x22
84 #define ADAU1373_MICBIAS_CTRL2 0x23
85 #define ADAU1373_OUTPUT_CTRL 0x24
86 #define ADAU1373_PWDN_CTRL1 0x25
87 #define ADAU1373_PWDN_CTRL2 0x26
88 #define ADAU1373_PWDN_CTRL3 0x27
89 #define ADAU1373_DPLL_CTRL(x) (0x28 + (x) * 7)
90 #define ADAU1373_PLL_CTRL1(x) (0x29 + (x) * 7)
91 #define ADAU1373_PLL_CTRL2(x) (0x2a + (x) * 7)
92 #define ADAU1373_PLL_CTRL3(x) (0x2b + (x) * 7)
93 #define ADAU1373_PLL_CTRL4(x) (0x2c + (x) * 7)
94 #define ADAU1373_PLL_CTRL5(x) (0x2d + (x) * 7)
95 #define ADAU1373_PLL_CTRL6(x) (0x2e + (x) * 7)
96 #define ADAU1373_HEADDECT 0x36
97 #define ADAU1373_ADC_DAC_STATUS 0x37
98 #define ADAU1373_ADC_CTRL 0x3c
99 #define ADAU1373_DAI(x) (0x44 + (x))
100 #define ADAU1373_CLK_SRC_DIV(x) (0x40 + (x) * 2)
101 #define ADAU1373_BCLKDIV(x) (0x47 + (x))
102 #define ADAU1373_SRC_RATIOA(x) (0x4a + (x) * 2)
103 #define ADAU1373_SRC_RATIOB(x) (0x4b + (x) * 2)
104 #define ADAU1373_DEEMP_CTRL 0x50
105 #define ADAU1373_SRC_DAI_CTRL(x) (0x51 + (x))
106 #define ADAU1373_DIN_MIX_CTRL(x) (0x56 + (x))
107 #define ADAU1373_DOUT_MIX_CTRL(x) (0x5b + (x))
108 #define ADAU1373_DAI_PBL_VOL(x) (0x62 + (x) * 2)
109 #define ADAU1373_DAI_PBR_VOL(x) (0x63 + (x) * 2)
110 #define ADAU1373_DAI_RECL_VOL(x) (0x68 + (x) * 2)
111 #define ADAU1373_DAI_RECR_VOL(x) (0x69 + (x) * 2)
112 #define ADAU1373_DAC1_PBL_VOL 0x6e
113 #define ADAU1373_DAC1_PBR_VOL 0x6f
114 #define ADAU1373_DAC2_PBL_VOL 0x70
115 #define ADAU1373_DAC2_PBR_VOL 0x71
116 #define ADAU1373_ADC_RECL_VOL 0x72
117 #define ADAU1373_ADC_RECR_VOL 0x73
118 #define ADAU1373_DMIC_RECL_VOL 0x74
119 #define ADAU1373_DMIC_RECR_VOL 0x75
120 #define ADAU1373_VOL_GAIN1 0x76
121 #define ADAU1373_VOL_GAIN2 0x77
122 #define ADAU1373_VOL_GAIN3 0x78
123 #define ADAU1373_HPF_CTRL 0x7d
124 #define ADAU1373_BASS1 0x7e
125 #define ADAU1373_BASS2 0x7f
126 #define ADAU1373_DRC(x) (0x80 + (x) * 0x10)
127 #define ADAU1373_3D_CTRL1 0xc0
128 #define ADAU1373_3D_CTRL2 0xc1
129 #define ADAU1373_FDSP_SEL1 0xdc
130 #define ADAU1373_FDSP_SEL2 0xdd
131 #define ADAU1373_FDSP_SEL3 0xde
132 #define ADAU1373_FDSP_SEL4 0xdf
133 #define ADAU1373_DIGMICCTRL 0xe2
134 #define ADAU1373_DIGEN 0xeb
135 #define ADAU1373_SOFT_RESET 0xff
136
137
138 #define ADAU1373_PLL_CTRL6_DPLL_BYPASS BIT(1)
139 #define ADAU1373_PLL_CTRL6_PLL_EN BIT(0)
140
141 #define ADAU1373_DAI_INVERT_BCLK BIT(7)
142 #define ADAU1373_DAI_MASTER BIT(6)
143 #define ADAU1373_DAI_INVERT_LRCLK BIT(4)
144 #define ADAU1373_DAI_WLEN_16 0x0
145 #define ADAU1373_DAI_WLEN_20 0x4
146 #define ADAU1373_DAI_WLEN_24 0x8
147 #define ADAU1373_DAI_WLEN_32 0xc
148 #define ADAU1373_DAI_WLEN_MASK 0xc
149 #define ADAU1373_DAI_FORMAT_RIGHT_J 0x0
150 #define ADAU1373_DAI_FORMAT_LEFT_J 0x1
151 #define ADAU1373_DAI_FORMAT_I2S 0x2
152 #define ADAU1373_DAI_FORMAT_DSP 0x3
153
154 #define ADAU1373_BCLKDIV_SOURCE BIT(5)
155 #define ADAU1373_BCLKDIV_SR_MASK (0x07 << 2)
156 #define ADAU1373_BCLKDIV_BCLK_MASK 0x03
157 #define ADAU1373_BCLKDIV_32 0x03
158 #define ADAU1373_BCLKDIV_64 0x02
159 #define ADAU1373_BCLKDIV_128 0x01
160 #define ADAU1373_BCLKDIV_256 0x00
161
162 #define ADAU1373_ADC_CTRL_PEAK_DETECT BIT(0)
163 #define ADAU1373_ADC_CTRL_RESET BIT(1)
164 #define ADAU1373_ADC_CTRL_RESET_FORCE BIT(2)
165
166 #define ADAU1373_OUTPUT_CTRL_LDIFF BIT(3)
167 #define ADAU1373_OUTPUT_CTRL_LNFBEN BIT(2)
168
169 #define ADAU1373_PWDN_CTRL3_PWR_EN BIT(0)
170
171 #define ADAU1373_EP_CTRL_MICBIAS1_OFFSET 4
172 #define ADAU1373_EP_CTRL_MICBIAS2_OFFSET 2
173
174 static const struct reg_default adau1373_reg_defaults[] = {
175 { ADAU1373_INPUT_MODE, 0x00 },
176 { ADAU1373_AINL_CTRL(0), 0x00 },
177 { ADAU1373_AINR_CTRL(0), 0x00 },
178 { ADAU1373_AINL_CTRL(1), 0x00 },
179 { ADAU1373_AINR_CTRL(1), 0x00 },
180 { ADAU1373_AINL_CTRL(2), 0x00 },
181 { ADAU1373_AINR_CTRL(2), 0x00 },
182 { ADAU1373_AINL_CTRL(3), 0x00 },
183 { ADAU1373_AINR_CTRL(3), 0x00 },
184 { ADAU1373_LLINE_OUT(0), 0x00 },
185 { ADAU1373_RLINE_OUT(0), 0x00 },
186 { ADAU1373_LLINE_OUT(1), 0x00 },
187 { ADAU1373_RLINE_OUT(1), 0x00 },
188 { ADAU1373_LSPK_OUT, 0x00 },
189 { ADAU1373_RSPK_OUT, 0x00 },
190 { ADAU1373_LHP_OUT, 0x00 },
191 { ADAU1373_RHP_OUT, 0x00 },
192 { ADAU1373_ADC_GAIN, 0x00 },
193 { ADAU1373_LADC_MIXER, 0x00 },
194 { ADAU1373_RADC_MIXER, 0x00 },
195 { ADAU1373_LLINE1_MIX, 0x00 },
196 { ADAU1373_RLINE1_MIX, 0x00 },
197 { ADAU1373_LLINE2_MIX, 0x00 },
198 { ADAU1373_RLINE2_MIX, 0x00 },
199 { ADAU1373_LSPK_MIX, 0x00 },
200 { ADAU1373_RSPK_MIX, 0x00 },
201 { ADAU1373_LHP_MIX, 0x00 },
202 { ADAU1373_RHP_MIX, 0x00 },
203 { ADAU1373_EP_MIX, 0x00 },
204 { ADAU1373_HP_CTRL, 0x00 },
205 { ADAU1373_HP_CTRL2, 0x00 },
206 { ADAU1373_LS_CTRL, 0x00 },
207 { ADAU1373_EP_CTRL, 0x00 },
208 { ADAU1373_MICBIAS_CTRL1, 0x00 },
209 { ADAU1373_MICBIAS_CTRL2, 0x00 },
210 { ADAU1373_OUTPUT_CTRL, 0x00 },
211 { ADAU1373_PWDN_CTRL1, 0x00 },
212 { ADAU1373_PWDN_CTRL2, 0x00 },
213 { ADAU1373_PWDN_CTRL3, 0x00 },
214 { ADAU1373_DPLL_CTRL(0), 0x00 },
215 { ADAU1373_PLL_CTRL1(0), 0x00 },
216 { ADAU1373_PLL_CTRL2(0), 0x00 },
217 { ADAU1373_PLL_CTRL3(0), 0x00 },
218 { ADAU1373_PLL_CTRL4(0), 0x00 },
219 { ADAU1373_PLL_CTRL5(0), 0x00 },
220 { ADAU1373_PLL_CTRL6(0), 0x02 },
221 { ADAU1373_DPLL_CTRL(1), 0x00 },
222 { ADAU1373_PLL_CTRL1(1), 0x00 },
223 { ADAU1373_PLL_CTRL2(1), 0x00 },
224 { ADAU1373_PLL_CTRL3(1), 0x00 },
225 { ADAU1373_PLL_CTRL4(1), 0x00 },
226 { ADAU1373_PLL_CTRL5(1), 0x00 },
227 { ADAU1373_PLL_CTRL6(1), 0x02 },
228 { ADAU1373_HEADDECT, 0x00 },
229 { ADAU1373_ADC_CTRL, 0x00 },
230 { ADAU1373_CLK_SRC_DIV(0), 0x00 },
231 { ADAU1373_CLK_SRC_DIV(1), 0x00 },
232 { ADAU1373_DAI(0), 0x0a },
233 { ADAU1373_DAI(1), 0x0a },
234 { ADAU1373_DAI(2), 0x0a },
235 { ADAU1373_BCLKDIV(0), 0x00 },
236 { ADAU1373_BCLKDIV(1), 0x00 },
237 { ADAU1373_BCLKDIV(2), 0x00 },
238 { ADAU1373_SRC_RATIOA(0), 0x00 },
239 { ADAU1373_SRC_RATIOB(0), 0x00 },
240 { ADAU1373_SRC_RATIOA(1), 0x00 },
241 { ADAU1373_SRC_RATIOB(1), 0x00 },
242 { ADAU1373_SRC_RATIOA(2), 0x00 },
243 { ADAU1373_SRC_RATIOB(2), 0x00 },
244 { ADAU1373_DEEMP_CTRL, 0x00 },
245 { ADAU1373_SRC_DAI_CTRL(0), 0x08 },
246 { ADAU1373_SRC_DAI_CTRL(1), 0x08 },
247 { ADAU1373_SRC_DAI_CTRL(2), 0x08 },
248 { ADAU1373_DIN_MIX_CTRL(0), 0x00 },
249 { ADAU1373_DIN_MIX_CTRL(1), 0x00 },
250 { ADAU1373_DIN_MIX_CTRL(2), 0x00 },
251 { ADAU1373_DIN_MIX_CTRL(3), 0x00 },
252 { ADAU1373_DIN_MIX_CTRL(4), 0x00 },
253 { ADAU1373_DOUT_MIX_CTRL(0), 0x00 },
254 { ADAU1373_DOUT_MIX_CTRL(1), 0x00 },
255 { ADAU1373_DOUT_MIX_CTRL(2), 0x00 },
256 { ADAU1373_DOUT_MIX_CTRL(3), 0x00 },
257 { ADAU1373_DOUT_MIX_CTRL(4), 0x00 },
258 { ADAU1373_DAI_PBL_VOL(0), 0x00 },
259 { ADAU1373_DAI_PBR_VOL(0), 0x00 },
260 { ADAU1373_DAI_PBL_VOL(1), 0x00 },
261 { ADAU1373_DAI_PBR_VOL(1), 0x00 },
262 { ADAU1373_DAI_PBL_VOL(2), 0x00 },
263 { ADAU1373_DAI_PBR_VOL(2), 0x00 },
264 { ADAU1373_DAI_RECL_VOL(0), 0x00 },
265 { ADAU1373_DAI_RECR_VOL(0), 0x00 },
266 { ADAU1373_DAI_RECL_VOL(1), 0x00 },
267 { ADAU1373_DAI_RECR_VOL(1), 0x00 },
268 { ADAU1373_DAI_RECL_VOL(2), 0x00 },
269 { ADAU1373_DAI_RECR_VOL(2), 0x00 },
270 { ADAU1373_DAC1_PBL_VOL, 0x00 },
271 { ADAU1373_DAC1_PBR_VOL, 0x00 },
272 { ADAU1373_DAC2_PBL_VOL, 0x00 },
273 { ADAU1373_DAC2_PBR_VOL, 0x00 },
274 { ADAU1373_ADC_RECL_VOL, 0x00 },
275 { ADAU1373_ADC_RECR_VOL, 0x00 },
276 { ADAU1373_DMIC_RECL_VOL, 0x00 },
277 { ADAU1373_DMIC_RECR_VOL, 0x00 },
278 { ADAU1373_VOL_GAIN1, 0x00 },
279 { ADAU1373_VOL_GAIN2, 0x00 },
280 { ADAU1373_VOL_GAIN3, 0x00 },
281 { ADAU1373_HPF_CTRL, 0x00 },
282 { ADAU1373_BASS1, 0x00 },
283 { ADAU1373_BASS2, 0x00 },
284 { ADAU1373_DRC(0) + 0x0, 0x78 },
285 { ADAU1373_DRC(0) + 0x1, 0x18 },
286 { ADAU1373_DRC(0) + 0x2, 0x00 },
287 { ADAU1373_DRC(0) + 0x3, 0x00 },
288 { ADAU1373_DRC(0) + 0x4, 0x00 },
289 { ADAU1373_DRC(0) + 0x5, 0xc0 },
290 { ADAU1373_DRC(0) + 0x6, 0x00 },
291 { ADAU1373_DRC(0) + 0x7, 0x00 },
292 { ADAU1373_DRC(0) + 0x8, 0x00 },
293 { ADAU1373_DRC(0) + 0x9, 0xc0 },
294 { ADAU1373_DRC(0) + 0xa, 0x88 },
295 { ADAU1373_DRC(0) + 0xb, 0x7a },
296 { ADAU1373_DRC(0) + 0xc, 0xdf },
297 { ADAU1373_DRC(0) + 0xd, 0x20 },
298 { ADAU1373_DRC(0) + 0xe, 0x00 },
299 { ADAU1373_DRC(0) + 0xf, 0x00 },
300 { ADAU1373_DRC(1) + 0x0, 0x78 },
301 { ADAU1373_DRC(1) + 0x1, 0x18 },
302 { ADAU1373_DRC(1) + 0x2, 0x00 },
303 { ADAU1373_DRC(1) + 0x3, 0x00 },
304 { ADAU1373_DRC(1) + 0x4, 0x00 },
305 { ADAU1373_DRC(1) + 0x5, 0xc0 },
306 { ADAU1373_DRC(1) + 0x6, 0x00 },
307 { ADAU1373_DRC(1) + 0x7, 0x00 },
308 { ADAU1373_DRC(1) + 0x8, 0x00 },
309 { ADAU1373_DRC(1) + 0x9, 0xc0 },
310 { ADAU1373_DRC(1) + 0xa, 0x88 },
311 { ADAU1373_DRC(1) + 0xb, 0x7a },
312 { ADAU1373_DRC(1) + 0xc, 0xdf },
313 { ADAU1373_DRC(1) + 0xd, 0x20 },
314 { ADAU1373_DRC(1) + 0xe, 0x00 },
315 { ADAU1373_DRC(1) + 0xf, 0x00 },
316 { ADAU1373_DRC(2) + 0x0, 0x78 },
317 { ADAU1373_DRC(2) + 0x1, 0x18 },
318 { ADAU1373_DRC(2) + 0x2, 0x00 },
319 { ADAU1373_DRC(2) + 0x3, 0x00 },
320 { ADAU1373_DRC(2) + 0x4, 0x00 },
321 { ADAU1373_DRC(2) + 0x5, 0xc0 },
322 { ADAU1373_DRC(2) + 0x6, 0x00 },
323 { ADAU1373_DRC(2) + 0x7, 0x00 },
324 { ADAU1373_DRC(2) + 0x8, 0x00 },
325 { ADAU1373_DRC(2) + 0x9, 0xc0 },
326 { ADAU1373_DRC(2) + 0xa, 0x88 },
327 { ADAU1373_DRC(2) + 0xb, 0x7a },
328 { ADAU1373_DRC(2) + 0xc, 0xdf },
329 { ADAU1373_DRC(2) + 0xd, 0x20 },
330 { ADAU1373_DRC(2) + 0xe, 0x00 },
331 { ADAU1373_DRC(2) + 0xf, 0x00 },
332 { ADAU1373_3D_CTRL1, 0x00 },
333 { ADAU1373_3D_CTRL2, 0x00 },
334 { ADAU1373_FDSP_SEL1, 0x00 },
335 { ADAU1373_FDSP_SEL2, 0x00 },
336 { ADAU1373_FDSP_SEL2, 0x00 },
337 { ADAU1373_FDSP_SEL4, 0x00 },
338 { ADAU1373_DIGMICCTRL, 0x00 },
339 { ADAU1373_DIGEN, 0x00 },
340 };
341
342 static const DECLARE_TLV_DB_RANGE(adau1373_out_tlv,
343 0, 7, TLV_DB_SCALE_ITEM(-7900, 400, 1),
344 8, 15, TLV_DB_SCALE_ITEM(-4700, 300, 0),
345 16, 23, TLV_DB_SCALE_ITEM(-2300, 200, 0),
346 24, 31, TLV_DB_SCALE_ITEM(-700, 100, 0)
347 );
348
349 static const DECLARE_TLV_DB_MINMAX(adau1373_digital_tlv, -9563, 0);
350 static const DECLARE_TLV_DB_SCALE(adau1373_in_pga_tlv, -1300, 100, 1);
351 static const DECLARE_TLV_DB_SCALE(adau1373_ep_tlv, -600, 600, 1);
352
353 static const DECLARE_TLV_DB_SCALE(adau1373_input_boost_tlv, 0, 2000, 0);
354 static const DECLARE_TLV_DB_SCALE(adau1373_gain_boost_tlv, 0, 600, 0);
355 static const DECLARE_TLV_DB_SCALE(adau1373_speaker_boost_tlv, 1200, 600, 0);
356
357 static const char *adau1373_fdsp_sel_text[] = {
358 "None",
359 "Channel 1",
360 "Channel 2",
361 "Channel 3",
362 "Channel 4",
363 "Channel 5",
364 };
365
366 static SOC_ENUM_SINGLE_DECL(adau1373_drc1_channel_enum,
367 ADAU1373_FDSP_SEL1, 4, adau1373_fdsp_sel_text);
368 static SOC_ENUM_SINGLE_DECL(adau1373_drc2_channel_enum,
369 ADAU1373_FDSP_SEL1, 0, adau1373_fdsp_sel_text);
370 static SOC_ENUM_SINGLE_DECL(adau1373_drc3_channel_enum,
371 ADAU1373_FDSP_SEL2, 0, adau1373_fdsp_sel_text);
372 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_channel_enum,
373 ADAU1373_FDSP_SEL3, 0, adau1373_fdsp_sel_text);
374 static SOC_ENUM_SINGLE_DECL(adau1373_bass_channel_enum,
375 ADAU1373_FDSP_SEL4, 4, adau1373_fdsp_sel_text);
376
377 static const char *adau1373_hpf_cutoff_text[] = {
378 "3.7Hz", "50Hz", "100Hz", "150Hz", "200Hz", "250Hz", "300Hz", "350Hz",
379 "400Hz", "450Hz", "500Hz", "550Hz", "600Hz", "650Hz", "700Hz", "750Hz",
380 "800Hz",
381 };
382
383 static SOC_ENUM_SINGLE_DECL(adau1373_hpf_cutoff_enum,
384 ADAU1373_HPF_CTRL, 3, adau1373_hpf_cutoff_text);
385
386 static const char *adau1373_bass_lpf_cutoff_text[] = {
387 "801Hz", "1001Hz",
388 };
389
390 static const char *adau1373_bass_clip_level_text[] = {
391 "0.125", "0.250", "0.370", "0.500", "0.625", "0.750", "0.875",
392 };
393
394 static const unsigned int adau1373_bass_clip_level_values[] = {
395 1, 2, 3, 4, 5, 6, 7,
396 };
397
398 static const char *adau1373_bass_hpf_cutoff_text[] = {
399 "158Hz", "232Hz", "347Hz", "520Hz",
400 };
401
402 static const DECLARE_TLV_DB_RANGE(adau1373_bass_tlv,
403 0, 2, TLV_DB_SCALE_ITEM(-600, 600, 1),
404 3, 4, TLV_DB_SCALE_ITEM(950, 250, 0),
405 5, 7, TLV_DB_SCALE_ITEM(1400, 150, 0)
406 );
407
408 static SOC_ENUM_SINGLE_DECL(adau1373_bass_lpf_cutoff_enum,
409 ADAU1373_BASS1, 5, adau1373_bass_lpf_cutoff_text);
410
411 static SOC_VALUE_ENUM_SINGLE_DECL(adau1373_bass_clip_level_enum,
412 ADAU1373_BASS1, 2, 7, adau1373_bass_clip_level_text,
413 adau1373_bass_clip_level_values);
414
415 static SOC_ENUM_SINGLE_DECL(adau1373_bass_hpf_cutoff_enum,
416 ADAU1373_BASS1, 0, adau1373_bass_hpf_cutoff_text);
417
418 static const char *adau1373_3d_level_text[] = {
419 "0%", "6.67%", "13.33%", "20%", "26.67%", "33.33%",
420 "40%", "46.67%", "53.33%", "60%", "66.67%", "73.33%",
421 "80%", "86.67", "99.33%", "100%"
422 };
423
424 static const char *adau1373_3d_cutoff_text[] = {
425 "No 3D", "0.03125 fs", "0.04583 fs", "0.075 fs", "0.11458 fs",
426 "0.16875 fs", "0.27083 fs"
427 };
428
429 static SOC_ENUM_SINGLE_DECL(adau1373_3d_level_enum,
430 ADAU1373_3D_CTRL1, 4, adau1373_3d_level_text);
431 static SOC_ENUM_SINGLE_DECL(adau1373_3d_cutoff_enum,
432 ADAU1373_3D_CTRL1, 0, adau1373_3d_cutoff_text);
433
434 static const DECLARE_TLV_DB_RANGE(adau1373_3d_tlv,
435 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
436 1, 7, TLV_DB_LINEAR_ITEM(-1800, -120)
437 );
438
439 static const char *adau1373_lr_mux_text[] = {
440 "Mute",
441 "Right Channel (L+R)",
442 "Left Channel (L+R)",
443 "Stereo",
444 };
445
446 static SOC_ENUM_SINGLE_DECL(adau1373_lineout1_lr_mux_enum,
447 ADAU1373_OUTPUT_CTRL, 4, adau1373_lr_mux_text);
448 static SOC_ENUM_SINGLE_DECL(adau1373_lineout2_lr_mux_enum,
449 ADAU1373_OUTPUT_CTRL, 6, adau1373_lr_mux_text);
450 static SOC_ENUM_SINGLE_DECL(adau1373_speaker_lr_mux_enum,
451 ADAU1373_LS_CTRL, 4, adau1373_lr_mux_text);
452
453 static const struct snd_kcontrol_new adau1373_controls[] = {
454 SOC_DOUBLE_R_TLV("AIF1 Capture Volume", ADAU1373_DAI_RECL_VOL(0),
455 ADAU1373_DAI_RECR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
456 SOC_DOUBLE_R_TLV("AIF2 Capture Volume", ADAU1373_DAI_RECL_VOL(1),
457 ADAU1373_DAI_RECR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
458 SOC_DOUBLE_R_TLV("AIF3 Capture Volume", ADAU1373_DAI_RECL_VOL(2),
459 ADAU1373_DAI_RECR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
460
461 SOC_DOUBLE_R_TLV("ADC Capture Volume", ADAU1373_ADC_RECL_VOL,
462 ADAU1373_ADC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
463 SOC_DOUBLE_R_TLV("DMIC Capture Volume", ADAU1373_DMIC_RECL_VOL,
464 ADAU1373_DMIC_RECR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
465
466 SOC_DOUBLE_R_TLV("AIF1 Playback Volume", ADAU1373_DAI_PBL_VOL(0),
467 ADAU1373_DAI_PBR_VOL(0), 0, 0xff, 1, adau1373_digital_tlv),
468 SOC_DOUBLE_R_TLV("AIF2 Playback Volume", ADAU1373_DAI_PBL_VOL(1),
469 ADAU1373_DAI_PBR_VOL(1), 0, 0xff, 1, adau1373_digital_tlv),
470 SOC_DOUBLE_R_TLV("AIF3 Playback Volume", ADAU1373_DAI_PBL_VOL(2),
471 ADAU1373_DAI_PBR_VOL(2), 0, 0xff, 1, adau1373_digital_tlv),
472
473 SOC_DOUBLE_R_TLV("DAC1 Playback Volume", ADAU1373_DAC1_PBL_VOL,
474 ADAU1373_DAC1_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
475 SOC_DOUBLE_R_TLV("DAC2 Playback Volume", ADAU1373_DAC2_PBL_VOL,
476 ADAU1373_DAC2_PBR_VOL, 0, 0xff, 1, adau1373_digital_tlv),
477
478 SOC_DOUBLE_R_TLV("Lineout1 Playback Volume", ADAU1373_LLINE_OUT(0),
479 ADAU1373_RLINE_OUT(0), 0, 0x1f, 0, adau1373_out_tlv),
480 SOC_DOUBLE_R_TLV("Speaker Playback Volume", ADAU1373_LSPK_OUT,
481 ADAU1373_RSPK_OUT, 0, 0x1f, 0, adau1373_out_tlv),
482 SOC_DOUBLE_R_TLV("Headphone Playback Volume", ADAU1373_LHP_OUT,
483 ADAU1373_RHP_OUT, 0, 0x1f, 0, adau1373_out_tlv),
484
485 SOC_DOUBLE_R_TLV("Input 1 Capture Volume", ADAU1373_AINL_CTRL(0),
486 ADAU1373_AINR_CTRL(0), 0, 0x1f, 0, adau1373_in_pga_tlv),
487 SOC_DOUBLE_R_TLV("Input 2 Capture Volume", ADAU1373_AINL_CTRL(1),
488 ADAU1373_AINR_CTRL(1), 0, 0x1f, 0, adau1373_in_pga_tlv),
489 SOC_DOUBLE_R_TLV("Input 3 Capture Volume", ADAU1373_AINL_CTRL(2),
490 ADAU1373_AINR_CTRL(2), 0, 0x1f, 0, adau1373_in_pga_tlv),
491 SOC_DOUBLE_R_TLV("Input 4 Capture Volume", ADAU1373_AINL_CTRL(3),
492 ADAU1373_AINR_CTRL(3), 0, 0x1f, 0, adau1373_in_pga_tlv),
493
494 SOC_SINGLE_TLV("Earpiece Playback Volume", ADAU1373_EP_CTRL, 0, 3, 0,
495 adau1373_ep_tlv),
496
497 SOC_DOUBLE_TLV("AIF3 Boost Playback Volume", ADAU1373_VOL_GAIN1, 4, 5,
498 1, 0, adau1373_gain_boost_tlv),
499 SOC_DOUBLE_TLV("AIF2 Boost Playback Volume", ADAU1373_VOL_GAIN1, 2, 3,
500 1, 0, adau1373_gain_boost_tlv),
501 SOC_DOUBLE_TLV("AIF1 Boost Playback Volume", ADAU1373_VOL_GAIN1, 0, 1,
502 1, 0, adau1373_gain_boost_tlv),
503 SOC_DOUBLE_TLV("AIF3 Boost Capture Volume", ADAU1373_VOL_GAIN2, 4, 5,
504 1, 0, adau1373_gain_boost_tlv),
505 SOC_DOUBLE_TLV("AIF2 Boost Capture Volume", ADAU1373_VOL_GAIN2, 2, 3,
506 1, 0, adau1373_gain_boost_tlv),
507 SOC_DOUBLE_TLV("AIF1 Boost Capture Volume", ADAU1373_VOL_GAIN2, 0, 1,
508 1, 0, adau1373_gain_boost_tlv),
509 SOC_DOUBLE_TLV("DMIC Boost Capture Volume", ADAU1373_VOL_GAIN3, 6, 7,
510 1, 0, adau1373_gain_boost_tlv),
511 SOC_DOUBLE_TLV("ADC Boost Capture Volume", ADAU1373_VOL_GAIN3, 4, 5,
512 1, 0, adau1373_gain_boost_tlv),
513 SOC_DOUBLE_TLV("DAC2 Boost Playback Volume", ADAU1373_VOL_GAIN3, 2, 3,
514 1, 0, adau1373_gain_boost_tlv),
515 SOC_DOUBLE_TLV("DAC1 Boost Playback Volume", ADAU1373_VOL_GAIN3, 0, 1,
516 1, 0, adau1373_gain_boost_tlv),
517
518 SOC_DOUBLE_TLV("Input 1 Boost Capture Volume", ADAU1373_ADC_GAIN, 0, 4,
519 1, 0, adau1373_input_boost_tlv),
520 SOC_DOUBLE_TLV("Input 2 Boost Capture Volume", ADAU1373_ADC_GAIN, 1, 5,
521 1, 0, adau1373_input_boost_tlv),
522 SOC_DOUBLE_TLV("Input 3 Boost Capture Volume", ADAU1373_ADC_GAIN, 2, 6,
523 1, 0, adau1373_input_boost_tlv),
524 SOC_DOUBLE_TLV("Input 4 Boost Capture Volume", ADAU1373_ADC_GAIN, 3, 7,
525 1, 0, adau1373_input_boost_tlv),
526
527 SOC_DOUBLE_TLV("Speaker Boost Playback Volume", ADAU1373_LS_CTRL, 2, 3,
528 1, 0, adau1373_speaker_boost_tlv),
529
530 SOC_ENUM("Lineout1 LR Mux", adau1373_lineout1_lr_mux_enum),
531 SOC_ENUM("Speaker LR Mux", adau1373_speaker_lr_mux_enum),
532
533 SOC_ENUM("HPF Cutoff", adau1373_hpf_cutoff_enum),
534 SOC_DOUBLE("HPF Switch", ADAU1373_HPF_CTRL, 1, 0, 1, 0),
535 SOC_ENUM("HPF Channel", adau1373_hpf_channel_enum),
536
537 SOC_ENUM("Bass HPF Cutoff", adau1373_bass_hpf_cutoff_enum),
538 SOC_ENUM("Bass Clip Level Threshold", adau1373_bass_clip_level_enum),
539 SOC_ENUM("Bass LPF Cutoff", adau1373_bass_lpf_cutoff_enum),
540 SOC_DOUBLE("Bass Playback Switch", ADAU1373_BASS2, 0, 1, 1, 0),
541 SOC_SINGLE_TLV("Bass Playback Volume", ADAU1373_BASS2, 2, 7, 0,
542 adau1373_bass_tlv),
543 SOC_ENUM("Bass Channel", adau1373_bass_channel_enum),
544
545 SOC_ENUM("3D Freq", adau1373_3d_cutoff_enum),
546 SOC_ENUM("3D Level", adau1373_3d_level_enum),
547 SOC_SINGLE("3D Playback Switch", ADAU1373_3D_CTRL2, 0, 1, 0),
548 SOC_SINGLE_TLV("3D Playback Volume", ADAU1373_3D_CTRL2, 2, 7, 0,
549 adau1373_3d_tlv),
550 SOC_ENUM("3D Channel", adau1373_bass_channel_enum),
551
552 SOC_SINGLE("Zero Cross Switch", ADAU1373_PWDN_CTRL3, 7, 1, 0),
553 };
554
555 static const struct snd_kcontrol_new adau1373_lineout2_controls[] = {
556 SOC_DOUBLE_R_TLV("Lineout2 Playback Volume", ADAU1373_LLINE_OUT(1),
557 ADAU1373_RLINE_OUT(1), 0, 0x1f, 0, adau1373_out_tlv),
558 SOC_ENUM("Lineout2 LR Mux", adau1373_lineout2_lr_mux_enum),
559 };
560
561 static const struct snd_kcontrol_new adau1373_drc_controls[] = {
562 SOC_ENUM("DRC1 Channel", adau1373_drc1_channel_enum),
563 SOC_ENUM("DRC2 Channel", adau1373_drc2_channel_enum),
564 SOC_ENUM("DRC3 Channel", adau1373_drc3_channel_enum),
565 };
566
adau1373_pll_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)567 static int adau1373_pll_event(struct snd_soc_dapm_widget *w,
568 struct snd_kcontrol *kcontrol, int event)
569 {
570 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
571 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
572 unsigned int pll_id = w->name[3] - '1';
573 unsigned int val;
574
575 if (SND_SOC_DAPM_EVENT_ON(event))
576 val = ADAU1373_PLL_CTRL6_PLL_EN;
577 else
578 val = 0;
579
580 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
581 ADAU1373_PLL_CTRL6_PLL_EN, val);
582
583 if (SND_SOC_DAPM_EVENT_ON(event))
584 mdelay(5);
585
586 return 0;
587 }
588
589 static const char *adau1373_decimator_text[] = {
590 "ADC",
591 "DMIC1",
592 };
593
594 static SOC_ENUM_SINGLE_VIRT_DECL(adau1373_decimator_enum,
595 adau1373_decimator_text);
596
597 static const struct snd_kcontrol_new adau1373_decimator_mux =
598 SOC_DAPM_ENUM("Decimator Mux", adau1373_decimator_enum);
599
600 static const struct snd_kcontrol_new adau1373_left_adc_mixer_controls[] = {
601 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_LADC_MIXER, 4, 1, 0),
602 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_LADC_MIXER, 3, 1, 0),
603 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_LADC_MIXER, 2, 1, 0),
604 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_LADC_MIXER, 1, 1, 0),
605 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_LADC_MIXER, 0, 1, 0),
606 };
607
608 static const struct snd_kcontrol_new adau1373_right_adc_mixer_controls[] = {
609 SOC_DAPM_SINGLE("DAC1 Switch", ADAU1373_RADC_MIXER, 4, 1, 0),
610 SOC_DAPM_SINGLE("Input 4 Switch", ADAU1373_RADC_MIXER, 3, 1, 0),
611 SOC_DAPM_SINGLE("Input 3 Switch", ADAU1373_RADC_MIXER, 2, 1, 0),
612 SOC_DAPM_SINGLE("Input 2 Switch", ADAU1373_RADC_MIXER, 1, 1, 0),
613 SOC_DAPM_SINGLE("Input 1 Switch", ADAU1373_RADC_MIXER, 0, 1, 0),
614 };
615
616 #define DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(_name, _reg) \
617 const struct snd_kcontrol_new _name[] = { \
618 SOC_DAPM_SINGLE("Left DAC2 Switch", _reg, 7, 1, 0), \
619 SOC_DAPM_SINGLE("Right DAC2 Switch", _reg, 6, 1, 0), \
620 SOC_DAPM_SINGLE("Left DAC1 Switch", _reg, 5, 1, 0), \
621 SOC_DAPM_SINGLE("Right DAC1 Switch", _reg, 4, 1, 0), \
622 SOC_DAPM_SINGLE("Input 4 Bypass Switch", _reg, 3, 1, 0), \
623 SOC_DAPM_SINGLE("Input 3 Bypass Switch", _reg, 2, 1, 0), \
624 SOC_DAPM_SINGLE("Input 2 Bypass Switch", _reg, 1, 1, 0), \
625 SOC_DAPM_SINGLE("Input 1 Bypass Switch", _reg, 0, 1, 0), \
626 }
627
628 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line1_mixer_controls,
629 ADAU1373_LLINE1_MIX);
630 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line1_mixer_controls,
631 ADAU1373_RLINE1_MIX);
632 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_line2_mixer_controls,
633 ADAU1373_LLINE2_MIX);
634 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_line2_mixer_controls,
635 ADAU1373_RLINE2_MIX);
636 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_left_spk_mixer_controls,
637 ADAU1373_LSPK_MIX);
638 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_right_spk_mixer_controls,
639 ADAU1373_RSPK_MIX);
640 static DECLARE_ADAU1373_OUTPUT_MIXER_CTRLS(adau1373_ep_mixer_controls,
641 ADAU1373_EP_MIX);
642
643 static const struct snd_kcontrol_new adau1373_left_hp_mixer_controls[] = {
644 SOC_DAPM_SINGLE("Left DAC1 Switch", ADAU1373_LHP_MIX, 5, 1, 0),
645 SOC_DAPM_SINGLE("Left DAC2 Switch", ADAU1373_LHP_MIX, 4, 1, 0),
646 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_LHP_MIX, 3, 1, 0),
647 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_LHP_MIX, 2, 1, 0),
648 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_LHP_MIX, 1, 1, 0),
649 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_LHP_MIX, 0, 1, 0),
650 };
651
652 static const struct snd_kcontrol_new adau1373_right_hp_mixer_controls[] = {
653 SOC_DAPM_SINGLE("Right DAC1 Switch", ADAU1373_RHP_MIX, 5, 1, 0),
654 SOC_DAPM_SINGLE("Right DAC2 Switch", ADAU1373_RHP_MIX, 4, 1, 0),
655 SOC_DAPM_SINGLE("Input 4 Bypass Switch", ADAU1373_RHP_MIX, 3, 1, 0),
656 SOC_DAPM_SINGLE("Input 3 Bypass Switch", ADAU1373_RHP_MIX, 2, 1, 0),
657 SOC_DAPM_SINGLE("Input 2 Bypass Switch", ADAU1373_RHP_MIX, 1, 1, 0),
658 SOC_DAPM_SINGLE("Input 1 Bypass Switch", ADAU1373_RHP_MIX, 0, 1, 0),
659 };
660
661 #define DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(_name, _reg) \
662 const struct snd_kcontrol_new _name[] = { \
663 SOC_DAPM_SINGLE("DMIC2 Swapped Switch", _reg, 6, 1, 0), \
664 SOC_DAPM_SINGLE("DMIC2 Switch", _reg, 5, 1, 0), \
665 SOC_DAPM_SINGLE("ADC/DMIC1 Swapped Switch", _reg, 4, 1, 0), \
666 SOC_DAPM_SINGLE("ADC/DMIC1 Switch", _reg, 3, 1, 0), \
667 SOC_DAPM_SINGLE("AIF3 Switch", _reg, 2, 1, 0), \
668 SOC_DAPM_SINGLE("AIF2 Switch", _reg, 1, 1, 0), \
669 SOC_DAPM_SINGLE("AIF1 Switch", _reg, 0, 1, 0), \
670 }
671
672 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel1_mixer_controls,
673 ADAU1373_DIN_MIX_CTRL(0));
674 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel2_mixer_controls,
675 ADAU1373_DIN_MIX_CTRL(1));
676 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel3_mixer_controls,
677 ADAU1373_DIN_MIX_CTRL(2));
678 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel4_mixer_controls,
679 ADAU1373_DIN_MIX_CTRL(3));
680 static DECLARE_ADAU1373_DSP_CHANNEL_MIXER_CTRLS(adau1373_dsp_channel5_mixer_controls,
681 ADAU1373_DIN_MIX_CTRL(4));
682
683 #define DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(_name, _reg) \
684 const struct snd_kcontrol_new _name[] = { \
685 SOC_DAPM_SINGLE("DSP Channel5 Switch", _reg, 4, 1, 0), \
686 SOC_DAPM_SINGLE("DSP Channel4 Switch", _reg, 3, 1, 0), \
687 SOC_DAPM_SINGLE("DSP Channel3 Switch", _reg, 2, 1, 0), \
688 SOC_DAPM_SINGLE("DSP Channel2 Switch", _reg, 1, 1, 0), \
689 SOC_DAPM_SINGLE("DSP Channel1 Switch", _reg, 0, 1, 0), \
690 }
691
692 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif1_mixer_controls,
693 ADAU1373_DOUT_MIX_CTRL(0));
694 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif2_mixer_controls,
695 ADAU1373_DOUT_MIX_CTRL(1));
696 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_aif3_mixer_controls,
697 ADAU1373_DOUT_MIX_CTRL(2));
698 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac1_mixer_controls,
699 ADAU1373_DOUT_MIX_CTRL(3));
700 static DECLARE_ADAU1373_DSP_OUTPUT_MIXER_CTRLS(adau1373_dac2_mixer_controls,
701 ADAU1373_DOUT_MIX_CTRL(4));
702
703 static const struct snd_soc_dapm_widget adau1373_dapm_widgets[] = {
704 /* Datasheet claims Left ADC is bit 6 and Right ADC is bit 7, but that
705 * doesn't seem to be the case. */
706 SND_SOC_DAPM_ADC("Left ADC", NULL, ADAU1373_PWDN_CTRL1, 7, 0),
707 SND_SOC_DAPM_ADC("Right ADC", NULL, ADAU1373_PWDN_CTRL1, 6, 0),
708
709 SND_SOC_DAPM_ADC("DMIC1", NULL, ADAU1373_DIGMICCTRL, 0, 0),
710 SND_SOC_DAPM_ADC("DMIC2", NULL, ADAU1373_DIGMICCTRL, 2, 0),
711
712 SND_SOC_DAPM_MUX("Decimator Mux", SND_SOC_NOPM, 0, 0,
713 &adau1373_decimator_mux),
714
715 SND_SOC_DAPM_SUPPLY("MICBIAS2", ADAU1373_PWDN_CTRL1, 5, 0, NULL, 0),
716 SND_SOC_DAPM_SUPPLY("MICBIAS1", ADAU1373_PWDN_CTRL1, 4, 0, NULL, 0),
717
718 SND_SOC_DAPM_PGA("IN4PGA", ADAU1373_PWDN_CTRL1, 3, 0, NULL, 0),
719 SND_SOC_DAPM_PGA("IN3PGA", ADAU1373_PWDN_CTRL1, 2, 0, NULL, 0),
720 SND_SOC_DAPM_PGA("IN2PGA", ADAU1373_PWDN_CTRL1, 1, 0, NULL, 0),
721 SND_SOC_DAPM_PGA("IN1PGA", ADAU1373_PWDN_CTRL1, 0, 0, NULL, 0),
722
723 SND_SOC_DAPM_DAC("Left DAC2", NULL, ADAU1373_PWDN_CTRL2, 7, 0),
724 SND_SOC_DAPM_DAC("Right DAC2", NULL, ADAU1373_PWDN_CTRL2, 6, 0),
725 SND_SOC_DAPM_DAC("Left DAC1", NULL, ADAU1373_PWDN_CTRL2, 5, 0),
726 SND_SOC_DAPM_DAC("Right DAC1", NULL, ADAU1373_PWDN_CTRL2, 4, 0),
727
728 SOC_MIXER_ARRAY("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
729 adau1373_left_adc_mixer_controls),
730 SOC_MIXER_ARRAY("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
731 adau1373_right_adc_mixer_controls),
732
733 SOC_MIXER_ARRAY("Left Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 3, 0,
734 adau1373_left_line2_mixer_controls),
735 SOC_MIXER_ARRAY("Right Lineout2 Mixer", ADAU1373_PWDN_CTRL2, 2, 0,
736 adau1373_right_line2_mixer_controls),
737 SOC_MIXER_ARRAY("Left Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 1, 0,
738 adau1373_left_line1_mixer_controls),
739 SOC_MIXER_ARRAY("Right Lineout1 Mixer", ADAU1373_PWDN_CTRL2, 0, 0,
740 adau1373_right_line1_mixer_controls),
741
742 SOC_MIXER_ARRAY("Earpiece Mixer", ADAU1373_PWDN_CTRL3, 4, 0,
743 adau1373_ep_mixer_controls),
744 SOC_MIXER_ARRAY("Left Speaker Mixer", ADAU1373_PWDN_CTRL3, 3, 0,
745 adau1373_left_spk_mixer_controls),
746 SOC_MIXER_ARRAY("Right Speaker Mixer", ADAU1373_PWDN_CTRL3, 2, 0,
747 adau1373_right_spk_mixer_controls),
748 SOC_MIXER_ARRAY("Left Headphone Mixer", SND_SOC_NOPM, 0, 0,
749 adau1373_left_hp_mixer_controls),
750 SOC_MIXER_ARRAY("Right Headphone Mixer", SND_SOC_NOPM, 0, 0,
751 adau1373_right_hp_mixer_controls),
752 SND_SOC_DAPM_SUPPLY("Headphone Enable", ADAU1373_PWDN_CTRL3, 1, 0,
753 NULL, 0),
754
755 SND_SOC_DAPM_SUPPLY("AIF1 CLK", ADAU1373_SRC_DAI_CTRL(0), 0, 0,
756 NULL, 0),
757 SND_SOC_DAPM_SUPPLY("AIF2 CLK", ADAU1373_SRC_DAI_CTRL(1), 0, 0,
758 NULL, 0),
759 SND_SOC_DAPM_SUPPLY("AIF3 CLK", ADAU1373_SRC_DAI_CTRL(2), 0, 0,
760 NULL, 0),
761 SND_SOC_DAPM_SUPPLY("AIF1 IN SRC", ADAU1373_SRC_DAI_CTRL(0), 2, 0,
762 NULL, 0),
763 SND_SOC_DAPM_SUPPLY("AIF1 OUT SRC", ADAU1373_SRC_DAI_CTRL(0), 1, 0,
764 NULL, 0),
765 SND_SOC_DAPM_SUPPLY("AIF2 IN SRC", ADAU1373_SRC_DAI_CTRL(1), 2, 0,
766 NULL, 0),
767 SND_SOC_DAPM_SUPPLY("AIF2 OUT SRC", ADAU1373_SRC_DAI_CTRL(1), 1, 0,
768 NULL, 0),
769 SND_SOC_DAPM_SUPPLY("AIF3 IN SRC", ADAU1373_SRC_DAI_CTRL(2), 2, 0,
770 NULL, 0),
771 SND_SOC_DAPM_SUPPLY("AIF3 OUT SRC", ADAU1373_SRC_DAI_CTRL(2), 1, 0,
772 NULL, 0),
773
774 SND_SOC_DAPM_AIF_IN("AIF1 IN", "AIF1 Playback", 0, SND_SOC_NOPM, 0, 0),
775 SND_SOC_DAPM_AIF_OUT("AIF1 OUT", "AIF1 Capture", 0, SND_SOC_NOPM, 0, 0),
776 SND_SOC_DAPM_AIF_IN("AIF2 IN", "AIF2 Playback", 0, SND_SOC_NOPM, 0, 0),
777 SND_SOC_DAPM_AIF_OUT("AIF2 OUT", "AIF2 Capture", 0, SND_SOC_NOPM, 0, 0),
778 SND_SOC_DAPM_AIF_IN("AIF3 IN", "AIF3 Playback", 0, SND_SOC_NOPM, 0, 0),
779 SND_SOC_DAPM_AIF_OUT("AIF3 OUT", "AIF3 Capture", 0, SND_SOC_NOPM, 0, 0),
780
781 SOC_MIXER_ARRAY("DSP Channel1 Mixer", SND_SOC_NOPM, 0, 0,
782 adau1373_dsp_channel1_mixer_controls),
783 SOC_MIXER_ARRAY("DSP Channel2 Mixer", SND_SOC_NOPM, 0, 0,
784 adau1373_dsp_channel2_mixer_controls),
785 SOC_MIXER_ARRAY("DSP Channel3 Mixer", SND_SOC_NOPM, 0, 0,
786 adau1373_dsp_channel3_mixer_controls),
787 SOC_MIXER_ARRAY("DSP Channel4 Mixer", SND_SOC_NOPM, 0, 0,
788 adau1373_dsp_channel4_mixer_controls),
789 SOC_MIXER_ARRAY("DSP Channel5 Mixer", SND_SOC_NOPM, 0, 0,
790 adau1373_dsp_channel5_mixer_controls),
791
792 SOC_MIXER_ARRAY("AIF1 Mixer", SND_SOC_NOPM, 0, 0,
793 adau1373_aif1_mixer_controls),
794 SOC_MIXER_ARRAY("AIF2 Mixer", SND_SOC_NOPM, 0, 0,
795 adau1373_aif2_mixer_controls),
796 SOC_MIXER_ARRAY("AIF3 Mixer", SND_SOC_NOPM, 0, 0,
797 adau1373_aif3_mixer_controls),
798 SOC_MIXER_ARRAY("DAC1 Mixer", SND_SOC_NOPM, 0, 0,
799 adau1373_dac1_mixer_controls),
800 SOC_MIXER_ARRAY("DAC2 Mixer", SND_SOC_NOPM, 0, 0,
801 adau1373_dac2_mixer_controls),
802
803 SND_SOC_DAPM_SUPPLY("DSP", ADAU1373_DIGEN, 4, 0, NULL, 0),
804 SND_SOC_DAPM_SUPPLY("Recording Engine B", ADAU1373_DIGEN, 3, 0, NULL, 0),
805 SND_SOC_DAPM_SUPPLY("Recording Engine A", ADAU1373_DIGEN, 2, 0, NULL, 0),
806 SND_SOC_DAPM_SUPPLY("Playback Engine B", ADAU1373_DIGEN, 1, 0, NULL, 0),
807 SND_SOC_DAPM_SUPPLY("Playback Engine A", ADAU1373_DIGEN, 0, 0, NULL, 0),
808
809 SND_SOC_DAPM_SUPPLY("PLL1", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
810 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
811 SND_SOC_DAPM_SUPPLY("PLL2", SND_SOC_NOPM, 0, 0, adau1373_pll_event,
812 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
813 SND_SOC_DAPM_SUPPLY("SYSCLK1", ADAU1373_CLK_SRC_DIV(0), 7, 0, NULL, 0),
814 SND_SOC_DAPM_SUPPLY("SYSCLK2", ADAU1373_CLK_SRC_DIV(1), 7, 0, NULL, 0),
815
816 SND_SOC_DAPM_INPUT("AIN1L"),
817 SND_SOC_DAPM_INPUT("AIN1R"),
818 SND_SOC_DAPM_INPUT("AIN2L"),
819 SND_SOC_DAPM_INPUT("AIN2R"),
820 SND_SOC_DAPM_INPUT("AIN3L"),
821 SND_SOC_DAPM_INPUT("AIN3R"),
822 SND_SOC_DAPM_INPUT("AIN4L"),
823 SND_SOC_DAPM_INPUT("AIN4R"),
824
825 SND_SOC_DAPM_INPUT("DMIC1DAT"),
826 SND_SOC_DAPM_INPUT("DMIC2DAT"),
827
828 SND_SOC_DAPM_OUTPUT("LOUT1L"),
829 SND_SOC_DAPM_OUTPUT("LOUT1R"),
830 SND_SOC_DAPM_OUTPUT("LOUT2L"),
831 SND_SOC_DAPM_OUTPUT("LOUT2R"),
832 SND_SOC_DAPM_OUTPUT("HPL"),
833 SND_SOC_DAPM_OUTPUT("HPR"),
834 SND_SOC_DAPM_OUTPUT("SPKL"),
835 SND_SOC_DAPM_OUTPUT("SPKR"),
836 SND_SOC_DAPM_OUTPUT("EP"),
837 };
838
adau1373_check_aif_clk(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)839 static int adau1373_check_aif_clk(struct snd_soc_dapm_widget *source,
840 struct snd_soc_dapm_widget *sink)
841 {
842 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
843 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
844 unsigned int dai;
845 const char *clk;
846
847 dai = sink->name[3] - '1';
848
849 if (!adau1373->dais[dai].clock_provider)
850 return 0;
851
852 if (adau1373->dais[dai].clk_src == ADAU1373_CLK_SRC_PLL1)
853 clk = "SYSCLK1";
854 else
855 clk = "SYSCLK2";
856
857 return snd_soc_dapm_widget_name_cmp(source, clk) == 0;
858 }
859
adau1373_check_src(struct snd_soc_dapm_widget * source,struct snd_soc_dapm_widget * sink)860 static int adau1373_check_src(struct snd_soc_dapm_widget *source,
861 struct snd_soc_dapm_widget *sink)
862 {
863 struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
864 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
865 unsigned int dai;
866
867 dai = sink->name[3] - '1';
868
869 return adau1373->dais[dai].enable_src;
870 }
871
872 #define DSP_CHANNEL_MIXER_ROUTES(_sink) \
873 { _sink, "DMIC2 Swapped Switch", "DMIC2" }, \
874 { _sink, "DMIC2 Switch", "DMIC2" }, \
875 { _sink, "ADC/DMIC1 Swapped Switch", "Decimator Mux" }, \
876 { _sink, "ADC/DMIC1 Switch", "Decimator Mux" }, \
877 { _sink, "AIF1 Switch", "AIF1 IN" }, \
878 { _sink, "AIF2 Switch", "AIF2 IN" }, \
879 { _sink, "AIF3 Switch", "AIF3 IN" }
880
881 #define DSP_OUTPUT_MIXER_ROUTES(_sink) \
882 { _sink, "DSP Channel1 Switch", "DSP Channel1 Mixer" }, \
883 { _sink, "DSP Channel2 Switch", "DSP Channel2 Mixer" }, \
884 { _sink, "DSP Channel3 Switch", "DSP Channel3 Mixer" }, \
885 { _sink, "DSP Channel4 Switch", "DSP Channel4 Mixer" }, \
886 { _sink, "DSP Channel5 Switch", "DSP Channel5 Mixer" }
887
888 #define LEFT_OUTPUT_MIXER_ROUTES(_sink) \
889 { _sink, "Right DAC2 Switch", "Right DAC2" }, \
890 { _sink, "Left DAC2 Switch", "Left DAC2" }, \
891 { _sink, "Right DAC1 Switch", "Right DAC1" }, \
892 { _sink, "Left DAC1 Switch", "Left DAC1" }, \
893 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
894 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
895 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
896 { _sink, "Input 4 Bypass Switch", "IN4PGA" }
897
898 #define RIGHT_OUTPUT_MIXER_ROUTES(_sink) \
899 { _sink, "Right DAC2 Switch", "Right DAC2" }, \
900 { _sink, "Left DAC2 Switch", "Left DAC2" }, \
901 { _sink, "Right DAC1 Switch", "Right DAC1" }, \
902 { _sink, "Left DAC1 Switch", "Left DAC1" }, \
903 { _sink, "Input 1 Bypass Switch", "IN1PGA" }, \
904 { _sink, "Input 2 Bypass Switch", "IN2PGA" }, \
905 { _sink, "Input 3 Bypass Switch", "IN3PGA" }, \
906 { _sink, "Input 4 Bypass Switch", "IN4PGA" }
907
908 static const struct snd_soc_dapm_route adau1373_dapm_routes[] = {
909 { "Left ADC Mixer", "DAC1 Switch", "Left DAC1" },
910 { "Left ADC Mixer", "Input 1 Switch", "IN1PGA" },
911 { "Left ADC Mixer", "Input 2 Switch", "IN2PGA" },
912 { "Left ADC Mixer", "Input 3 Switch", "IN3PGA" },
913 { "Left ADC Mixer", "Input 4 Switch", "IN4PGA" },
914
915 { "Right ADC Mixer", "DAC1 Switch", "Right DAC1" },
916 { "Right ADC Mixer", "Input 1 Switch", "IN1PGA" },
917 { "Right ADC Mixer", "Input 2 Switch", "IN2PGA" },
918 { "Right ADC Mixer", "Input 3 Switch", "IN3PGA" },
919 { "Right ADC Mixer", "Input 4 Switch", "IN4PGA" },
920
921 { "Left ADC", NULL, "Left ADC Mixer" },
922 { "Right ADC", NULL, "Right ADC Mixer" },
923
924 { "Decimator Mux", "ADC", "Left ADC" },
925 { "Decimator Mux", "ADC", "Right ADC" },
926 { "Decimator Mux", "DMIC1", "DMIC1" },
927
928 DSP_CHANNEL_MIXER_ROUTES("DSP Channel1 Mixer"),
929 DSP_CHANNEL_MIXER_ROUTES("DSP Channel2 Mixer"),
930 DSP_CHANNEL_MIXER_ROUTES("DSP Channel3 Mixer"),
931 DSP_CHANNEL_MIXER_ROUTES("DSP Channel4 Mixer"),
932 DSP_CHANNEL_MIXER_ROUTES("DSP Channel5 Mixer"),
933
934 DSP_OUTPUT_MIXER_ROUTES("AIF1 Mixer"),
935 DSP_OUTPUT_MIXER_ROUTES("AIF2 Mixer"),
936 DSP_OUTPUT_MIXER_ROUTES("AIF3 Mixer"),
937 DSP_OUTPUT_MIXER_ROUTES("DAC1 Mixer"),
938 DSP_OUTPUT_MIXER_ROUTES("DAC2 Mixer"),
939
940 { "AIF1 OUT", NULL, "AIF1 Mixer" },
941 { "AIF2 OUT", NULL, "AIF2 Mixer" },
942 { "AIF3 OUT", NULL, "AIF3 Mixer" },
943 { "Left DAC1", NULL, "DAC1 Mixer" },
944 { "Right DAC1", NULL, "DAC1 Mixer" },
945 { "Left DAC2", NULL, "DAC2 Mixer" },
946 { "Right DAC2", NULL, "DAC2 Mixer" },
947
948 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout1 Mixer"),
949 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout1 Mixer"),
950 LEFT_OUTPUT_MIXER_ROUTES("Left Lineout2 Mixer"),
951 RIGHT_OUTPUT_MIXER_ROUTES("Right Lineout2 Mixer"),
952 LEFT_OUTPUT_MIXER_ROUTES("Left Speaker Mixer"),
953 RIGHT_OUTPUT_MIXER_ROUTES("Right Speaker Mixer"),
954
955 { "Left Headphone Mixer", "Left DAC2 Switch", "Left DAC2" },
956 { "Left Headphone Mixer", "Left DAC1 Switch", "Left DAC1" },
957 { "Left Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
958 { "Left Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
959 { "Left Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
960 { "Left Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
961 { "Right Headphone Mixer", "Right DAC2 Switch", "Right DAC2" },
962 { "Right Headphone Mixer", "Right DAC1 Switch", "Right DAC1" },
963 { "Right Headphone Mixer", "Input 1 Bypass Switch", "IN1PGA" },
964 { "Right Headphone Mixer", "Input 2 Bypass Switch", "IN2PGA" },
965 { "Right Headphone Mixer", "Input 3 Bypass Switch", "IN3PGA" },
966 { "Right Headphone Mixer", "Input 4 Bypass Switch", "IN4PGA" },
967
968 { "Left Headphone Mixer", NULL, "Headphone Enable" },
969 { "Right Headphone Mixer", NULL, "Headphone Enable" },
970
971 { "Earpiece Mixer", "Right DAC2 Switch", "Right DAC2" },
972 { "Earpiece Mixer", "Left DAC2 Switch", "Left DAC2" },
973 { "Earpiece Mixer", "Right DAC1 Switch", "Right DAC1" },
974 { "Earpiece Mixer", "Left DAC1 Switch", "Left DAC1" },
975 { "Earpiece Mixer", "Input 1 Bypass Switch", "IN1PGA" },
976 { "Earpiece Mixer", "Input 2 Bypass Switch", "IN2PGA" },
977 { "Earpiece Mixer", "Input 3 Bypass Switch", "IN3PGA" },
978 { "Earpiece Mixer", "Input 4 Bypass Switch", "IN4PGA" },
979
980 { "LOUT1L", NULL, "Left Lineout1 Mixer" },
981 { "LOUT1R", NULL, "Right Lineout1 Mixer" },
982 { "LOUT2L", NULL, "Left Lineout2 Mixer" },
983 { "LOUT2R", NULL, "Right Lineout2 Mixer" },
984 { "SPKL", NULL, "Left Speaker Mixer" },
985 { "SPKR", NULL, "Right Speaker Mixer" },
986 { "HPL", NULL, "Left Headphone Mixer" },
987 { "HPR", NULL, "Right Headphone Mixer" },
988 { "EP", NULL, "Earpiece Mixer" },
989
990 { "IN1PGA", NULL, "AIN1L" },
991 { "IN2PGA", NULL, "AIN2L" },
992 { "IN3PGA", NULL, "AIN3L" },
993 { "IN4PGA", NULL, "AIN4L" },
994 { "IN1PGA", NULL, "AIN1R" },
995 { "IN2PGA", NULL, "AIN2R" },
996 { "IN3PGA", NULL, "AIN3R" },
997 { "IN4PGA", NULL, "AIN4R" },
998
999 { "SYSCLK1", NULL, "PLL1" },
1000 { "SYSCLK2", NULL, "PLL2" },
1001
1002 { "Left DAC1", NULL, "SYSCLK1" },
1003 { "Right DAC1", NULL, "SYSCLK1" },
1004 { "Left DAC2", NULL, "SYSCLK1" },
1005 { "Right DAC2", NULL, "SYSCLK1" },
1006 { "Left ADC", NULL, "SYSCLK1" },
1007 { "Right ADC", NULL, "SYSCLK1" },
1008
1009 { "DSP", NULL, "SYSCLK1" },
1010
1011 { "AIF1 Mixer", NULL, "DSP" },
1012 { "AIF2 Mixer", NULL, "DSP" },
1013 { "AIF3 Mixer", NULL, "DSP" },
1014 { "DAC1 Mixer", NULL, "DSP" },
1015 { "DAC2 Mixer", NULL, "DSP" },
1016 { "DAC1 Mixer", NULL, "Playback Engine A" },
1017 { "DAC2 Mixer", NULL, "Playback Engine B" },
1018 { "Left ADC Mixer", NULL, "Recording Engine A" },
1019 { "Right ADC Mixer", NULL, "Recording Engine A" },
1020
1021 { "AIF1 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1022 { "AIF2 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1023 { "AIF3 CLK", NULL, "SYSCLK1", adau1373_check_aif_clk },
1024 { "AIF1 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1025 { "AIF2 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1026 { "AIF3 CLK", NULL, "SYSCLK2", adau1373_check_aif_clk },
1027
1028 { "AIF1 IN", NULL, "AIF1 CLK" },
1029 { "AIF1 OUT", NULL, "AIF1 CLK" },
1030 { "AIF2 IN", NULL, "AIF2 CLK" },
1031 { "AIF2 OUT", NULL, "AIF2 CLK" },
1032 { "AIF3 IN", NULL, "AIF3 CLK" },
1033 { "AIF3 OUT", NULL, "AIF3 CLK" },
1034 { "AIF1 IN", NULL, "AIF1 IN SRC", adau1373_check_src },
1035 { "AIF1 OUT", NULL, "AIF1 OUT SRC", adau1373_check_src },
1036 { "AIF2 IN", NULL, "AIF2 IN SRC", adau1373_check_src },
1037 { "AIF2 OUT", NULL, "AIF2 OUT SRC", adau1373_check_src },
1038 { "AIF3 IN", NULL, "AIF3 IN SRC", adau1373_check_src },
1039 { "AIF3 OUT", NULL, "AIF3 OUT SRC", adau1373_check_src },
1040
1041 { "DMIC1", NULL, "DMIC1DAT" },
1042 { "DMIC1", NULL, "SYSCLK1" },
1043 { "DMIC1", NULL, "Recording Engine A" },
1044 { "DMIC2", NULL, "DMIC2DAT" },
1045 { "DMIC2", NULL, "SYSCLK1" },
1046 { "DMIC2", NULL, "Recording Engine B" },
1047 };
1048
adau1373_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1049 static int adau1373_hw_params(struct snd_pcm_substream *substream,
1050 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1051 {
1052 struct snd_soc_component *component = dai->component;
1053 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1054 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1055 unsigned int div;
1056 unsigned int freq;
1057 unsigned int ctrl;
1058
1059 freq = adau1373_dai->sysclk;
1060
1061 if (freq % params_rate(params) != 0)
1062 return -EINVAL;
1063
1064 switch (freq / params_rate(params)) {
1065 case 1024: /* sysclk / 256 */
1066 div = 0;
1067 break;
1068 case 1536: /* 2/3 sysclk / 256 */
1069 div = 1;
1070 break;
1071 case 2048: /* 1/2 sysclk / 256 */
1072 div = 2;
1073 break;
1074 case 3072: /* 1/3 sysclk / 256 */
1075 div = 3;
1076 break;
1077 case 4096: /* 1/4 sysclk / 256 */
1078 div = 4;
1079 break;
1080 case 6144: /* 1/6 sysclk / 256 */
1081 div = 5;
1082 break;
1083 case 5632: /* 2/11 sysclk / 256 */
1084 div = 6;
1085 break;
1086 default:
1087 return -EINVAL;
1088 }
1089
1090 adau1373_dai->enable_src = (div != 0);
1091
1092 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1093 ADAU1373_BCLKDIV_SR_MASK | ADAU1373_BCLKDIV_BCLK_MASK,
1094 (div << 2) | ADAU1373_BCLKDIV_64);
1095
1096 switch (params_width(params)) {
1097 case 16:
1098 ctrl = ADAU1373_DAI_WLEN_16;
1099 break;
1100 case 20:
1101 ctrl = ADAU1373_DAI_WLEN_20;
1102 break;
1103 case 24:
1104 ctrl = ADAU1373_DAI_WLEN_24;
1105 break;
1106 case 32:
1107 ctrl = ADAU1373_DAI_WLEN_32;
1108 break;
1109 default:
1110 return -EINVAL;
1111 }
1112
1113 return regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1114 ADAU1373_DAI_WLEN_MASK, ctrl);
1115 }
1116
adau1373_set_dai_fmt(struct snd_soc_dai * dai,unsigned int fmt)1117 static int adau1373_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1118 {
1119 struct snd_soc_component *component = dai->component;
1120 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1121 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1122 unsigned int ctrl;
1123
1124 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
1125 case SND_SOC_DAIFMT_CBP_CFP:
1126 ctrl = ADAU1373_DAI_MASTER;
1127 adau1373_dai->clock_provider = true;
1128 break;
1129 case SND_SOC_DAIFMT_CBC_CFC:
1130 ctrl = 0;
1131 adau1373_dai->clock_provider = false;
1132 break;
1133 default:
1134 return -EINVAL;
1135 }
1136
1137 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1138 case SND_SOC_DAIFMT_I2S:
1139 ctrl |= ADAU1373_DAI_FORMAT_I2S;
1140 break;
1141 case SND_SOC_DAIFMT_LEFT_J:
1142 ctrl |= ADAU1373_DAI_FORMAT_LEFT_J;
1143 break;
1144 case SND_SOC_DAIFMT_RIGHT_J:
1145 ctrl |= ADAU1373_DAI_FORMAT_RIGHT_J;
1146 break;
1147 case SND_SOC_DAIFMT_DSP_B:
1148 ctrl |= ADAU1373_DAI_FORMAT_DSP;
1149 break;
1150 default:
1151 return -EINVAL;
1152 }
1153
1154 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1155 case SND_SOC_DAIFMT_NB_NF:
1156 break;
1157 case SND_SOC_DAIFMT_IB_NF:
1158 ctrl |= ADAU1373_DAI_INVERT_BCLK;
1159 break;
1160 case SND_SOC_DAIFMT_NB_IF:
1161 ctrl |= ADAU1373_DAI_INVERT_LRCLK;
1162 break;
1163 case SND_SOC_DAIFMT_IB_IF:
1164 ctrl |= ADAU1373_DAI_INVERT_LRCLK | ADAU1373_DAI_INVERT_BCLK;
1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170 regmap_update_bits(adau1373->regmap, ADAU1373_DAI(dai->id),
1171 ~ADAU1373_DAI_WLEN_MASK, ctrl);
1172
1173 return 0;
1174 }
1175
adau1373_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)1176 static int adau1373_set_dai_sysclk(struct snd_soc_dai *dai,
1177 int clk_id, unsigned int freq, int dir)
1178 {
1179 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(dai->component);
1180 struct adau1373_dai *adau1373_dai = &adau1373->dais[dai->id];
1181
1182 switch (clk_id) {
1183 case ADAU1373_CLK_SRC_PLL1:
1184 case ADAU1373_CLK_SRC_PLL2:
1185 break;
1186 default:
1187 return -EINVAL;
1188 }
1189
1190 adau1373_dai->sysclk = freq;
1191 adau1373_dai->clk_src = clk_id;
1192
1193 regmap_update_bits(adau1373->regmap, ADAU1373_BCLKDIV(dai->id),
1194 ADAU1373_BCLKDIV_SOURCE, clk_id << 5);
1195
1196 return 0;
1197 }
1198
1199 static const struct snd_soc_dai_ops adau1373_dai_ops = {
1200 .hw_params = adau1373_hw_params,
1201 .set_sysclk = adau1373_set_dai_sysclk,
1202 .set_fmt = adau1373_set_dai_fmt,
1203 };
1204
1205 #define ADAU1373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1206 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
1207
1208 static struct snd_soc_dai_driver adau1373_dai_driver[] = {
1209 {
1210 .id = 0,
1211 .name = "adau1373-aif1",
1212 .playback = {
1213 .stream_name = "AIF1 Playback",
1214 .channels_min = 2,
1215 .channels_max = 2,
1216 .rates = SNDRV_PCM_RATE_8000_48000,
1217 .formats = ADAU1373_FORMATS,
1218 },
1219 .capture = {
1220 .stream_name = "AIF1 Capture",
1221 .channels_min = 2,
1222 .channels_max = 2,
1223 .rates = SNDRV_PCM_RATE_8000_48000,
1224 .formats = ADAU1373_FORMATS,
1225 },
1226 .ops = &adau1373_dai_ops,
1227 .symmetric_rate = 1,
1228 },
1229 {
1230 .id = 1,
1231 .name = "adau1373-aif2",
1232 .playback = {
1233 .stream_name = "AIF2 Playback",
1234 .channels_min = 2,
1235 .channels_max = 2,
1236 .rates = SNDRV_PCM_RATE_8000_48000,
1237 .formats = ADAU1373_FORMATS,
1238 },
1239 .capture = {
1240 .stream_name = "AIF2 Capture",
1241 .channels_min = 2,
1242 .channels_max = 2,
1243 .rates = SNDRV_PCM_RATE_8000_48000,
1244 .formats = ADAU1373_FORMATS,
1245 },
1246 .ops = &adau1373_dai_ops,
1247 .symmetric_rate = 1,
1248 },
1249 {
1250 .id = 2,
1251 .name = "adau1373-aif3",
1252 .playback = {
1253 .stream_name = "AIF3 Playback",
1254 .channels_min = 2,
1255 .channels_max = 2,
1256 .rates = SNDRV_PCM_RATE_8000_48000,
1257 .formats = ADAU1373_FORMATS,
1258 },
1259 .capture = {
1260 .stream_name = "AIF3 Capture",
1261 .channels_min = 2,
1262 .channels_max = 2,
1263 .rates = SNDRV_PCM_RATE_8000_48000,
1264 .formats = ADAU1373_FORMATS,
1265 },
1266 .ops = &adau1373_dai_ops,
1267 .symmetric_rate = 1,
1268 },
1269 };
1270
adau1373_set_pll(struct snd_soc_component * component,int pll_id,int source,unsigned int freq_in,unsigned int freq_out)1271 static int adau1373_set_pll(struct snd_soc_component *component, int pll_id,
1272 int source, unsigned int freq_in, unsigned int freq_out)
1273 {
1274 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1275 unsigned int dpll_div = 0;
1276 uint8_t pll_regs[5];
1277 int ret;
1278
1279 switch (pll_id) {
1280 case ADAU1373_PLL1:
1281 case ADAU1373_PLL2:
1282 break;
1283 default:
1284 return -EINVAL;
1285 }
1286
1287 switch (source) {
1288 case ADAU1373_PLL_SRC_BCLK1:
1289 case ADAU1373_PLL_SRC_BCLK2:
1290 case ADAU1373_PLL_SRC_BCLK3:
1291 case ADAU1373_PLL_SRC_LRCLK1:
1292 case ADAU1373_PLL_SRC_LRCLK2:
1293 case ADAU1373_PLL_SRC_LRCLK3:
1294 case ADAU1373_PLL_SRC_MCLK1:
1295 case ADAU1373_PLL_SRC_MCLK2:
1296 case ADAU1373_PLL_SRC_GPIO1:
1297 case ADAU1373_PLL_SRC_GPIO2:
1298 case ADAU1373_PLL_SRC_GPIO3:
1299 case ADAU1373_PLL_SRC_GPIO4:
1300 break;
1301 default:
1302 return -EINVAL;
1303 }
1304
1305 if (freq_in < 7813 || freq_in > 27000000)
1306 return -EINVAL;
1307
1308 if (freq_out < 45158000 || freq_out > 49152000)
1309 return -EINVAL;
1310
1311 /* APLL input needs to be >= 8Mhz, so in case freq_in is less we use the
1312 * DPLL to get it there. DPLL_out = (DPLL_in / div) * 1024 */
1313 while (freq_in < 8000000) {
1314 freq_in *= 2;
1315 dpll_div++;
1316 }
1317
1318 ret = adau_calc_pll_cfg(freq_in, freq_out, pll_regs);
1319 if (ret)
1320 return -EINVAL;
1321
1322 if (dpll_div) {
1323 dpll_div = 11 - dpll_div;
1324 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1325 ADAU1373_PLL_CTRL6_DPLL_BYPASS, 0);
1326 } else {
1327 regmap_update_bits(adau1373->regmap, ADAU1373_PLL_CTRL6(pll_id),
1328 ADAU1373_PLL_CTRL6_DPLL_BYPASS,
1329 ADAU1373_PLL_CTRL6_DPLL_BYPASS);
1330 }
1331
1332 regmap_write(adau1373->regmap, ADAU1373_DPLL_CTRL(pll_id),
1333 (source << 4) | dpll_div);
1334 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL1(pll_id), pll_regs[0]);
1335 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL2(pll_id), pll_regs[1]);
1336 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL3(pll_id), pll_regs[2]);
1337 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL4(pll_id), pll_regs[3]);
1338 regmap_write(adau1373->regmap, ADAU1373_PLL_CTRL5(pll_id), pll_regs[4]);
1339
1340 /* Set sysclk to pll_rate / 4 */
1341 regmap_update_bits(adau1373->regmap, ADAU1373_CLK_SRC_DIV(pll_id), 0x3f, 0x09);
1342
1343 return 0;
1344 }
1345
adau1373_load_drc_settings(struct adau1373 * adau1373,unsigned int nr,uint8_t * drc)1346 static void adau1373_load_drc_settings(struct adau1373 *adau1373,
1347 unsigned int nr, uint8_t *drc)
1348 {
1349 unsigned int i;
1350
1351 for (i = 0; i < ADAU1373_DRC_SIZE; ++i)
1352 regmap_write(adau1373->regmap, ADAU1373_DRC(nr) + i, drc[i]);
1353 }
1354
adau1373_get_micbias(unsigned int val,enum adau1373_micbias_voltage * micbias)1355 static int adau1373_get_micbias(unsigned int val,
1356 enum adau1373_micbias_voltage *micbias)
1357 {
1358 switch (val) {
1359 case 2900000:
1360 *micbias = ADAU1373_MICBIAS_2_9V;
1361 return 0;
1362 case 2200000:
1363 *micbias = ADAU1373_MICBIAS_2_2V;
1364 return 0;
1365 case 2600000:
1366 *micbias = ADAU1373_MICBIAS_2_6V;
1367 return 0;
1368 case 1800000:
1369 *micbias = ADAU1373_MICBIAS_1_8V;
1370 return 0;
1371 default:
1372 return -EINVAL;
1373 }
1374 }
1375
adau1373_probe(struct snd_soc_component * component)1376 static int adau1373_probe(struct snd_soc_component *component)
1377 {
1378 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1379 unsigned int val;
1380 int i;
1381
1382 for (i = 0; i < adau1373->num_drc; ++i) {
1383 adau1373_load_drc_settings(adau1373, i,
1384 adau1373->drc_setting[i]);
1385 }
1386
1387 snd_soc_add_component_controls(component, adau1373_drc_controls,
1388 adau1373->num_drc);
1389
1390 val = 0;
1391 for (i = 0; i < ARRAY_SIZE(adau1373->input_differential); ++i) {
1392 if (adau1373->input_differential[i])
1393 val |= BIT(i);
1394 }
1395 regmap_write(adau1373->regmap, ADAU1373_INPUT_MODE, val);
1396
1397 val = 0;
1398 if (adau1373->lineout_differential)
1399 val |= ADAU1373_OUTPUT_CTRL_LDIFF;
1400 if (adau1373->lineout_ground_sense)
1401 val |= ADAU1373_OUTPUT_CTRL_LNFBEN;
1402
1403 regmap_write(adau1373->regmap, ADAU1373_OUTPUT_CTRL, val);
1404
1405 regmap_write(adau1373->regmap, ADAU1373_EP_CTRL,
1406 (adau1373->micbias1 << ADAU1373_EP_CTRL_MICBIAS1_OFFSET) |
1407 (adau1373->micbias2 << ADAU1373_EP_CTRL_MICBIAS2_OFFSET));
1408
1409 if (!adau1373->lineout_differential) {
1410 snd_soc_add_component_controls(component, adau1373_lineout2_controls,
1411 ARRAY_SIZE(adau1373_lineout2_controls));
1412 }
1413
1414 regmap_write(adau1373->regmap, ADAU1373_ADC_CTRL,
1415 ADAU1373_ADC_CTRL_RESET_FORCE | ADAU1373_ADC_CTRL_PEAK_DETECT);
1416
1417 return 0;
1418 }
1419
adau1373_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)1420 static int adau1373_set_bias_level(struct snd_soc_component *component,
1421 enum snd_soc_bias_level level)
1422 {
1423 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1424
1425 switch (level) {
1426 case SND_SOC_BIAS_ON:
1427 break;
1428 case SND_SOC_BIAS_PREPARE:
1429 break;
1430 case SND_SOC_BIAS_STANDBY:
1431 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1432 ADAU1373_PWDN_CTRL3_PWR_EN, ADAU1373_PWDN_CTRL3_PWR_EN);
1433 break;
1434 case SND_SOC_BIAS_OFF:
1435 regmap_update_bits(adau1373->regmap, ADAU1373_PWDN_CTRL3,
1436 ADAU1373_PWDN_CTRL3_PWR_EN, 0);
1437 break;
1438 }
1439 return 0;
1440 }
1441
adau1373_resume(struct snd_soc_component * component)1442 static int adau1373_resume(struct snd_soc_component *component)
1443 {
1444 struct adau1373 *adau1373 = snd_soc_component_get_drvdata(component);
1445
1446 regcache_sync(adau1373->regmap);
1447
1448 return 0;
1449 }
1450
adau1373_register_volatile(struct device * dev,unsigned int reg)1451 static bool adau1373_register_volatile(struct device *dev, unsigned int reg)
1452 {
1453 switch (reg) {
1454 case ADAU1373_SOFT_RESET:
1455 case ADAU1373_ADC_DAC_STATUS:
1456 return true;
1457 default:
1458 return false;
1459 }
1460 }
1461
1462 static const struct regmap_config adau1373_regmap_config = {
1463 .val_bits = 8,
1464 .reg_bits = 8,
1465
1466 .volatile_reg = adau1373_register_volatile,
1467 .max_register = ADAU1373_SOFT_RESET,
1468
1469 .cache_type = REGCACHE_MAPLE,
1470 .reg_defaults = adau1373_reg_defaults,
1471 .num_reg_defaults = ARRAY_SIZE(adau1373_reg_defaults),
1472 };
1473
1474 static const struct snd_soc_component_driver adau1373_component_driver = {
1475 .probe = adau1373_probe,
1476 .resume = adau1373_resume,
1477 .set_bias_level = adau1373_set_bias_level,
1478 .set_pll = adau1373_set_pll,
1479 .controls = adau1373_controls,
1480 .num_controls = ARRAY_SIZE(adau1373_controls),
1481 .dapm_widgets = adau1373_dapm_widgets,
1482 .num_dapm_widgets = ARRAY_SIZE(adau1373_dapm_widgets),
1483 .dapm_routes = adau1373_dapm_routes,
1484 .num_dapm_routes = ARRAY_SIZE(adau1373_dapm_routes),
1485 .use_pmdown_time = 1,
1486 .endianness = 1,
1487 };
1488
adau1373_reset(void * reset_gpio)1489 static void adau1373_reset(void *reset_gpio)
1490 {
1491 gpiod_set_value_cansleep(reset_gpio, 1);
1492 }
1493
adau1373_parse_fw(struct device * dev,struct adau1373 * adau1373)1494 static int adau1373_parse_fw(struct device *dev, struct adau1373 *adau1373)
1495 {
1496 int ret, drc_count;
1497 unsigned int val;
1498
1499 if (device_property_present(dev, "adi,input1-differential"))
1500 adau1373->input_differential[0] = true;
1501 if (device_property_present(dev, "adi,input2-differential"))
1502 adau1373->input_differential[1] = true;
1503 if (device_property_present(dev, "adi,input3-differential"))
1504 adau1373->input_differential[2] = true;
1505 if (device_property_present(dev, "adi,input4-differential"))
1506 adau1373->input_differential[3] = true;
1507
1508 if (device_property_present(dev, "adi,lineout-differential"))
1509 adau1373->lineout_differential = true;
1510 if (device_property_present(dev, "adi,lineout-gnd-sense"))
1511 adau1373->lineout_ground_sense = true;
1512
1513 ret = device_property_read_u32(dev, "adi,micbias1-microvolt", &val);
1514 if (!ret) {
1515 ret = adau1373_get_micbias(val, &adau1373->micbias1);
1516 if (ret)
1517 return dev_err_probe(dev, ret,
1518 "Failed to get micbias1(%u)\n", val);
1519 }
1520
1521 ret = device_property_read_u32(dev, "adi,micbias2-microvolt", &val);
1522 if (!ret) {
1523 ret = adau1373_get_micbias(val, &adau1373->micbias2);
1524 if (ret)
1525 return dev_err_probe(dev, ret,
1526 "Failed to get micbias2(%u)\n", val);
1527 }
1528
1529 drc_count = device_property_count_u8(dev, "adi,drc-settings");
1530 if (drc_count < 0)
1531 return 0;
1532 if (drc_count % ADAU1373_DRC_SIZE != 0)
1533 return dev_err_probe(dev, -EINVAL,
1534 "DRC count(%u) not multiple of %u\n",
1535 drc_count, ADAU1373_DRC_SIZE);
1536
1537 adau1373->num_drc = drc_count / ADAU1373_DRC_SIZE;
1538 if (adau1373->num_drc > ARRAY_SIZE(adau1373->drc_setting))
1539 return dev_err_probe(dev, -EINVAL,
1540 "Too many DRC settings(%u)\n",
1541 adau1373->num_drc);
1542
1543 ret = device_property_read_u8_array(dev, "adi,drc-settings",
1544 (u8 *)&adau1373->drc_setting[0],
1545 drc_count);
1546 if (ret)
1547 return dev_err_probe(dev, ret,
1548 "Failed to read DRC settings\n");
1549
1550 return 0;
1551 }
1552
adau1373_i2c_probe(struct i2c_client * client)1553 static int adau1373_i2c_probe(struct i2c_client *client)
1554 {
1555 struct adau1373 *adau1373;
1556 struct gpio_desc *gpiod;
1557 int ret;
1558
1559 adau1373 = devm_kzalloc(&client->dev, sizeof(*adau1373), GFP_KERNEL);
1560 if (!adau1373)
1561 return -ENOMEM;
1562
1563 adau1373->regmap = devm_regmap_init_i2c(client,
1564 &adau1373_regmap_config);
1565 if (IS_ERR(adau1373->regmap))
1566 return PTR_ERR(adau1373->regmap);
1567
1568 /*
1569 * If the powerdown GPIO is specified, we use it for reset. Otherwise
1570 * a software reset is done.
1571 */
1572 gpiod = devm_gpiod_get_optional(&client->dev, "powerdown",
1573 GPIOD_OUT_HIGH);
1574 if (IS_ERR(gpiod))
1575 return PTR_ERR(gpiod);
1576
1577 if (gpiod) {
1578 gpiod_set_value_cansleep(gpiod, 0);
1579 fsleep(10);
1580
1581 ret = devm_add_action_or_reset(&client->dev, adau1373_reset,
1582 gpiod);
1583 if (ret)
1584 return ret;
1585 } else {
1586 regmap_write(adau1373->regmap, ADAU1373_SOFT_RESET, 0x00);
1587 }
1588
1589 dev_set_drvdata(&client->dev, adau1373);
1590
1591 ret = adau1373_parse_fw(&client->dev, adau1373);
1592 if (ret)
1593 return ret;
1594
1595 ret = devm_snd_soc_register_component(&client->dev,
1596 &adau1373_component_driver,
1597 adau1373_dai_driver, ARRAY_SIZE(adau1373_dai_driver));
1598 return ret;
1599 }
1600
1601 static const struct i2c_device_id adau1373_i2c_id[] = {
1602 { "adau1373" },
1603 { }
1604 };
1605 MODULE_DEVICE_TABLE(i2c, adau1373_i2c_id);
1606
1607 static const struct of_device_id adau1373_of_match[] = {
1608 { .compatible = "adi,adau1373", },
1609 { }
1610 };
1611 MODULE_DEVICE_TABLE(of, adau1373_of_match);
1612
1613 static struct i2c_driver adau1373_i2c_driver = {
1614 .driver = {
1615 .name = "adau1373",
1616 .of_match_table = adau1373_of_match,
1617 },
1618 .probe = adau1373_i2c_probe,
1619 .id_table = adau1373_i2c_id,
1620 };
1621
1622 module_i2c_driver(adau1373_i2c_driver);
1623
1624 MODULE_DESCRIPTION("ASoC ADAU1373 driver");
1625 MODULE_AUTHOR("Lars-Peter Clausen <[email protected]>");
1626 MODULE_LICENSE("GPL");
1627