1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * AMD ALSA SoC PDM Driver 4 * 5 * Copyright (C) 2022, 2023 Advanced Micro Devices, Inc. All rights reserved. 6 */ 7 8 #include <linux/soundwire/sdw_amd.h> 9 #include <sound/acp63_chip_offset_byte.h> 10 11 #define ACP_DEVICE_ID 0x15E2 12 #define ACP63_REG_START 0x1240000 13 #define ACP63_REG_END 0x125C000 14 #define ACP63_PCI_REV 0x63 15 16 #define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001 17 #define ACP_PGFSM_CNTL_POWER_ON_MASK 1 18 #define ACP_PGFSM_CNTL_POWER_OFF_MASK 0 19 #define ACP_PGFSM_STATUS_MASK 3 20 #define ACP_POWERED_ON 0 21 #define ACP_POWER_ON_IN_PROGRESS 1 22 #define ACP_POWERED_OFF 2 23 #define ACP_POWER_OFF_IN_PROGRESS 3 24 25 #define ACP_ERROR_MASK 0x20000000 26 #define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF 27 #define PDM_DMA_STAT 0x10 28 29 #define PDM_DMA_INTR_MASK 0x10000 30 #define ACP_ERROR_STAT 29 31 #define PDM_DECIMATION_FACTOR 2 32 #define ACP_PDM_CLK_FREQ_MASK 7 33 #define ACP_WOV_GAIN_CONTROL GENMASK(4, 3) 34 #define ACP_PDM_ENABLE 1 35 #define ACP_PDM_DISABLE 0 36 #define ACP_PDM_DMA_EN_STATUS 2 37 #define TWO_CH 2 38 #define DELAY_US 5 39 #define ACP_COUNTER 20000 40 41 #define ACP_SRAM_PTE_OFFSET 0x03800000 42 #define PAGE_SIZE_4K_ENABLE 2 43 #define PDM_PTE_OFFSET 0 44 #define PDM_MEM_WINDOW_START 0x4000000 45 46 #define CAPTURE_MIN_NUM_PERIODS 4 47 #define CAPTURE_MAX_NUM_PERIODS 4 48 #define CAPTURE_MAX_PERIOD_SIZE 8192 49 #define CAPTURE_MIN_PERIOD_SIZE 4096 50 51 #define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS) 52 #define MIN_BUFFER MAX_BUFFER 53 54 /* time in ms for runtime suspend delay */ 55 #define ACP_SUSPEND_DELAY_MS 2000 56 57 #define ACP_DMIC_DEV 2 58 59 #define ACP63_DMIC_ADDR 2 60 #define ACP63_SDW_ADDR 5 61 #define AMD_SDW_MAX_MANAGERS 2 62 63 /* time in ms for acp timeout */ 64 #define ACP_TIMEOUT 500 65 66 #define ACP_SDW0_STAT BIT(21) 67 #define ACP_SDW1_STAT BIT(2) 68 #define ACP_ERROR_IRQ BIT(29) 69 70 #define ACP_AUDIO0_TX_THRESHOLD 0x1c 71 #define ACP_AUDIO1_TX_THRESHOLD 0x1a 72 #define ACP_AUDIO2_TX_THRESHOLD 0x18 73 #define ACP_AUDIO0_RX_THRESHOLD 0x1b 74 #define ACP_AUDIO1_RX_THRESHOLD 0x19 75 #define ACP_AUDIO2_RX_THRESHOLD 0x17 76 #define ACP_P1_AUDIO1_TX_THRESHOLD BIT(6) 77 #define ACP_P1_AUDIO1_RX_THRESHOLD BIT(5) 78 #define ACP_SDW_DMA_IRQ_MASK 0x1F800000 79 #define ACP_P1_SDW_DMA_IRQ_MASK 0x60 80 #define ACP63_SDW0_DMA_MAX_STREAMS 6 81 #define ACP63_SDW1_DMA_MAX_STREAMS 2 82 #define ACP_P1_AUDIO_TX_THRESHOLD 6 83 84 /* 85 * Below entries describes SDW0 instance DMA stream id and DMA irq bit mapping 86 * in ACP_EXTENAL_INTR_CNTL register. 87 * Stream id IRQ Bit 88 * 0 (SDW0_AUDIO0_TX) 28 89 * 1 (SDW0_AUDIO1_TX) 26 90 * 2 (SDW0_AUDIO2_TX) 24 91 * 3 (SDW0_AUDIO0_RX) 27 92 * 4 (SDW0_AUDIO1_RX) 25 93 * 5 (SDW0_AUDIO2_RX) 23 94 */ 95 #define SDW0_DMA_TX_IRQ_MASK(i) (ACP_AUDIO0_TX_THRESHOLD - (2 * (i))) 96 #define SDW0_DMA_RX_IRQ_MASK(i) (ACP_AUDIO0_RX_THRESHOLD - (2 * ((i) - 3))) 97 98 /* 99 * Below entries describes SDW1 instance DMA stream id and DMA irq bit mapping 100 * in ACP_EXTENAL_INTR_CNTL1 register. 101 * Stream id IRQ Bit 102 * 0 (SDW1_AUDIO1_TX) 6 103 * 1 (SDW1_AUDIO1_RX) 5 104 */ 105 #define SDW1_DMA_IRQ_MASK(i) (ACP_P1_AUDIO_TX_THRESHOLD - (i)) 106 107 #define ACP_DELAY_US 5 108 #define ACP_SDW_RING_BUFF_ADDR_OFFSET (128 * 1024) 109 #define SDW0_MEM_WINDOW_START 0x4800000 110 #define ACP_SDW_SRAM_PTE_OFFSET 0x03800400 111 #define SDW0_PTE_OFFSET 0x400 112 #define SDW_FIFO_SIZE 0x100 113 #define SDW_DMA_SIZE 0x40 114 #define ACP_SDW0_FIFO_OFFSET 0x100 115 #define ACP_SDW_PTE_OFFSET 0x100 116 #define SDW_FIFO_OFFSET 0x100 117 #define SDW_PTE_OFFSET(i) (SDW0_PTE_OFFSET + ((i) * 0x600)) 118 #define ACP_SDW_FIFO_OFFSET(i) (ACP_SDW0_FIFO_OFFSET + ((i) * 0x500)) 119 #define SDW_MEM_WINDOW_START(i) (SDW0_MEM_WINDOW_START + ((i) * 0xC0000)) 120 121 #define SDW_PLAYBACK_MIN_NUM_PERIODS 2 122 #define SDW_PLAYBACK_MAX_NUM_PERIODS 8 123 #define SDW_PLAYBACK_MAX_PERIOD_SIZE 8192 124 #define SDW_PLAYBACK_MIN_PERIOD_SIZE 1024 125 #define SDW_CAPTURE_MIN_NUM_PERIODS 2 126 #define SDW_CAPTURE_MAX_NUM_PERIODS 8 127 #define SDW_CAPTURE_MAX_PERIOD_SIZE 8192 128 #define SDW_CAPTURE_MIN_PERIOD_SIZE 1024 129 130 #define SDW_MAX_BUFFER (SDW_PLAYBACK_MAX_PERIOD_SIZE * SDW_PLAYBACK_MAX_NUM_PERIODS) 131 #define SDW_MIN_BUFFER SDW_MAX_BUFFER 132 133 enum acp_config { 134 ACP_CONFIG_0 = 0, 135 ACP_CONFIG_1, 136 ACP_CONFIG_2, 137 ACP_CONFIG_3, 138 ACP_CONFIG_4, 139 ACP_CONFIG_5, 140 ACP_CONFIG_6, 141 ACP_CONFIG_7, 142 ACP_CONFIG_8, 143 ACP_CONFIG_9, 144 ACP_CONFIG_10, 145 ACP_CONFIG_11, 146 ACP_CONFIG_12, 147 ACP_CONFIG_13, 148 ACP_CONFIG_14, 149 ACP_CONFIG_15, 150 }; 151 152 enum amd_sdw0_channel { 153 ACP_SDW0_AUDIO0_TX = 0, 154 ACP_SDW0_AUDIO1_TX, 155 ACP_SDW0_AUDIO2_TX, 156 ACP_SDW0_AUDIO0_RX, 157 ACP_SDW0_AUDIO1_RX, 158 ACP_SDW0_AUDIO2_RX, 159 }; 160 161 enum amd_sdw1_channel { 162 ACP_SDW1_AUDIO1_TX, 163 ACP_SDW1_AUDIO1_RX, 164 }; 165 166 struct pdm_stream_instance { 167 u16 num_pages; 168 u16 channels; 169 dma_addr_t dma_addr; 170 u64 bytescount; 171 void __iomem *acp63_base; 172 }; 173 174 struct pdm_dev_data { 175 u32 pdm_irq; 176 void __iomem *acp63_base; 177 struct mutex *acp_lock; 178 struct snd_pcm_substream *capture_stream; 179 }; 180 181 struct sdw_dma_dev_data { 182 void __iomem *acp_base; 183 struct mutex *acp_lock; /* used to protect acp common register access */ 184 struct snd_pcm_substream *sdw0_dma_stream[ACP63_SDW0_DMA_MAX_STREAMS]; 185 struct snd_pcm_substream *sdw1_dma_stream[ACP63_SDW1_DMA_MAX_STREAMS]; 186 }; 187 188 struct acp_sdw_dma_stream { 189 u16 num_pages; 190 u16 channels; 191 u32 stream_id; 192 u32 instance; 193 dma_addr_t dma_addr; 194 u64 bytescount; 195 }; 196 197 union acp_sdw_dma_count { 198 struct { 199 u32 low; 200 u32 high; 201 } bcount; 202 u64 bytescount; 203 }; 204 205 struct sdw_dma_ring_buf_reg { 206 u32 reg_dma_size; 207 u32 reg_fifo_addr; 208 u32 reg_fifo_size; 209 u32 reg_ring_buf_size; 210 u32 reg_ring_buf_addr; 211 u32 water_mark_size_reg; 212 u32 pos_low_reg; 213 u32 pos_high_reg; 214 }; 215 216 /** 217 * struct acp63_dev_data - acp pci driver context 218 * @acp63_base: acp mmio base 219 * @res: resource 220 * @pdm_dev: ACP PDM controller platform device 221 * @dmic_codec: platform device for DMIC Codec 222 * sdw_dma_dev: platform device for SoundWire DMA controller 223 * @mach_dev: platform device for machine driver to support ACP PDM/SoundWire configuration 224 * @acp_lock: used to protect acp common registers 225 * @info: SoundWire AMD information found in ACPI tables 226 * @sdw: SoundWire context for all SoundWire manager instances 227 * @machine: ACPI machines for SoundWire interface 228 * @is_sdw_dev: flag set to true when any SoundWire manager instances are available 229 * @is_pdm_dev: flag set to true when ACP PDM controller exists 230 * @is_pdm_config: flat set to true when PDM configuration is selected from BIOS 231 * @is_sdw_config: flag set to true when SDW configuration is selected from BIOS 232 * @sdw_en_stat: flag set to true when any one of the SoundWire manager instance is enabled 233 * @addr: pci ioremap address 234 * @reg_range: ACP reigister range 235 * @acp_rev: ACP PCI revision id 236 * @sdw0-dma_intr_stat: DMA interrupt status array for SoundWire manager-SW0 instance 237 * @sdw_dma_intr_stat: DMA interrupt status array for SoundWire manager-SW1 instance 238 */ 239 240 struct acp63_dev_data { 241 void __iomem *acp63_base; 242 struct resource *res; 243 struct platform_device *pdm_dev; 244 struct platform_device *dmic_codec_dev; 245 struct platform_device *sdw_dma_dev; 246 struct platform_device *mach_dev; 247 struct mutex acp_lock; /* protect shared registers */ 248 struct sdw_amd_acpi_info info; 249 /* sdw context allocated by SoundWire driver */ 250 struct sdw_amd_ctx *sdw; 251 struct snd_soc_acpi_mach *machines; 252 bool is_sdw_dev; 253 bool is_pdm_dev; 254 bool is_pdm_config; 255 bool is_sdw_config; 256 bool sdw_en_stat; 257 u32 addr; 258 u32 reg_range; 259 u32 acp_rev; 260 u16 sdw0_dma_intr_stat[ACP63_SDW0_DMA_MAX_STREAMS]; 261 u16 sdw1_dma_intr_stat[ACP63_SDW1_DMA_MAX_STREAMS]; 262 }; 263 264 int snd_amd_acp_find_config(struct pci_dev *pci); 265