1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 dmsc: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 bootph-all; 25 }; 26 27 k3_clks: clock-controller { 28 compatible = "ti,k2g-sci-clk"; 29 #clock-cells = <2>; 30 bootph-all; 31 }; 32 33 k3_reset: reset-controller { 34 compatible = "ti,sci-reset"; 35 #reset-cells = <2>; 36 bootph-all; 37 }; 38 }; 39 40 mcu_timer0: timer@40400000 { 41 status = "reserved"; 42 compatible = "ti,am654-timer"; 43 reg = <0x00 0x40400000 0x00 0x400>; 44 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 45 clocks = <&k3_clks 35 1>; 46 clock-names = "fck"; 47 assigned-clocks = <&k3_clks 35 1>; 48 assigned-clock-parents = <&k3_clks 35 2>; 49 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 50 bootph-pre-ram; 51 ti,timer-pwm; 52 }; 53 54 mcu_timer1: timer@40410000 { 55 status = "reserved"; 56 compatible = "ti,am654-timer"; 57 reg = <0x00 0x40410000 0x00 0x400>; 58 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 59 clocks = <&k3_clks 71 1>; 60 clock-names = "fck"; 61 assigned-clocks = <&k3_clks 71 1>, <&k3_clks 308 0>; 62 assigned-clock-parents = <&k3_clks 71 2>, <&k3_clks 308 1>; 63 power-domains = <&k3_pds 71 TI_SCI_PD_EXCLUSIVE>; 64 ti,timer-pwm; 65 }; 66 67 mcu_timer2: timer@40420000 { 68 status = "reserved"; 69 compatible = "ti,am654-timer"; 70 reg = <0x00 0x40420000 0x00 0x400>; 71 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 72 clocks = <&k3_clks 72 1>; 73 clock-names = "fck"; 74 assigned-clocks = <&k3_clks 72 1>; 75 assigned-clock-parents = <&k3_clks 72 2>; 76 power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; 77 ti,timer-pwm; 78 }; 79 80 mcu_timer3: timer@40430000 { 81 status = "reserved"; 82 compatible = "ti,am654-timer"; 83 reg = <0x00 0x40430000 0x00 0x400>; 84 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 85 clocks = <&k3_clks 73 1>; 86 clock-names = "fck"; 87 assigned-clocks = <&k3_clks 73 1>, <&k3_clks 309 0>; 88 assigned-clock-parents = <&k3_clks 73 2>, <&k3_clks 309 1>; 89 power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; 90 ti,timer-pwm; 91 }; 92 93 mcu_timer4: timer@40440000 { 94 status = "reserved"; 95 compatible = "ti,am654-timer"; 96 reg = <0x00 0x40440000 0x00 0x400>; 97 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&k3_clks 74 1>; 99 clock-names = "fck"; 100 assigned-clocks = <&k3_clks 74 1>; 101 assigned-clock-parents = <&k3_clks 74 2>; 102 power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; 103 ti,timer-pwm; 104 }; 105 106 mcu_timer5: timer@40450000 { 107 status = "reserved"; 108 compatible = "ti,am654-timer"; 109 reg = <0x00 0x40450000 0x00 0x400>; 110 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 111 clocks = <&k3_clks 75 1>; 112 clock-names = "fck"; 113 assigned-clocks = <&k3_clks 75 1>, <&k3_clks 310 0>; 114 assigned-clock-parents = <&k3_clks 75 2>, <&k3_clks 310 1>; 115 power-domains = <&k3_pds 75 TI_SCI_PD_EXCLUSIVE>; 116 ti,timer-pwm; 117 }; 118 119 mcu_timer6: timer@40460000 { 120 status = "reserved"; 121 compatible = "ti,am654-timer"; 122 reg = <0x00 0x40460000 0x00 0x400>; 123 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 124 clocks = <&k3_clks 76 1>; 125 clock-names = "fck"; 126 assigned-clocks = <&k3_clks 76 1>; 127 assigned-clock-parents = <&k3_clks 76 2>; 128 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 129 ti,timer-pwm; 130 }; 131 132 mcu_timer7: timer@40470000 { 133 status = "reserved"; 134 compatible = "ti,am654-timer"; 135 reg = <0x00 0x40470000 0x00 0x400>; 136 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 137 clocks = <&k3_clks 77 1>; 138 clock-names = "fck"; 139 assigned-clocks = <&k3_clks 77 1>, <&k3_clks 311 0>; 140 assigned-clock-parents = <&k3_clks 77 2>, <&k3_clks 311 1>; 141 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 142 ti,timer-pwm; 143 }; 144 145 mcu_timer8: timer@40480000 { 146 status = "reserved"; 147 compatible = "ti,am654-timer"; 148 reg = <0x00 0x40480000 0x00 0x400>; 149 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 150 clocks = <&k3_clks 78 1>; 151 clock-names = "fck"; 152 assigned-clocks = <&k3_clks 78 1>; 153 assigned-clock-parents = <&k3_clks 78 2>; 154 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 155 ti,timer-pwm; 156 }; 157 158 mcu_timer9: timer@40490000 { 159 status = "reserved"; 160 compatible = "ti,am654-timer"; 161 reg = <0x00 0x40490000 0x00 0x400>; 162 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&k3_clks 79 1>; 164 clock-names = "fck"; 165 assigned-clocks = <&k3_clks 79 1>, <&k3_clks 312 0>; 166 assigned-clock-parents = <&k3_clks 79 2>, <&k3_clks 312 1>; 167 power-domains = <&k3_pds 79 TI_SCI_PD_EXCLUSIVE>; 168 ti,timer-pwm; 169 }; 170 171 mcu_conf: bus@40f00000 { 172 compatible = "simple-bus"; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0x0 0x0 0x40f00000 0x20000>; 176 177 cpsw_mac_syscon: ethernet-mac-syscon@200 { 178 compatible = "ti,am62p-cpsw-mac-efuse", "syscon"; 179 reg = <0x200 0x8>; 180 }; 181 182 phy_gmii_sel: phy@4040 { 183 compatible = "ti,am654-phy-gmii-sel"; 184 reg = <0x4040 0x4>; 185 #phy-cells = <1>; 186 }; 187 188 spi1_linkdis: mux-controller@4060 { 189 compatible = "reg-mux"; 190 reg = <0x4060 0x4>; 191 #mux-control-cells = <1>; 192 mux-reg-masks = <0x0 0x1>; 193 }; 194 }; 195 196 wkup_conf: bus@43000000 { 197 compatible = "simple-bus"; 198 #address-cells = <1>; 199 #size-cells = <1>; 200 ranges = <0x0 0x00 0x43000000 0x20000>; 201 202 chipid: chipid@14 { 203 compatible = "ti,am654-chipid"; 204 reg = <0x14 0x4>; 205 bootph-all; 206 }; 207 }; 208 209 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 210 mcu_timerio_input: pinctrl@40f04200 { 211 compatible = "ti,j7200-padconf", "pinctrl-single"; 212 reg = <0x0 0x40f04200 0x0 0x28>; 213 #pinctrl-cells = <1>; 214 pinctrl-single,register-width = <32>; 215 pinctrl-single,function-mask = <0x0000000F>; 216 status = "reserved"; 217 }; 218 219 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 220 mcu_timerio_output: pinctrl@40f04280 { 221 compatible = "ti,j7200-padconf", "pinctrl-single"; 222 reg = <0x0 0x40f04280 0x0 0x28>; 223 #pinctrl-cells = <1>; 224 pinctrl-single,register-width = <32>; 225 pinctrl-single,function-mask = <0x0000000F>; 226 status = "reserved"; 227 }; 228 229 wkup_pmx0: pinctrl@4301c000 { 230 compatible = "ti,j7200-padconf", "pinctrl-single"; 231 /* Proxy 0 addressing */ 232 reg = <0x00 0x4301c000 0x00 0x34>; 233 #pinctrl-cells = <1>; 234 pinctrl-single,register-width = <32>; 235 pinctrl-single,function-mask = <0xffffffff>; 236 }; 237 238 wkup_pmx1: pinctrl@4301c038 { 239 compatible = "ti,j7200-padconf", "pinctrl-single"; 240 /* Proxy 0 addressing */ 241 reg = <0x00 0x4301c038 0x00 0x8>; 242 #pinctrl-cells = <1>; 243 pinctrl-single,register-width = <32>; 244 pinctrl-single,function-mask = <0xffffffff>; 245 }; 246 247 wkup_pmx2: pinctrl@4301c068 { 248 compatible = "ti,j7200-padconf", "pinctrl-single"; 249 /* Proxy 0 addressing */ 250 reg = <0x00 0x4301c068 0x00 0xec>; 251 #pinctrl-cells = <1>; 252 pinctrl-single,register-width = <32>; 253 pinctrl-single,function-mask = <0xffffffff>; 254 }; 255 256 wkup_pmx3: pinctrl@4301c174 { 257 compatible = "ti,j7200-padconf", "pinctrl-single"; 258 /* Proxy 0 addressing */ 259 reg = <0x00 0x4301c174 0x00 0x20>; 260 #pinctrl-cells = <1>; 261 pinctrl-single,register-width = <32>; 262 pinctrl-single,function-mask = <0xffffffff>; 263 }; 264 265 mcu_ram: sram@41c00000 { 266 compatible = "mmio-sram"; 267 reg = <0x00 0x41c00000 0x00 0x100000>; 268 ranges = <0x00 0x00 0x41c00000 0x100000>; 269 #address-cells = <1>; 270 #size-cells = <1>; 271 }; 272 273 wkup_uart0: serial@42300000 { 274 compatible = "ti,j721e-uart", "ti,am654-uart"; 275 reg = <0x00 0x42300000 0x00 0x100>; 276 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 277 clock-frequency = <48000000>; 278 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>; 279 clocks = <&k3_clks 287 2>; 280 clock-names = "fclk"; 281 status = "disabled"; 282 }; 283 284 mcu_uart0: serial@40a00000 { 285 compatible = "ti,j721e-uart", "ti,am654-uart"; 286 reg = <0x00 0x40a00000 0x00 0x100>; 287 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 288 clock-frequency = <96000000>; 289 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 290 clocks = <&k3_clks 149 2>; 291 clock-names = "fclk"; 292 status = "disabled"; 293 }; 294 295 wkup_gpio_intr: interrupt-controller@42200000 { 296 compatible = "ti,sci-intr"; 297 reg = <0x00 0x42200000 0x00 0x400>; 298 ti,intr-trigger-type = <1>; 299 interrupt-controller; 300 interrupt-parent = <&gic500>; 301 #interrupt-cells = <1>; 302 ti,sci = <&dmsc>; 303 ti,sci-dev-id = <137>; 304 ti,interrupt-ranges = <16 960 16>; 305 }; 306 307 wkup_gpio0: gpio@42110000 { 308 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 309 reg = <0x00 0x42110000 0x00 0x100>; 310 gpio-controller; 311 #gpio-cells = <2>; 312 interrupt-parent = <&wkup_gpio_intr>; 313 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 314 interrupt-controller; 315 #interrupt-cells = <2>; 316 ti,ngpio = <85>; 317 ti,davinci-gpio-unbanked = <0>; 318 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 319 clocks = <&k3_clks 113 0>; 320 clock-names = "gpio"; 321 status = "disabled"; 322 }; 323 324 wkup_gpio1: gpio@42100000 { 325 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 326 reg = <0x00 0x42100000 0x00 0x100>; 327 gpio-controller; 328 #gpio-cells = <2>; 329 interrupt-parent = <&wkup_gpio_intr>; 330 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 331 interrupt-controller; 332 #interrupt-cells = <2>; 333 ti,ngpio = <85>; 334 ti,davinci-gpio-unbanked = <0>; 335 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 336 clocks = <&k3_clks 114 0>; 337 clock-names = "gpio"; 338 status = "disabled"; 339 }; 340 341 mcu_navss: bus@28380000 { 342 compatible = "simple-bus"; 343 #address-cells = <2>; 344 #size-cells = <2>; 345 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 346 dma-coherent; 347 dma-ranges; 348 ti,sci-dev-id = <232>; 349 350 mcu_ringacc: ringacc@2b800000 { 351 compatible = "ti,am654-navss-ringacc"; 352 reg = <0x00 0x2b800000 0x00 0x400000>, 353 <0x00 0x2b000000 0x00 0x400000>, 354 <0x00 0x28590000 0x00 0x100>, 355 <0x00 0x2a500000 0x00 0x40000>, 356 <0x00 0x28440000 0x00 0x40000>; 357 reg-names = "rt", "fifos", "proxy_gcfg", 358 "proxy_target", "cfg"; 359 bootph-all; 360 ti,num-rings = <286>; 361 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 362 ti,sci = <&dmsc>; 363 ti,sci-dev-id = <235>; 364 msi-parent = <&main_udmass_inta>; 365 }; 366 367 mcu_udmap: dma-controller@285c0000 { 368 compatible = "ti,j721e-navss-mcu-udmap"; 369 reg = <0x00 0x285c0000 0x00 0x100>, 370 <0x00 0x2a800000 0x00 0x40000>, 371 <0x00 0x2aa00000 0x00 0x40000>, 372 <0x00 0x284a0000 0x00 0x4000>, 373 <0x00 0x284c0000 0x00 0x4000>, 374 <0x00 0x28400000 0x00 0x2000>; 375 reg-names = "gcfg", "rchanrt", "tchanrt", 376 "tchan", "rchan", "rflow"; 377 msi-parent = <&main_udmass_inta>; 378 #dma-cells = <1>; 379 bootph-all; 380 381 ti,sci = <&dmsc>; 382 ti,sci-dev-id = <236>; 383 ti,ringacc = <&mcu_ringacc>; 384 385 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 386 <0x0f>; /* TX_HCHAN */ 387 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 388 <0x0b>; /* RX_HCHAN */ 389 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 390 }; 391 }; 392 393 secure_proxy_mcu: mailbox@2a480000 { 394 compatible = "ti,am654-secure-proxy"; 395 #mbox-cells = <1>; 396 reg-names = "target_data", "rt", "scfg"; 397 reg = <0x0 0x2a480000 0x0 0x80000>, 398 <0x0 0x2a380000 0x0 0x80000>, 399 <0x0 0x2a400000 0x0 0x80000>; 400 bootph-pre-ram; 401 402 /* 403 * Marked Disabled: 404 * Node is incomplete as it is meant for bootloaders and 405 * firmware on non-MPU processors 406 */ 407 status = "disabled"; 408 }; 409 410 mcu_cpsw: ethernet@46000000 { 411 compatible = "ti,j721e-cpsw-nuss"; 412 #address-cells = <2>; 413 #size-cells = <2>; 414 reg = <0x00 0x46000000 0x00 0x200000>; 415 reg-names = "cpsw_nuss"; 416 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 417 dma-coherent; 418 clocks = <&k3_clks 18 21>; 419 clock-names = "fck"; 420 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>; 421 422 dmas = <&mcu_udmap 0xf000>, 423 <&mcu_udmap 0xf001>, 424 <&mcu_udmap 0xf002>, 425 <&mcu_udmap 0xf003>, 426 <&mcu_udmap 0xf004>, 427 <&mcu_udmap 0xf005>, 428 <&mcu_udmap 0xf006>, 429 <&mcu_udmap 0xf007>, 430 <&mcu_udmap 0x7000>; 431 dma-names = "tx0", "tx1", "tx2", "tx3", 432 "tx4", "tx5", "tx6", "tx7", 433 "rx"; 434 435 ethernet-ports { 436 #address-cells = <1>; 437 #size-cells = <0>; 438 439 cpsw_port1: port@1 { 440 reg = <1>; 441 ti,mac-only; 442 label = "port1"; 443 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>; 444 phys = <&phy_gmii_sel 1>; 445 }; 446 }; 447 448 davinci_mdio: mdio@f00 { 449 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 450 reg = <0x00 0xf00 0x00 0x100>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 clocks = <&k3_clks 18 21>; 454 clock-names = "fck"; 455 bus_freq = <1000000>; 456 }; 457 458 cpts@3d000 { 459 compatible = "ti,am65-cpts"; 460 reg = <0x00 0x3d000 0x00 0x400>; 461 clocks = <&k3_clks 18 2>; 462 clock-names = "cpts"; 463 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 464 interrupt-names = "cpts"; 465 ti,cpts-ext-ts-inputs = <4>; 466 ti,cpts-periodic-outputs = <2>; 467 }; 468 }; 469 470 mcu_i2c0: i2c@40b00000 { 471 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 472 reg = <0x00 0x40b00000 0x00 0x100>; 473 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 clock-names = "fck"; 477 clocks = <&k3_clks 194 1>; 478 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>; 479 status = "disabled"; 480 }; 481 482 mcu_i2c1: i2c@40b10000 { 483 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 484 reg = <0x00 0x40b10000 0x00 0x100>; 485 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 clock-names = "fck"; 489 clocks = <&k3_clks 195 1>; 490 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>; 491 status = "disabled"; 492 }; 493 494 wkup_i2c0: i2c@42120000 { 495 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 496 reg = <0x00 0x42120000 0x00 0x100>; 497 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 clock-names = "fck"; 501 clocks = <&k3_clks 197 1>; 502 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>; 503 status = "disabled"; 504 }; 505 506 mcu_spi0: spi@40300000 { 507 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 508 reg = <0x00 0x040300000 0x00 0x400>; 509 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 513 clocks = <&k3_clks 274 4>; 514 status = "disabled"; 515 }; 516 517 mcu_spi1: spi@40310000 { 518 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 519 reg = <0x00 0x040310000 0x00 0x400>; 520 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 521 #address-cells = <1>; 522 #size-cells = <0>; 523 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 524 clocks = <&k3_clks 275 4>; 525 status = "disabled"; 526 }; 527 528 mcu_spi2: spi@40320000 { 529 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 530 reg = <0x00 0x040320000 0x00 0x400>; 531 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 532 #address-cells = <1>; 533 #size-cells = <0>; 534 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 535 clocks = <&k3_clks 276 2>; 536 status = "disabled"; 537 }; 538 539 fss: bus@47000000 { 540 compatible = "simple-bus"; 541 #address-cells = <2>; 542 #size-cells = <2>; 543 ranges = <0x0 0x47000000 0x0 0x47000000 0x0 0x100>, /* FSS Control */ 544 <0x0 0x47034000 0x0 0x47040000 0x0 0x100>, /* HBMC Control */ 545 <0x0 0x47040000 0x0 0x47040000 0x0 0x100>, /* OSPI0 Control */ 546 <0x5 0x00000000 0x5 0x00000000 0x1 0x0000000>; /* HBMC/OSPI0 Memory */ 547 548 hbmc_mux: mux-controller@47000004 { 549 compatible = "reg-mux"; 550 reg = <0x00 0x47000004 0x00 0x4>; 551 #mux-control-cells = <1>; 552 mux-reg-masks = <0x0 0x2>; /* HBMC select */ 553 bootph-all; 554 }; 555 556 hbmc: hyperbus@47034000 { 557 compatible = "ti,am654-hbmc"; 558 reg = <0x00 0x47034000 0x00 0x100>, 559 <0x05 0x00000000 0x01 0x0000000>; 560 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; 561 clocks = <&k3_clks 102 0>; 562 assigned-clocks = <&k3_clks 102 5>; 563 assigned-clock-rates = <333333333>; 564 #address-cells = <2>; 565 #size-cells = <1>; 566 mux-controls = <&hbmc_mux 0>; 567 }; 568 569 ospi0: spi@47040000 { 570 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 571 reg = <0x0 0x47040000 0x0 0x100>, 572 <0x5 0x00000000 0x1 0x0000000>; 573 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 574 cdns,fifo-depth = <256>; 575 cdns,fifo-width = <4>; 576 cdns,trigger-address = <0x0>; 577 clocks = <&k3_clks 103 0>; 578 assigned-clocks = <&k3_clks 103 0>; 579 assigned-clock-parents = <&k3_clks 103 2>; 580 assigned-clock-rates = <166666666>; 581 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 }; 587 588 tscadc0: tscadc@40200000 { 589 compatible = "ti,am3359-tscadc"; 590 reg = <0x00 0x40200000 0x00 0x1000>; 591 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 592 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 593 clocks = <&k3_clks 0 1>; 594 assigned-clocks = <&k3_clks 0 3>; 595 assigned-clock-rates = <60000000>; 596 clock-names = "fck"; 597 dmas = <&main_udmap 0x7400>, 598 <&main_udmap 0x7401>; 599 dma-names = "fifo0", "fifo1"; 600 601 adc { 602 #io-channel-cells = <1>; 603 compatible = "ti,am3359-adc"; 604 }; 605 }; 606 607 mcu_r5fss0: r5fss@41000000 { 608 compatible = "ti,j7200-r5fss"; 609 ti,cluster-mode = <1>; 610 #address-cells = <1>; 611 #size-cells = <1>; 612 ranges = <0x41000000 0x00 0x41000000 0x20000>, 613 <0x41400000 0x00 0x41400000 0x20000>; 614 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 615 616 mcu_r5fss0_core0: r5f@41000000 { 617 compatible = "ti,j7200-r5f"; 618 reg = <0x41000000 0x00010000>, 619 <0x41010000 0x00010000>; 620 reg-names = "atcm", "btcm"; 621 ti,sci = <&dmsc>; 622 ti,sci-dev-id = <250>; 623 ti,sci-proc-ids = <0x01 0xff>; 624 resets = <&k3_reset 250 1>; 625 firmware-name = "j7200-mcu-r5f0_0-fw"; 626 ti,atcm-enable = <1>; 627 ti,btcm-enable = <1>; 628 ti,loczrama = <1>; 629 }; 630 631 mcu_r5fss0_core1: r5f@41400000 { 632 compatible = "ti,j7200-r5f"; 633 reg = <0x41400000 0x00008000>, 634 <0x41410000 0x00008000>; 635 reg-names = "atcm", "btcm"; 636 ti,sci = <&dmsc>; 637 ti,sci-dev-id = <251>; 638 ti,sci-proc-ids = <0x02 0xff>; 639 resets = <&k3_reset 251 1>; 640 firmware-name = "j7200-mcu-r5f0_1-fw"; 641 ti,atcm-enable = <1>; 642 ti,btcm-enable = <1>; 643 ti,loczrama = <1>; 644 }; 645 }; 646 647 mcu_crypto: crypto@40900000 { 648 compatible = "ti,j721e-sa2ul"; 649 reg = <0x00 0x40900000 0x00 0x1200>; 650 power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>; 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>; 654 dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>, 655 <&mcu_udmap 0x7503>; 656 dma-names = "tx", "rx1", "rx2"; 657 658 rng: rng@40910000 { 659 compatible = "inside-secure,safexcel-eip76"; 660 reg = <0x00 0x40910000 0x00 0x7d>; 661 interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>; 662 status = "disabled"; /* Used by OP-TEE */ 663 }; 664 }; 665 666 wkup_vtm0: temperature-sensor@42040000 { 667 compatible = "ti,j7200-vtm"; 668 reg = <0x00 0x42040000 0x00 0x350>, 669 <0x00 0x42050000 0x00 0x350>; 670 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 671 #thermal-sensor-cells = <1>; 672 bootph-pre-ram; 673 }; 674 675 mcu_esm: esm@40800000 { 676 compatible = "ti,j721e-esm"; 677 reg = <0x00 0x40800000 0x00 0x1000>; 678 ti,esm-pins = <95>; 679 bootph-pre-ram; 680 }; 681 682 mcu_mcan0: can@40528000 { 683 compatible = "bosch,m_can"; 684 reg = <0x00 0x40528000 0x00 0x200>, 685 <0x00 0x40500000 0x00 0x8000>; 686 reg-names = "m_can", "message_ram"; 687 power-domains = <&k3_pds 172 TI_SCI_PD_EXCLUSIVE>; 688 clocks = <&k3_clks 172 0>, <&k3_clks 172 2>; 689 clock-names = "hclk", "cclk"; 690 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 692 interrupt-names = "int0", "int1"; 693 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 694 status = "disabled"; 695 }; 696 697 mcu_mcan1: can@40568000 { 698 compatible = "bosch,m_can"; 699 reg = <0x00 0x40568000 0x00 0x200>, 700 <0x00 0x40540000 0x00 0x8000>; 701 reg-names = "m_can", "message_ram"; 702 power-domains = <&k3_pds 173 TI_SCI_PD_EXCLUSIVE>; 703 clocks = <&k3_clks 173 0>, <&k3_clks 173 2>; 704 clock-names = "hclk", "cclk"; 705 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 707 interrupt-names = "int0", "int1"; 708 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 709 status = "disabled"; 710 }; 711}; 712