1// SPDX-License-Identifier: GPL-2.0-only OR MIT
2/**
3 * DT Overlay for enabling PCIE0 instances of PCIe in Endpoint Configuration
4 * on AM69-SK.
5 *
6 * AM69-SK Product Link: https://www.ti.com/tool/SK-AM69
7 *
8 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
9 */
10
11/dts-v1/;
12/plugin/;
13
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/soc/ti,sci_pm_domain.h>
16
17#include "k3-pinctrl.h"
18
19/*
20 * Since Root Complex and Endpoint modes are mutually exclusive
21 * disable Root Complex mode.
22 */
23&pcie0_rc {
24	status = "disabled";
25};
26
27&cbass_main {
28	#address-cells = <2>;
29	#size-cells = <2>;
30	interrupt-parent = <&gic500>;
31
32	pcie0_ep: pcie-ep@2900000 {
33		compatible = "ti,j784s4-pcie-ep";
34		reg = <0x00 0x02900000 0x00 0x1000>,
35		      <0x00 0x02907000 0x00 0x400>,
36		      <0x00 0x0d000000 0x00 0x00800000>,
37		      <0x00 0x10000000 0x00 0x08000000>;
38		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
39		interrupt-names = "link_state";
40		interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
41		max-link-speed = <3>;
42		num-lanes = <4>;
43		power-domains = <&k3_pds 332 TI_SCI_PD_EXCLUSIVE>;
44		clocks = <&k3_clks 332 0>;
45		clock-names = "fck";
46		max-functions = /bits/ 8 <6>;
47		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
48		dma-coherent;
49		phys = <&serdes1_pcie_link>;
50		phy-names = "pcie-phy";
51		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
52	};
53};
54