1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 PHYTEC Messtechnik GmbH 4 * Author: Wadim Egorov <[email protected]> 5 * 6 * Product homepage: 7 * https://www.phytec.com/product/phycore-am62x 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13 14/ { 15 model = "PHYTEC phyCORE-AM62x"; 16 compatible = "phytec,am62-phycore-som", "ti,am625"; 17 18 aliases { 19 ethernet0 = &cpsw_port1; 20 gpio0 = &main_gpio0; 21 gpio1 = &main_gpio1; 22 i2c0 = &main_i2c0; 23 mmc0 = &sdhci0; 24 rtc0 = &i2c_som_rtc; 25 rtc1 = &wkup_rtc0; 26 spi0 = &ospi0; 27 }; 28 29 memory@80000000 { 30 device_type = "memory"; 31 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 32 }; 33 34 reserved_memory: reserved-memory { 35 #address-cells = <2>; 36 #size-cells = <2>; 37 ranges; 38 39 ramoops@9ca00000 { 40 compatible = "ramoops"; 41 reg = <0x00 0x9ca00000 0x00 0x00100000>; 42 record-size = <0x8000>; 43 console-size = <0x8000>; 44 ftrace-size = <0x00>; 45 pmsg-size = <0x8000>; 46 }; 47 48 mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0x9cb00000 0x00 0x100000>; 51 no-map; 52 }; 53 54 mcu_m4fss_memory_region: m4f-memory@9cc00000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0x9cc00000 0x00 0xe00000>; 57 no-map; 58 }; 59 60 secure_tfa_ddr: tfa@9e780000 { 61 reg = <0x00 0x9e780000 0x00 0x80000>; 62 alignment = <0x1000>; 63 no-map; 64 }; 65 66 secure_ddr: optee@9e800000 { 67 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 68 alignment = <0x1000>; 69 no-map; 70 }; 71 72 wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0x9db00000 0x00 0x00c00000>; 75 no-map; 76 }; 77 }; 78 79 vcc_5v0_som: regulator-vcc-5v0-som { 80 compatible = "regulator-fixed"; 81 regulator-name = "VCC_5V0_SOM"; 82 regulator-min-microvolt = <5000000>; 83 regulator-max-microvolt = <5000000>; 84 regulator-always-on; 85 regulator-boot-on; 86 }; 87 88 vdd_1v8: regulator-vdd-1v8 { 89 compatible = "regulator-fixed"; 90 regulator-name = "VDD_1V8"; 91 regulator-min-microvolt = <1800000>; 92 regulator-max-microvolt = <1800000>; 93 vin-supply = <&vcc_5v0_som>; 94 regulator-always-on; 95 regulator-boot-on; 96 }; 97 98 vddshv_3v3: regulator-vddshv-3v3 { 99 compatible = "regulator-fixed"; 100 regulator-name = "VDDSHV0"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 vin-supply = <&vdd_3v3>; 104 regulator-always-on; 105 regulator-boot-on; 106 }; 107 108 leds { 109 compatible = "gpio-leds"; 110 pinctrl-names = "default"; 111 pinctrl-0 = <&leds_pins_default>; 112 113 led-0 { 114 color = <LED_COLOR_ID_GREEN>; 115 gpios = <&main_gpio0 13 GPIO_ACTIVE_HIGH>; 116 linux,default-trigger = "heartbeat"; 117 function = LED_FUNCTION_HEARTBEAT; 118 }; 119 }; 120}; 121 122&main_pmx0 { 123 leds_pins_default: leds-default-pins { 124 pinctrl-single,pins = < 125 AM62X_IOPAD(0x034, PIN_OUTPUT, 7) /* (H21) OSPI0_CSN2.GPIO0_13 */ 126 >; 127 }; 128 129 main_i2c0_pins_default: main-i2c0-default-pins { 130 pinctrl-single,pins = < 131 AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ 132 AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ 133 >; 134 }; 135 136 main_mdio1_pins_default: main-mdio1-default-pins { 137 pinctrl-single,pins = < 138 AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ 139 AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ 140 >; 141 }; 142 143 main_mmc0_pins_default: main-mmc0-default-pins { 144 pinctrl-single,pins = < 145 AM62X_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (Y3) MMC0_CMD */ 146 AM62X_IOPAD(0x218, PIN_INPUT_PULLDOWN, 0) /* (AB1) MMC0_CLK */ 147 AM62X_IOPAD(0x214, PIN_INPUT_PULLUP, 0) /* (AA2) MMC0_DAT0 */ 148 AM62X_IOPAD(0x210, PIN_INPUT_PULLUP, 0) /* (AA1) MMC0_DAT1 */ 149 AM62X_IOPAD(0x20c, PIN_INPUT_PULLUP, 0) /* (AA3) MMC0_DAT2 */ 150 AM62X_IOPAD(0x208, PIN_INPUT_PULLUP, 0) /* (Y4) MMC0_DAT3 */ 151 AM62X_IOPAD(0x204, PIN_INPUT_PULLUP, 0) /* (AB2) MMC0_DAT4 */ 152 AM62X_IOPAD(0x200, PIN_INPUT_PULLUP, 0) /* (AC1) MMC0_DAT5 */ 153 AM62X_IOPAD(0x1fc, PIN_INPUT_PULLUP, 0) /* (AD2) MMC0_DAT6 */ 154 AM62X_IOPAD(0x1f8, PIN_INPUT_PULLUP, 0) /* (AC2) MMC0_DAT7 */ 155 >; 156 }; 157 158 main_rgmii1_pins_default: main-rgmii1-default-pins { 159 pinctrl-single,pins = < 160 AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ 161 AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ 162 AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ 163 AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ 164 AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ 165 AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ 166 AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ 167 AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ 168 AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ 169 AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ 170 AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ 171 AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ 172 >; 173 }; 174 175 ospi0_pins_default: ospi0-default-pins { 176 pinctrl-single,pins = < 177 AM62X_IOPAD(0x000, PIN_OUTPUT, 0) /* (H24) OSPI0_CLK */ 178 AM62X_IOPAD(0x02c, PIN_OUTPUT, 0) /* (F23) OSPI0_CSn0 */ 179 AM62X_IOPAD(0x00c, PIN_INPUT, 0) /* (E25) OSPI0_D0 */ 180 AM62X_IOPAD(0x010, PIN_INPUT, 0) /* (G24) OSPI0_D1 */ 181 AM62X_IOPAD(0x014, PIN_INPUT, 0) /* (F25) OSPI0_D2 */ 182 AM62X_IOPAD(0x018, PIN_INPUT, 0) /* (F24) OSPI0_D3 */ 183 AM62X_IOPAD(0x01c, PIN_INPUT, 0) /* (J23) OSPI0_D4 */ 184 AM62X_IOPAD(0x020, PIN_INPUT, 0) /* (J25) OSPI0_D5 */ 185 AM62X_IOPAD(0x024, PIN_INPUT, 0) /* (H25) OSPI0_D6 */ 186 AM62X_IOPAD(0x028, PIN_INPUT, 0) /* (J22) OSPI0_D7 */ 187 AM62X_IOPAD(0x008, PIN_INPUT, 0) /* (J24) OSPI0_DQS */ 188 >; 189 }; 190 191 pmic_irq_pins_default: pmic-irq-default-pins { 192 pinctrl-single,pins = < 193 AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (D16) EXTINTn */ 194 >; 195 }; 196}; 197 198&a53_opp_table { 199 opp-1400000000 { 200 opp-hz = /bits/ 64 <1400000000>; 201 opp-supported-hw = <0x01 0x0004>; 202 }; 203}; 204 205&cpsw3g { 206 pinctrl-names = "default"; 207 pinctrl-0 = <&main_rgmii1_pins_default>; 208}; 209 210&cpsw_port1 { 211 phy-mode = "rgmii-rxid"; 212 phy-handle = <&cpsw3g_phy1>; 213}; 214 215&cpsw3g_mdio { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&main_mdio1_pins_default>; 218 status = "okay"; 219 220 cpsw3g_phy1: ethernet-phy@1 { 221 compatible = "ethernet-phy-id2000.a231", "ethernet-phy-ieee802.3-c22"; 222 reg = <1>; 223 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 224 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 225 }; 226}; 227 228&mailbox0_cluster0 { 229 mbox_m4_0: mbox-m4-0 { 230 ti,mbox-rx = <0 0 0>; 231 ti,mbox-tx = <1 0 0>; 232 }; 233}; 234 235&main_i2c0 { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&main_i2c0_pins_default>; 238 clock-frequency = <400000>; 239 status = "okay"; 240 241 pmic@30 { 242 compatible = "ti,tps65219"; 243 reg = <0x30>; 244 buck1-supply = <&vcc_5v0_som>; 245 buck2-supply = <&vcc_5v0_som>; 246 buck3-supply = <&vcc_5v0_som>; 247 ldo1-supply = <&vdd_3v3>; 248 ldo2-supply = <&vdd_1v8>; 249 ldo3-supply = <&vcc_5v0_som>; 250 ldo4-supply = <&vcc_5v0_som>; 251 252 pinctrl-names = "default"; 253 pinctrl-0 = <&pmic_irq_pins_default>; 254 interrupt-parent = <&gic500>; 255 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 256 interrupt-controller; 257 #interrupt-cells = <1>; 258 259 ti,power-button; 260 system-power-controller; 261 262 regulators { 263 vdd_core: buck1 { 264 regulator-name = "VDD_CORE"; 265 regulator-min-microvolt = <850000>; 266 regulator-max-microvolt = <850000>; 267 regulator-boot-on; 268 regulator-always-on; 269 }; 270 271 vdd_3v3: buck2 { 272 regulator-name = "VDD_3V3"; 273 regulator-min-microvolt = <3300000>; 274 regulator-max-microvolt = <3300000>; 275 regulator-boot-on; 276 regulator-always-on; 277 }; 278 279 vdd_ddr4: buck3 { 280 regulator-name = "VDD_DDR4"; 281 regulator-min-microvolt = <1200000>; 282 regulator-max-microvolt = <1200000>; 283 regulator-boot-on; 284 regulator-always-on; 285 }; 286 287 vddshv5_sdio: ldo1 { 288 regulator-name = "VDDSHV5_SDIO"; 289 regulator-min-microvolt = <3300000>; 290 regulator-max-microvolt = <3300000>; 291 regulator-allow-bypass; 292 regulator-boot-on; 293 regulator-always-on; 294 }; 295 296 vddr_core: ldo2 { 297 regulator-name = "VDDR_CORE"; 298 regulator-min-microvolt = <850000>; 299 regulator-max-microvolt = <850000>; 300 regulator-boot-on; 301 regulator-always-on; 302 }; 303 304 vdda_1v8: ldo3 { 305 regulator-name = "VDDA_1V8"; 306 regulator-min-microvolt = <1800000>; 307 regulator-max-microvolt = <1800000>; 308 regulator-boot-on; 309 regulator-always-on; 310 }; 311 312 vdd_2v5: ldo4 { 313 regulator-name = "VDD_2V5"; 314 regulator-min-microvolt = <2500000>; 315 regulator-max-microvolt = <2500000>; 316 regulator-boot-on; 317 regulator-always-on; 318 }; 319 }; 320 }; 321 322 eeprom@50 { 323 compatible = "atmel,24c32"; 324 pagesize = <32>; 325 reg = <0x50>; 326 vcc-supply = <&vddshv_3v3>; 327 }; 328 329 i2c_som_rtc: rtc@52 { 330 compatible = "microcrystal,rv3028"; 331 reg = <0x52>; 332 }; 333}; 334 335&mcu_m4fss { 336 mboxes = <&mailbox0_cluster0 &mbox_m4_0>; 337 memory-region = <&mcu_m4fss_dma_memory_region>, 338 <&mcu_m4fss_memory_region>; 339 status = "okay"; 340}; 341 342&ospi0 { 343 pinctrl-names = "default"; 344 pinctrl-0 = <&ospi0_pins_default>; 345 status = "okay"; 346 347 serial_flash: flash@0 { 348 compatible = "jedec,spi-nor"; 349 reg = <0x0>; 350 spi-tx-bus-width = <8>; 351 spi-rx-bus-width = <8>; 352 spi-max-frequency = <25000000>; 353 cdns,tshsl-ns = <60>; 354 cdns,tsd2d-ns = <60>; 355 cdns,tchsh-ns = <60>; 356 cdns,tslch-ns = <60>; 357 cdns,read-delay = <0>; 358 }; 359}; 360 361&sdhci0 { 362 pinctrl-names = "default"; 363 pinctrl-0 = <&main_mmc0_pins_default>; 364 disable-wp; 365 non-removable; 366 status = "okay"; 367}; 368