1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9	chosen {
10		stdout-path = "serial2:1500000n8";
11	};
12
13	/* Unnamed gated oscillator: 100MHz,3.3V,3225 */
14	pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
15		compatible = "gated-fixed-clock";
16		#clock-cells = <0>;
17		clock-frequency = <100000000>;
18		clock-output-names = "pcie30_refclk";
19		vdd-supply = <&vcc3v3_pi6c_05>;
20	};
21
22	vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
23		compatible = "regulator-fixed";
24		regulator-name = "vcc3v3_pcie2x1l0";
25		regulator-min-microvolt = <3300000>;
26		regulator-max-microvolt = <3300000>;
27		startup-delay-us = <5000>;
28		vin-supply = <&vcc_3v3_s3>;
29	};
30
31	vcc3v3_bkey: regulator-vcc3v3-bkey {
32		compatible = "regulator-fixed";
33		enable-active-high;
34		gpios = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; /* PCIE_4G_PWEN */
35		pinctrl-names = "default";
36		pinctrl-0 = <&pcie_4g_pwen>;
37		regulator-name = "vcc3v3_bkey";
38		regulator-min-microvolt = <3300000>;
39		regulator-max-microvolt = <3300000>;
40		startup-delay-us = <5000>;
41		vin-supply = <&vcc5v0_sys>;
42	};
43
44	vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
45		compatible = "regulator-fixed";
46		enable-active-high;
47		gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; /* PCIE30x4_PWREN_H */
48		pinctrl-names = "default";
49		pinctrl-0 = <&pcie30x4_pwren_h>;
50		regulator-name = "vcc3v3_pcie30";
51		regulator-min-microvolt = <3300000>;
52		regulator-max-microvolt = <3300000>;
53		startup-delay-us = <5000>;
54		vin-supply = <&vcc5v0_sys>;
55	};
56
57	vcc5v0_host: regulator-vcc5v0-host {
58		compatible = "regulator-fixed";
59		enable-active-high;
60		gpio = <&gpio3 RK_PC7 GPIO_ACTIVE_HIGH>;
61		pinctrl-names = "default";
62		pinctrl-0 = <&vcc5v0_host_en>;
63		regulator-name = "vcc5v0_host";
64		regulator-min-microvolt = <5000000>;
65		regulator-max-microvolt = <5000000>;
66		regulator-boot-on;
67		regulator-always-on;
68		vin-supply = <&vcc5v0_sys>;
69	};
70};
71
72&combphy0_ps {
73	status = "okay";
74};
75
76&combphy1_ps {
77	status = "okay";
78};
79
80&combphy2_psu {
81	status = "okay";
82};
83
84&i2c6 {
85	status = "okay";
86
87	hym8563: rtc@51 {
88		compatible = "haoyu,hym8563";
89		reg = <0x51>;
90		interrupt-parent = <&gpio0>;
91		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
92		#clock-cells = <0>;
93		clock-output-names = "hym8563";
94		pinctrl-names = "default";
95		pinctrl-0 = <&hym8563_int>;
96		wakeup-source;
97	};
98};
99
100/* ETH */
101&pcie2x1l0 {
102	pinctrl-names = "default";
103	pinctrl-0 = <&pcie2_0_rst>;
104	reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */
105	vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
106	status = "okay";
107};
108
109&pcie30phy {
110	data-lanes = <1 1 2 2>;
111	/* separate clock lines from the clock generator to phy and devices */
112	rockchip,rx-common-refclk-mode = <0 0 0 0>;
113	status = "okay";
114};
115
116/* M-Key */
117&pcie3x2 {
118	/*
119	 * The board has a "pcie_refclk" oscillator that needs enabling,
120	 * so add it to the list of clocks.
121	 */
122	clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
123		 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
124		 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>,
125		 <&pcie30_port1_refclk>;
126	clock-names = "aclk_mst", "aclk_slv",
127		      "aclk_dbi", "pclk",
128		      "aux", "pipe",
129		      "ref";
130	num-lanes = <2>;
131	pinctrl-names = "default";
132	pinctrl-0 = <&pcie30x2_perstn_m1_l>;
133	reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
134	vpcie3v3-supply = <&vcc3v3_pcie30>;
135	status = "okay";
136};
137
138/* B-Key and E-Key */
139&pcie3x4 {
140	/*
141	 * The board has a "pcie_refclk" oscillator that needs enabling,
142	 * so add it to the list of clocks.
143	 */
144	clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
145		 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
146		 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>,
147		 <&pcie30_port0_refclk>;
148	clock-names = "aclk_mst", "aclk_slv",
149		      "aclk_dbi", "pclk",
150		      "aux", "pipe",
151		      "ref";
152	pinctrl-names = "default";
153	pinctrl-0 = <&pcie30x4_perstn_m1_l>;
154	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
155	vpcie3v3-supply = <&vcc3v3_bkey>;
156	status = "okay";
157};
158
159&pinctrl {
160	pcie2 {
161		pcie2_0_rst: pcie2-0-rst {
162			rockchip,pins = <4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
163		};
164	};
165
166	pcie3 {
167		pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l {
168			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
169		};
170
171		pcie_4g_pwen: pcie-4g-pwen {
172			rockchip,pins = <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
173		};
174
175		pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l {
176			rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
177		};
178
179		pcie30x4_pwren_h: pcie30x4-pwren-h {
180			rockchip,pins = <2 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
181		};
182	};
183
184	hym8563 {
185		hym8563_int: hym8563-int {
186			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
187		};
188	};
189
190	usb {
191		vcc5v0_host_en: vcc5v0-host-en {
192			rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
193		};
194	};
195};
196
197/* FAN */
198&pwm2 {
199	pinctrl-0 = <&pwm2m1_pins>;
200	pinctrl-names = "default";
201	status = "okay";
202};
203
204&sata0 {
205	status = "okay";
206};
207
208&sdmmc {
209	bus-width = <4>;
210	cap-mmc-highspeed;
211	cap-sd-highspeed;
212	disable-wp;
213	no-sdio;
214	no-mmc;
215	sd-uhs-sdr104;
216	vmmc-supply = <&vcc_3v3_s3>;
217	vqmmc-supply = <&vccio_sd_s0>;
218	status = "okay";
219};
220
221&uart2 {
222	pinctrl-0 = <&uart2m0_xfer>;
223	status = "okay";
224};
225
226/* RS232 */
227&uart6 {
228	pinctrl-0 = <&uart6m0_xfer>;
229	pinctrl-names = "default";
230	status = "okay";
231};
232
233/* RS485 */
234&uart7 {
235	pinctrl-0 = <&uart7m2_xfer>;
236	pinctrl-names = "default";
237	status = "okay";
238};
239
240&u2phy2 {
241	status = "okay";
242};
243
244&u2phy2_host {
245	/* connected to USB hub, which is powered by vcc5v0_sys */
246	phy-supply = <&vcc5v0_sys>;
247	status = "okay";
248};
249
250&u2phy3 {
251	status = "okay";
252};
253
254&u2phy3_host {
255	phy-supply = <&vcc5v0_host>;
256	status = "okay";
257};
258
259&usb_host0_ehci {
260	status = "okay";
261};
262
263&usb_host0_ohci {
264	status = "okay";
265};
266
267&usb_host1_ehci {
268	status = "okay";
269};
270
271&usb_host1_ohci {
272	status = "okay";
273};
274
275&usb_host2_xhci {
276	status = "okay";
277};
278