1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rk3576-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/rockchip,rk3576-power.h> 12#include <dt-bindings/reset/rockchip,rk3576-cru.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14 15/ { 16 compatible = "rockchip,rk3576"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 i2c0 = &i2c0; 24 i2c1 = &i2c1; 25 i2c2 = &i2c2; 26 i2c3 = &i2c3; 27 i2c4 = &i2c4; 28 i2c5 = &i2c5; 29 i2c6 = &i2c6; 30 i2c7 = &i2c7; 31 i2c8 = &i2c8; 32 i2c9 = &i2c9; 33 serial0 = &uart0; 34 serial1 = &uart1; 35 serial2 = &uart2; 36 serial3 = &uart3; 37 serial4 = &uart4; 38 serial5 = &uart5; 39 serial6 = &uart6; 40 serial7 = &uart7; 41 serial8 = &uart8; 42 serial9 = &uart9; 43 serial10 = &uart10; 44 serial11 = &uart11; 45 spi0 = &spi0; 46 spi1 = &spi1; 47 spi2 = &spi2; 48 spi3 = &spi3; 49 spi4 = &spi4; 50 }; 51 52 xin32k: clock-xin32k { 53 compatible = "fixed-clock"; 54 clock-frequency = <32768>; 55 clock-output-names = "xin32k"; 56 #clock-cells = <0>; 57 }; 58 59 xin24m: clock-xin24m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <24000000>; 63 clock-output-names = "xin24m"; 64 }; 65 66 spll: clock-spll { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <702000000>; 70 clock-output-names = "spll"; 71 }; 72 73 cpus { 74 #address-cells = <1>; 75 #size-cells = <0>; 76 77 cpu-map { 78 cluster0 { 79 core0 { 80 cpu = <&cpu_l0>; 81 }; 82 core1 { 83 cpu = <&cpu_l1>; 84 }; 85 core2 { 86 cpu = <&cpu_l2>; 87 }; 88 core3 { 89 cpu = <&cpu_l3>; 90 }; 91 }; 92 cluster1 { 93 core0 { 94 cpu = <&cpu_b0>; 95 }; 96 core1 { 97 cpu = <&cpu_b1>; 98 }; 99 core2 { 100 cpu = <&cpu_b2>; 101 }; 102 core3 { 103 cpu = <&cpu_b3>; 104 }; 105 }; 106 }; 107 108 cpu_l0: cpu@0 { 109 device_type = "cpu"; 110 compatible = "arm,cortex-a53"; 111 reg = <0x0>; 112 enable-method = "psci"; 113 capacity-dmips-mhz = <485>; 114 clocks = <&scmi_clk ARMCLK_L>; 115 operating-points-v2 = <&cluster0_opp_table>; 116 #cooling-cells = <2>; 117 dynamic-power-coefficient = <120>; 118 cpu-idle-states = <&CPU_SLEEP>; 119 }; 120 121 cpu_l1: cpu@1 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a53"; 124 reg = <0x1>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <485>; 127 clocks = <&scmi_clk ARMCLK_L>; 128 operating-points-v2 = <&cluster0_opp_table>; 129 cpu-idle-states = <&CPU_SLEEP>; 130 }; 131 132 cpu_l2: cpu@2 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a53"; 135 reg = <0x2>; 136 enable-method = "psci"; 137 capacity-dmips-mhz = <485>; 138 clocks = <&scmi_clk ARMCLK_L>; 139 operating-points-v2 = <&cluster0_opp_table>; 140 cpu-idle-states = <&CPU_SLEEP>; 141 }; 142 143 cpu_l3: cpu@3 { 144 device_type = "cpu"; 145 compatible = "arm,cortex-a53"; 146 reg = <0x3>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <485>; 149 clocks = <&scmi_clk ARMCLK_L>; 150 operating-points-v2 = <&cluster0_opp_table>; 151 cpu-idle-states = <&CPU_SLEEP>; 152 }; 153 154 cpu_b0: cpu@100 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a72"; 157 reg = <0x100>; 158 enable-method = "psci"; 159 capacity-dmips-mhz = <1024>; 160 clocks = <&scmi_clk ARMCLK_B>; 161 operating-points-v2 = <&cluster1_opp_table>; 162 #cooling-cells = <2>; 163 dynamic-power-coefficient = <320>; 164 cpu-idle-states = <&CPU_SLEEP>; 165 }; 166 167 cpu_b1: cpu@101 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a72"; 170 reg = <0x101>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <1024>; 173 clocks = <&scmi_clk ARMCLK_B>; 174 operating-points-v2 = <&cluster1_opp_table>; 175 cpu-idle-states = <&CPU_SLEEP>; 176 }; 177 178 cpu_b2: cpu@102 { 179 device_type = "cpu"; 180 compatible = "arm,cortex-a72"; 181 reg = <0x102>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <1024>; 184 clocks = <&scmi_clk ARMCLK_B>; 185 operating-points-v2 = <&cluster1_opp_table>; 186 cpu-idle-states = <&CPU_SLEEP>; 187 }; 188 189 cpu_b3: cpu@103 { 190 device_type = "cpu"; 191 compatible = "arm,cortex-a72"; 192 reg = <0x103>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 clocks = <&scmi_clk ARMCLK_B>; 196 operating-points-v2 = <&cluster1_opp_table>; 197 cpu-idle-states = <&CPU_SLEEP>; 198 }; 199 200 idle-states { 201 entry-method = "psci"; 202 203 CPU_SLEEP: cpu-sleep { 204 compatible = "arm,idle-state"; 205 arm,psci-suspend-param = <0x0010000>; 206 entry-latency-us = <120>; 207 exit-latency-us = <250>; 208 min-residency-us = <900>; 209 local-timer-stop; 210 }; 211 }; 212 }; 213 214 cluster0_opp_table: opp-table-cluster0 { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 218 opp-408000000 { 219 opp-hz = /bits/ 64 <408000000>; 220 opp-microvolt = <700000 700000 950000>; 221 clock-latency-ns = <40000>; 222 }; 223 224 opp-600000000 { 225 opp-hz = /bits/ 64 <600000000>; 226 opp-microvolt = <700000 700000 950000>; 227 clock-latency-ns = <40000>; 228 }; 229 230 opp-816000000 { 231 opp-hz = /bits/ 64 <816000000>; 232 opp-microvolt = <700000 700000 950000>; 233 clock-latency-ns = <40000>; 234 }; 235 236 opp-1008000000 { 237 opp-hz = /bits/ 64 <1008000000>; 238 opp-microvolt = <700000 700000 950000>; 239 clock-latency-ns = <40000>; 240 }; 241 242 opp-1200000000 { 243 opp-hz = /bits/ 64 <1200000000>; 244 opp-microvolt = <700000 700000 950000>; 245 clock-latency-ns = <40000>; 246 }; 247 248 opp-1416000000 { 249 opp-hz = /bits/ 64 <1416000000>; 250 opp-microvolt = <725000 725000 950000>; 251 clock-latency-ns = <40000>; 252 }; 253 254 opp-1608000000 { 255 opp-hz = /bits/ 64 <1608000000>; 256 opp-microvolt = <750000 750000 950000>; 257 clock-latency-ns = <40000>; 258 }; 259 260 opp-1800000000 { 261 opp-hz = /bits/ 64 <1800000000>; 262 opp-microvolt = <825000 825000 950000>; 263 clock-latency-ns = <40000>; 264 opp-suspend; 265 }; 266 267 opp-2016000000 { 268 opp-hz = /bits/ 64 <2016000000>; 269 opp-microvolt = <900000 900000 950000>; 270 clock-latency-ns = <40000>; 271 }; 272 273 opp-2208000000 { 274 opp-hz = /bits/ 64 <2208000000>; 275 opp-microvolt = <950000 950000 950000>; 276 clock-latency-ns = <40000>; 277 }; 278 }; 279 280 cluster1_opp_table: opp-table-cluster1 { 281 compatible = "operating-points-v2"; 282 opp-shared; 283 284 opp-408000000 { 285 opp-hz = /bits/ 64 <408000000>; 286 opp-microvolt = <700000 700000 950000>; 287 clock-latency-ns = <40000>; 288 opp-suspend; 289 }; 290 291 opp-600000000 { 292 opp-hz = /bits/ 64 <600000000>; 293 opp-microvolt = <700000 700000 950000>; 294 clock-latency-ns = <40000>; 295 }; 296 297 opp-816000000 { 298 opp-hz = /bits/ 64 <816000000>; 299 opp-microvolt = <700000 700000 950000>; 300 clock-latency-ns = <40000>; 301 }; 302 303 opp-1008000000 { 304 opp-hz = /bits/ 64 <1008000000>; 305 opp-microvolt = <700000 700000 950000>; 306 clock-latency-ns = <40000>; 307 }; 308 309 opp-1200000000 { 310 opp-hz = /bits/ 64 <1200000000>; 311 opp-microvolt = <700000 700000 950000>; 312 clock-latency-ns = <40000>; 313 }; 314 315 opp-1416000000 { 316 opp-hz = /bits/ 64 <1416000000>; 317 opp-microvolt = <712500 712500 950000>; 318 clock-latency-ns = <40000>; 319 }; 320 321 opp-1608000000 { 322 opp-hz = /bits/ 64 <1608000000>; 323 opp-microvolt = <737500 737500 950000>; 324 clock-latency-ns = <40000>; 325 }; 326 327 opp-1800000000 { 328 opp-hz = /bits/ 64 <1800000000>; 329 opp-microvolt = <800000 800000 950000>; 330 clock-latency-ns = <40000>; 331 }; 332 333 opp-2016000000 { 334 opp-hz = /bits/ 64 <2016000000>; 335 opp-microvolt = <862500 862500 950000>; 336 clock-latency-ns = <40000>; 337 }; 338 339 opp-2208000000 { 340 opp-hz = /bits/ 64 <2208000000>; 341 opp-microvolt = <925000 925000 950000>; 342 clock-latency-ns = <40000>; 343 }; 344 345 opp-2304000000 { 346 opp-hz = /bits/ 64 <2304000000>; 347 opp-microvolt = <950000 950000 950000>; 348 clock-latency-ns = <40000>; 349 }; 350 }; 351 352 gpu_opp_table: opp-table-gpu { 353 compatible = "operating-points-v2"; 354 355 opp-300000000 { 356 opp-hz = /bits/ 64 <300000000>; 357 opp-microvolt = <700000 700000 850000>; 358 }; 359 360 opp-400000000 { 361 opp-hz = /bits/ 64 <400000000>; 362 opp-microvolt = <700000 700000 850000>; 363 }; 364 365 opp-500000000 { 366 opp-hz = /bits/ 64 <500000000>; 367 opp-microvolt = <700000 700000 850000>; 368 }; 369 370 opp-600000000 { 371 opp-hz = /bits/ 64 <600000000>; 372 opp-microvolt = <700000 700000 850000>; 373 }; 374 375 opp-700000000 { 376 opp-hz = /bits/ 64 <700000000>; 377 opp-microvolt = <725000 725000 850000>; 378 }; 379 380 opp-800000000 { 381 opp-hz = /bits/ 64 <800000000>; 382 opp-microvolt = <775000 775000 850000>; 383 }; 384 385 opp-900000000 { 386 opp-hz = /bits/ 64 <900000000>; 387 opp-microvolt = <825000 825000 850000>; 388 }; 389 390 opp-950000000 { 391 opp-hz = /bits/ 64 <950000000>; 392 opp-microvolt = <850000 850000 850000>; 393 }; 394 }; 395 396 firmware { 397 scmi: scmi { 398 compatible = "arm,scmi-smc"; 399 arm,smc-id = <0x82000010>; 400 shmem = <&scmi_shmem>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 404 scmi_clk: protocol@14 { 405 reg = <0x14>; 406 #clock-cells = <1>; 407 }; 408 }; 409 }; 410 411 pmu_a53: pmu-a53 { 412 compatible = "arm,cortex-a53-pmu"; 413 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 415 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 416 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 417 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>; 418 }; 419 420 pmu_a72: pmu-a72 { 421 compatible = "arm,cortex-a72-pmu"; 422 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-affinity = <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 427 }; 428 429 psci { 430 compatible = "arm,psci-1.0"; 431 method = "smc"; 432 }; 433 434 timer { 435 compatible = "arm,armv8-timer"; 436 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 437 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 438 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 439 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 440 }; 441 442 soc { 443 compatible = "simple-bus"; 444 #address-cells = <2>; 445 #size-cells = <2>; 446 ranges; 447 448 usb_drd0_dwc3: usb@23000000 { 449 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 450 reg = <0x0 0x23000000 0x0 0x400000>; 451 clocks = <&cru CLK_REF_USB3OTG0>, 452 <&cru CLK_SUSPEND_USB3OTG0>, 453 <&cru ACLK_USB3OTG0>; 454 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 455 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 456 power-domains = <&power RK3576_PD_USB>; 457 resets = <&cru SRST_A_USB3OTG0>; 458 dr_mode = "otg"; 459 phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>; 460 phy-names = "usb2-phy", "usb3-phy"; 461 phy_type = "utmi_wide"; 462 snps,dis_enblslpm_quirk; 463 snps,dis-u1-entry-quirk; 464 snps,dis-u2-entry-quirk; 465 snps,dis-u2-freeclk-exists-quirk; 466 snps,dis-del-phy-power-chg-quirk; 467 snps,dis-tx-ipgap-linecheck-quirk; 468 snps,parkmode-disable-hs-quirk; 469 snps,parkmode-disable-ss-quirk; 470 status = "disabled"; 471 }; 472 473 usb_drd1_dwc3: usb@23400000 { 474 compatible = "rockchip,rk3576-dwc3", "snps,dwc3"; 475 reg = <0x0 0x23400000 0x0 0x400000>; 476 clocks = <&cru CLK_REF_USB3OTG1>, 477 <&cru CLK_SUSPEND_USB3OTG1>, 478 <&cru ACLK_USB3OTG1>; 479 clock-names = "ref_clk", "suspend_clk", "bus_clk"; 480 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 481 power-domains = <&power RK3576_PD_PHP>; 482 resets = <&cru SRST_A_USB3OTG1>; 483 dr_mode = "otg"; 484 phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>; 485 phy-names = "usb2-phy", "usb3-phy"; 486 phy_type = "utmi_wide"; 487 snps,dis_enblslpm_quirk; 488 snps,dis-u1-entry-quirk; 489 snps,dis-u2-entry-quirk; 490 snps,dis-u2-freeclk-exists-quirk; 491 snps,dis-del-phy-power-chg-quirk; 492 snps,dis-tx-ipgap-linecheck-quirk; 493 snps,dis_rxdet_inp3_quirk; 494 snps,parkmode-disable-hs-quirk; 495 snps,parkmode-disable-ss-quirk; 496 dma-coherent; 497 status = "disabled"; 498 }; 499 500 sys_grf: syscon@2600a000 { 501 compatible = "rockchip,rk3576-sys-grf", "syscon"; 502 reg = <0x0 0x2600a000 0x0 0x2000>; 503 }; 504 505 bigcore_grf: syscon@2600c000 { 506 compatible = "rockchip,rk3576-bigcore-grf", "syscon"; 507 reg = <0x0 0x2600c000 0x0 0x2000>; 508 }; 509 510 litcore_grf: syscon@2600e000 { 511 compatible = "rockchip,rk3576-litcore-grf", "syscon"; 512 reg = <0x0 0x2600e000 0x0 0x2000>; 513 }; 514 515 cci_grf: syscon@26010000 { 516 compatible = "rockchip,rk3576-cci-grf", "syscon"; 517 reg = <0x0 0x26010000 0x0 0x2000>; 518 }; 519 520 gpu_grf: syscon@26016000 { 521 compatible = "rockchip,rk3576-gpu-grf", "syscon"; 522 reg = <0x0 0x26016000 0x0 0x2000>; 523 }; 524 525 npu_grf: syscon@26018000 { 526 compatible = "rockchip,rk3576-npu-grf", "syscon"; 527 reg = <0x0 0x26018000 0x0 0x2000>; 528 }; 529 530 vo0_grf: syscon@2601a000 { 531 compatible = "rockchip,rk3576-vo0-grf", "syscon"; 532 reg = <0x0 0x2601a000 0x0 0x2000>; 533 }; 534 535 usb_grf: syscon@2601e000 { 536 compatible = "rockchip,rk3576-usb-grf", "syscon"; 537 reg = <0x0 0x2601e000 0x0 0x1000>; 538 }; 539 540 php_grf: syscon@26020000 { 541 compatible = "rockchip,rk3576-php-grf", "syscon"; 542 reg = <0x0 0x26020000 0x0 0x2000>; 543 }; 544 545 pmu0_grf: syscon@26024000 { 546 compatible = "rockchip,rk3576-pmu0-grf", "syscon", "simple-mfd"; 547 reg = <0x0 0x26024000 0x0 0x1000>; 548 }; 549 550 pmu1_grf: syscon@26026000 { 551 compatible = "rockchip,rk3576-pmu1-grf", "syscon"; 552 reg = <0x0 0x26026000 0x0 0x1000>; 553 }; 554 555 pipe_phy0_grf: syscon@26028000 { 556 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 557 reg = <0x0 0x26028000 0x0 0x2000>; 558 }; 559 560 pipe_phy1_grf: syscon@2602a000 { 561 compatible = "rockchip,rk3576-pipe-phy-grf", "syscon"; 562 reg = <0x0 0x2602a000 0x0 0x2000>; 563 }; 564 565 usbdpphy_grf: syscon@2602c000 { 566 compatible = "rockchip,rk3576-usbdpphy-grf", "syscon"; 567 reg = <0x0 0x2602c000 0x0 0x2000>; 568 }; 569 570 usb2phy_grf: syscon@2602e000 { 571 compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd"; 572 reg = <0x0 0x2602e000 0x0 0x4000>; 573 #address-cells = <1>; 574 #size-cells = <1>; 575 576 u2phy0: usb2-phy@0 { 577 compatible = "rockchip,rk3576-usb2phy"; 578 reg = <0x0 0x10>; 579 resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>; 580 reset-names = "phy", "apb"; 581 clocks = <&cru CLK_PHY_REF_SRC>, 582 <&cru ACLK_MMU2>, 583 <&cru ACLK_SLV_MMU2>; 584 clock-names = "phyclk", "aclk", "aclk_slv"; 585 clock-output-names = "usb480m_phy0"; 586 #clock-cells = <0>; 587 status = "disabled"; 588 589 u2phy0_otg: otg-port { 590 #phy-cells = <0>; 591 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 595 status = "disabled"; 596 }; 597 }; 598 599 u2phy1: usb2-phy@2000 { 600 compatible = "rockchip,rk3576-usb2phy"; 601 reg = <0x2000 0x10>; 602 resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>; 603 reset-names = "phy", "apb"; 604 clocks = <&cru CLK_PHY_REF_SRC>, 605 <&cru ACLK_MMU1>, 606 <&cru ACLK_SLV_MMU1>; 607 clock-names = "phyclk", "aclk", "aclk_slv"; 608 clock-output-names = "usb480m_phy1"; 609 #clock-cells = <0>; 610 status = "disabled"; 611 612 u2phy1_otg: otg-port { 613 #phy-cells = <0>; 614 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 617 interrupt-names = "otg-bvalid", "otg-id", "linestate"; 618 status = "disabled"; 619 }; 620 }; 621 }; 622 623 vo1_grf: syscon@26036000 { 624 compatible = "rockchip,rk3576-vo1-grf", "syscon"; 625 reg = <0x0 0x26036000 0x0 0x100>; 626 clocks = <&cru PCLK_VO1_ROOT>; 627 }; 628 629 sdgmac_grf: syscon@26038000 { 630 compatible = "rockchip,rk3576-sdgmac-grf", "syscon"; 631 reg = <0x0 0x26038000 0x0 0x1000>; 632 }; 633 634 ioc_grf: syscon@26040000 { 635 compatible = "rockchip,rk3576-ioc-grf", "syscon", "simple-mfd"; 636 reg = <0x0 0x26040000 0x0 0xc000>; 637 }; 638 639 cru: clock-controller@27200000 { 640 compatible = "rockchip,rk3576-cru"; 641 reg = <0x0 0x27200000 0x0 0x50000>; 642 #clock-cells = <1>; 643 #reset-cells = <1>; 644 645 assigned-clocks = 646 <&cru CLK_AUDIO_FRAC_1_SRC>, 647 <&cru PLL_GPLL>, <&cru PLL_CPLL>, 648 <&cru PLL_AUPLL>, <&cru CLK_UART_FRAC_0>, 649 <&cru CLK_UART_FRAC_1>, <&cru CLK_UART_FRAC_2>, 650 <&cru CLK_AUDIO_FRAC_0>, <&cru CLK_AUDIO_FRAC_1>, 651 <&cru CLK_CPLL_DIV2>, <&cru CLK_CPLL_DIV4>, 652 <&cru CLK_CPLL_DIV10>, <&cru FCLK_DDR_CM0_CORE>, 653 <&cru ACLK_PHP_ROOT>; 654 assigned-clock-parents = <&cru PLL_AUPLL>; 655 assigned-clock-rates = 656 <0>, 657 <1188000000>, <1000000000>, 658 <786432000>, <18432000>, 659 <96000000>, <128000000>, 660 <45158400>, <49152000>, 661 <500000000>, <250000000>, 662 <100000000>, <500000000>, 663 <250000000>; 664 }; 665 666 i2c0: i2c@27300000 { 667 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 668 reg = <0x0 0x27300000 0x0 0x1000>; 669 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 670 clock-names = "i2c", "pclk"; 671 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 672 pinctrl-names = "default"; 673 pinctrl-0 = <&i2c0m0_xfer>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 status = "disabled"; 677 }; 678 679 uart1: serial@27310000 { 680 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 681 reg = <0x0 0x27310000 0x0 0x100>; 682 reg-shift = <2>; 683 reg-io-width = <4>; 684 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 685 clock-names = "baudclk", "apb_pclk"; 686 dmas = <&dmac0 8>, <&dmac0 9>; 687 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 688 pinctrl-names = "default"; 689 pinctrl-0 = <&uart1m0_xfer>; 690 status = "disabled"; 691 }; 692 693 pmu: power-management@27380000 { 694 compatible = "rockchip,rk3576-pmu", "syscon", "simple-mfd"; 695 reg = <0x0 0x27380000 0x0 0x800>; 696 697 power: power-controller { 698 compatible = "rockchip,rk3576-power-controller"; 699 #power-domain-cells = <1>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 703 power-domain@RK3576_PD_NPU { 704 reg = <RK3576_PD_NPU>; 705 #power-domain-cells = <1>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 709 power-domain@RK3576_PD_NPUTOP { 710 reg = <RK3576_PD_NPUTOP>; 711 clocks = <&cru ACLK_RKNN0>, 712 <&cru ACLK_RKNN1>, 713 <&cru ACLK_RKNN_CBUF>, 714 <&cru CLK_RKNN_DSU0>, 715 <&cru HCLK_RKNN_CBUF>, 716 <&cru HCLK_RKNN_ROOT>, 717 <&cru HCLK_NPU_CM0_ROOT>, 718 <&cru PCLK_NPUTOP_ROOT>; 719 pm_qos = <&qos_npu_mcu>, 720 <&qos_npu_nsp0>, 721 <&qos_npu_nsp1>, 722 <&qos_npu_m0ro>, 723 <&qos_npu_m1ro>; 724 #power-domain-cells = <1>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 728 power-domain@RK3576_PD_NPU0 { 729 reg = <RK3576_PD_NPU0>; 730 clocks = <&cru HCLK_RKNN_ROOT>, 731 <&cru ACLK_RKNN0>; 732 pm_qos = <&qos_npu_m0>; 733 #power-domain-cells = <0>; 734 }; 735 power-domain@RK3576_PD_NPU1 { 736 reg = <RK3576_PD_NPU1>; 737 clocks = <&cru HCLK_RKNN_ROOT>, 738 <&cru ACLK_RKNN1>; 739 pm_qos = <&qos_npu_m1>; 740 #power-domain-cells = <0>; 741 }; 742 }; 743 }; 744 745 power-domain@RK3576_PD_GPU { 746 reg = <RK3576_PD_GPU>; 747 clocks = <&cru CLK_GPU>, <&cru PCLK_GPU_ROOT>; 748 pm_qos = <&qos_gpu>; 749 #power-domain-cells = <0>; 750 }; 751 752 power-domain@RK3576_PD_NVM { 753 reg = <RK3576_PD_NVM>; 754 clocks = <&cru ACLK_EMMC>, <&cru HCLK_EMMC>; 755 pm_qos = <&qos_emmc>, 756 <&qos_fspi0>; 757 #power-domain-cells = <1>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 power-domain@RK3576_PD_SDGMAC { 762 reg = <RK3576_PD_SDGMAC>; 763 clocks = <&cru ACLK_HSGPIO>, 764 <&cru ACLK_GMAC0>, 765 <&cru ACLK_GMAC1>, 766 <&cru CCLK_SRC_SDIO>, 767 <&cru CCLK_SRC_SDMMC0>, 768 <&cru HCLK_HSGPIO>, 769 <&cru HCLK_SDIO>, 770 <&cru HCLK_SDMMC0>, 771 <&cru PCLK_SDGMAC_ROOT>; 772 pm_qos = <&qos_fspi1>, 773 <&qos_gmac0>, 774 <&qos_gmac1>, 775 <&qos_sdio>, 776 <&qos_sdmmc>, 777 <&qos_flexbus>; 778 #power-domain-cells = <0>; 779 }; 780 }; 781 782 power-domain@RK3576_PD_PHP { 783 reg = <RK3576_PD_PHP>; 784 clocks = <&cru ACLK_PHP_ROOT>, 785 <&cru PCLK_PHP_ROOT>, 786 <&cru ACLK_MMU0>, 787 <&cru ACLK_MMU1>; 788 pm_qos = <&qos_mmu0>, 789 <&qos_mmu1>; 790 #power-domain-cells = <1>; 791 #address-cells = <1>; 792 #size-cells = <0>; 793 794 power-domain@RK3576_PD_SUBPHP { 795 reg = <RK3576_PD_SUBPHP>; 796 #power-domain-cells = <0>; 797 }; 798 }; 799 800 power-domain@RK3576_PD_AUDIO { 801 reg = <RK3576_PD_AUDIO>; 802 #power-domain-cells = <0>; 803 }; 804 805 power-domain@RK3576_PD_VEPU1 { 806 reg = <RK3576_PD_VEPU1>; 807 clocks = <&cru ACLK_VEPU1>, 808 <&cru HCLK_VEPU1>; 809 pm_qos = <&qos_vepu1>; 810 #power-domain-cells = <0>; 811 }; 812 813 power-domain@RK3576_PD_VPU { 814 reg = <RK3576_PD_VPU>; 815 clocks = <&cru ACLK_EBC>, 816 <&cru HCLK_EBC>, 817 <&cru ACLK_JPEG>, 818 <&cru HCLK_JPEG>, 819 <&cru ACLK_RGA2E_0>, 820 <&cru HCLK_RGA2E_0>, 821 <&cru ACLK_RGA2E_1>, 822 <&cru HCLK_RGA2E_1>, 823 <&cru ACLK_VDPP>, 824 <&cru HCLK_VDPP>; 825 pm_qos = <&qos_ebc>, 826 <&qos_jpeg>, 827 <&qos_rga0>, 828 <&qos_rga1>, 829 <&qos_vdpp>; 830 #power-domain-cells = <0>; 831 }; 832 833 power-domain@RK3576_PD_VDEC { 834 reg = <RK3576_PD_VDEC>; 835 clocks = <&cru ACLK_RKVDEC_ROOT>, 836 <&cru HCLK_RKVDEC>; 837 pm_qos = <&qos_rkvdec>; 838 #power-domain-cells = <0>; 839 }; 840 841 power-domain@RK3576_PD_VI { 842 reg = <RK3576_PD_VI>; 843 clocks = <&cru ACLK_VICAP>, 844 <&cru HCLK_VICAP>, 845 <&cru DCLK_VICAP>, 846 <&cru ACLK_VI_ROOT>, 847 <&cru HCLK_VI_ROOT>, 848 <&cru PCLK_VI_ROOT>, 849 <&cru CLK_ISP_CORE>, 850 <&cru ACLK_ISP>, 851 <&cru HCLK_ISP>, 852 <&cru CLK_CORE_VPSS>, 853 <&cru ACLK_VPSS>, 854 <&cru HCLK_VPSS>; 855 pm_qos = <&qos_isp_mro>, 856 <&qos_isp_mwo>, 857 <&qos_vicap_m0>, 858 <&qos_vpss_mro>, 859 <&qos_vpss_mwo>; 860 #power-domain-cells = <1>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 864 power-domain@RK3576_PD_VEPU0 { 865 reg = <RK3576_PD_VEPU0>; 866 clocks = <&cru ACLK_VEPU0>, 867 <&cru HCLK_VEPU0>; 868 pm_qos = <&qos_vepu0>; 869 #power-domain-cells = <0>; 870 }; 871 }; 872 873 power-domain@RK3576_PD_VOP { 874 reg = <RK3576_PD_VOP>; 875 clocks = <&cru ACLK_VOP>, 876 <&cru HCLK_VOP>, 877 <&cru HCLK_VOP_ROOT>, 878 <&cru PCLK_VOP_ROOT>; 879 pm_qos = <&qos_vop_m0>, 880 <&qos_vop_m1ro>; 881 #power-domain-cells = <1>; 882 #address-cells = <1>; 883 #size-cells = <0>; 884 885 power-domain@RK3576_PD_USB { 886 reg = <RK3576_PD_USB>; 887 clocks = <&cru PCLK_PHP_ROOT>, 888 <&cru ACLK_USB_ROOT>, 889 <&cru ACLK_MMU2>, 890 <&cru ACLK_SLV_MMU2>, 891 <&cru ACLK_UFS_SYS>; 892 pm_qos = <&qos_mmu2>, 893 <&qos_ufshc>; 894 #power-domain-cells = <0>; 895 }; 896 897 power-domain@RK3576_PD_VO0 { 898 reg = <RK3576_PD_VO0>; 899 clocks = <&cru ACLK_HDCP0>, 900 <&cru HCLK_HDCP0>, 901 <&cru ACLK_VO0_ROOT>, 902 <&cru PCLK_VO0_ROOT>, 903 <&cru HCLK_VOP_ROOT>; 904 pm_qos = <&qos_hdcp0>; 905 #power-domain-cells = <0>; 906 }; 907 908 power-domain@RK3576_PD_VO1 { 909 reg = <RK3576_PD_VO1>; 910 clocks = <&cru ACLK_HDCP1>, 911 <&cru HCLK_HDCP1>, 912 <&cru ACLK_VO1_ROOT>, 913 <&cru PCLK_VO1_ROOT>, 914 <&cru HCLK_VOP_ROOT>; 915 pm_qos = <&qos_hdcp1>; 916 #power-domain-cells = <0>; 917 }; 918 }; 919 }; 920 }; 921 922 gpu: gpu@27800000 { 923 compatible = "rockchip,rk3576-mali", "arm,mali-bifrost"; 924 reg = <0x0 0x27800000 0x0 0x200000>; 925 assigned-clocks = <&scmi_clk CLK_GPU>; 926 assigned-clock-rates = <198000000>; 927 clocks = <&cru CLK_GPU>; 928 clock-names = "core"; 929 dynamic-power-coefficient = <1625>; 930 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 933 interrupt-names = "job", "mmu", "gpu"; 934 operating-points-v2 = <&gpu_opp_table>; 935 power-domains = <&power RK3576_PD_GPU>; 936 #cooling-cells = <2>; 937 status = "disabled"; 938 }; 939 940 qos_hdcp1: qos@27f02000 { 941 compatible = "rockchip,rk3576-qos", "syscon"; 942 reg = <0x0 0x27f02000 0x0 0x20>; 943 }; 944 945 qos_fspi1: qos@27f04000 { 946 compatible = "rockchip,rk3576-qos", "syscon"; 947 reg = <0x0 0x27f04000 0x0 0x20>; 948 }; 949 950 qos_gmac0: qos@27f04080 { 951 compatible = "rockchip,rk3576-qos", "syscon"; 952 reg = <0x0 0x27f04080 0x0 0x20>; 953 }; 954 955 qos_gmac1: qos@27f04100 { 956 compatible = "rockchip,rk3576-qos", "syscon"; 957 reg = <0x0 0x27f04100 0x0 0x20>; 958 }; 959 960 qos_sdio: qos@27f04180 { 961 compatible = "rockchip,rk3576-qos", "syscon"; 962 reg = <0x0 0x27f04180 0x0 0x20>; 963 }; 964 965 qos_sdmmc: qos@27f04200 { 966 compatible = "rockchip,rk3576-qos", "syscon"; 967 reg = <0x0 0x27f04200 0x0 0x20>; 968 }; 969 970 qos_flexbus: qos@27f04280 { 971 compatible = "rockchip,rk3576-qos", "syscon"; 972 reg = <0x0 0x27f04280 0x0 0x20>; 973 }; 974 975 qos_gpu: qos@27f05000 { 976 compatible = "rockchip,rk3576-qos", "syscon"; 977 reg = <0x0 0x27f05000 0x0 0x20>; 978 }; 979 980 qos_vepu1: qos@27f06000 { 981 compatible = "rockchip,rk3576-qos", "syscon"; 982 reg = <0x0 0x27f06000 0x0 0x20>; 983 }; 984 985 qos_npu_mcu: qos@27f08000 { 986 compatible = "rockchip,rk3576-qos", "syscon"; 987 reg = <0x0 0x27f08000 0x0 0x20>; 988 }; 989 990 qos_npu_nsp0: qos@27f08080 { 991 compatible = "rockchip,rk3576-qos", "syscon"; 992 reg = <0x0 0x27f08080 0x0 0x20>; 993 }; 994 995 qos_npu_nsp1: qos@27f08100 { 996 compatible = "rockchip,rk3576-qos", "syscon"; 997 reg = <0x0 0x27f08100 0x0 0x20>; 998 }; 999 1000 qos_emmc: qos@27f09000 { 1001 compatible = "rockchip,rk3576-qos", "syscon"; 1002 reg = <0x0 0x27f09000 0x0 0x20>; 1003 }; 1004 1005 qos_fspi0: qos@27f09080 { 1006 compatible = "rockchip,rk3576-qos", "syscon"; 1007 reg = <0x0 0x27f09080 0x0 0x20>; 1008 }; 1009 1010 qos_mmu0: qos@27f0a000 { 1011 compatible = "rockchip,rk3576-qos", "syscon"; 1012 reg = <0x0 0x27f0a000 0x0 0x20>; 1013 }; 1014 1015 qos_mmu1: qos@27f0a080 { 1016 compatible = "rockchip,rk3576-qos", "syscon"; 1017 reg = <0x0 0x27f0a080 0x0 0x20>; 1018 }; 1019 1020 qos_rkvdec: qos@27f0c000 { 1021 compatible = "rockchip,rk3576-qos", "syscon"; 1022 reg = <0x0 0x27f0c000 0x0 0x20>; 1023 }; 1024 1025 qos_crypto: qos@27f0d000 { 1026 compatible = "rockchip,rk3576-qos", "syscon"; 1027 reg = <0x0 0x27f0d000 0x0 0x20>; 1028 }; 1029 1030 qos_mmu2: qos@27f0e000 { 1031 compatible = "rockchip,rk3576-qos", "syscon"; 1032 reg = <0x0 0x27f0e000 0x0 0x20>; 1033 }; 1034 1035 qos_ufshc: qos@27f0e080 { 1036 compatible = "rockchip,rk3576-qos", "syscon"; 1037 reg = <0x0 0x27f0e080 0x0 0x20>; 1038 }; 1039 1040 qos_vepu0: qos@27f0f000 { 1041 compatible = "rockchip,rk3576-qos", "syscon"; 1042 reg = <0x0 0x27f0f000 0x0 0x20>; 1043 }; 1044 1045 qos_isp_mro: qos@27f10000 { 1046 compatible = "rockchip,rk3576-qos", "syscon"; 1047 reg = <0x0 0x27f10000 0x0 0x20>; 1048 }; 1049 1050 qos_isp_mwo: qos@27f10080 { 1051 compatible = "rockchip,rk3576-qos", "syscon"; 1052 reg = <0x0 0x27f10080 0x0 0x20>; 1053 }; 1054 1055 qos_vicap_m0: qos@27f10100 { 1056 compatible = "rockchip,rk3576-qos", "syscon"; 1057 reg = <0x0 0x27f10100 0x0 0x20>; 1058 }; 1059 1060 qos_vpss_mro: qos@27f10180 { 1061 compatible = "rockchip,rk3576-qos", "syscon"; 1062 reg = <0x0 0x27f10180 0x0 0x20>; 1063 }; 1064 1065 qos_vpss_mwo: qos@27f10200 { 1066 compatible = "rockchip,rk3576-qos", "syscon"; 1067 reg = <0x0 0x27f10200 0x0 0x20>; 1068 }; 1069 1070 qos_hdcp0: qos@27f11000 { 1071 compatible = "rockchip,rk3576-qos", "syscon"; 1072 reg = <0x0 0x27f11000 0x0 0x20>; 1073 }; 1074 1075 qos_vop_m0: qos@27f12800 { 1076 compatible = "rockchip,rk3576-qos", "syscon"; 1077 reg = <0x0 0x27f12800 0x0 0x20>; 1078 }; 1079 1080 qos_vop_m1ro: qos@27f12880 { 1081 compatible = "rockchip,rk3576-qos", "syscon"; 1082 reg = <0x0 0x27f12880 0x0 0x20>; 1083 }; 1084 1085 qos_ebc: qos@27f13000 { 1086 compatible = "rockchip,rk3576-qos", "syscon"; 1087 reg = <0x0 0x27f13000 0x0 0x20>; 1088 }; 1089 1090 qos_rga0: qos@27f13080 { 1091 compatible = "rockchip,rk3576-qos", "syscon"; 1092 reg = <0x0 0x27f13080 0x0 0x20>; 1093 }; 1094 1095 qos_rga1: qos@27f13100 { 1096 compatible = "rockchip,rk3576-qos", "syscon"; 1097 reg = <0x0 0x27f13100 0x0 0x20>; 1098 }; 1099 1100 qos_jpeg: qos@27f13180 { 1101 compatible = "rockchip,rk3576-qos", "syscon"; 1102 reg = <0x0 0x27f13180 0x0 0x20>; 1103 }; 1104 1105 qos_vdpp: qos@27f13200 { 1106 compatible = "rockchip,rk3576-qos", "syscon"; 1107 reg = <0x0 0x27f13200 0x0 0x20>; 1108 }; 1109 1110 qos_npu_m0: qos@27f20000 { 1111 compatible = "rockchip,rk3576-qos", "syscon"; 1112 reg = <0x0 0x27f20000 0x0 0x20>; 1113 }; 1114 1115 qos_npu_m1: qos@27f21000 { 1116 compatible = "rockchip,rk3576-qos", "syscon"; 1117 reg = <0x0 0x27f21000 0x0 0x20>; 1118 }; 1119 1120 qos_npu_m0ro: qos@27f22080 { 1121 compatible = "rockchip,rk3576-qos", "syscon"; 1122 reg = <0x0 0x27f22080 0x0 0x20>; 1123 }; 1124 1125 qos_npu_m1ro: qos@27f22100 { 1126 compatible = "rockchip,rk3576-qos", "syscon"; 1127 reg = <0x0 0x27f22100 0x0 0x20>; 1128 }; 1129 1130 gmac0: ethernet@2a220000 { 1131 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1132 reg = <0x0 0x2a220000 0x0 0x10000>; 1133 clocks = <&cru CLK_GMAC0_125M_SRC>, <&cru CLK_GMAC0_RMII_CRU>, 1134 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 1135 <&cru CLK_GMAC0_PTP_REF>; 1136 clock-names = "stmmaceth", "clk_mac_ref", 1137 "pclk_mac", "aclk_mac", 1138 "ptp_ref"; 1139 interrupts = <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1140 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1141 interrupt-names = "macirq", "eth_wake_irq"; 1142 power-domains = <&power RK3576_PD_SDGMAC>; 1143 resets = <&cru SRST_A_GMAC0>; 1144 reset-names = "stmmaceth"; 1145 rockchip,grf = <&sdgmac_grf>; 1146 rockchip,php-grf = <&ioc_grf>; 1147 snps,axi-config = <&gmac0_stmmac_axi_setup>; 1148 snps,mixed-burst; 1149 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 1150 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 1151 snps,tso; 1152 status = "disabled"; 1153 1154 mdio0: mdio { 1155 compatible = "snps,dwmac-mdio"; 1156 #address-cells = <0x1>; 1157 #size-cells = <0x0>; 1158 }; 1159 1160 gmac0_stmmac_axi_setup: stmmac-axi-config { 1161 snps,blen = <0 0 0 0 16 8 4>; 1162 snps,rd_osr_lmt = <8>; 1163 snps,wr_osr_lmt = <4>; 1164 }; 1165 1166 gmac0_mtl_rx_setup: rx-queues-config { 1167 snps,rx-queues-to-use = <1>; 1168 queue0 {}; 1169 }; 1170 1171 gmac0_mtl_tx_setup: tx-queues-config { 1172 snps,tx-queues-to-use = <1>; 1173 queue0 {}; 1174 }; 1175 }; 1176 1177 gmac1: ethernet@2a230000 { 1178 compatible = "rockchip,rk3576-gmac", "snps,dwmac-4.20a"; 1179 reg = <0x0 0x2a230000 0x0 0x10000>; 1180 clocks = <&cru CLK_GMAC1_125M_SRC>, <&cru CLK_GMAC1_RMII_CRU>, 1181 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 1182 <&cru CLK_GMAC1_PTP_REF>; 1183 clock-names = "stmmaceth", "clk_mac_ref", 1184 "pclk_mac", "aclk_mac", 1185 "ptp_ref"; 1186 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1188 interrupt-names = "macirq", "eth_wake_irq"; 1189 power-domains = <&power RK3576_PD_SDGMAC>; 1190 resets = <&cru SRST_A_GMAC1>; 1191 reset-names = "stmmaceth"; 1192 rockchip,grf = <&sdgmac_grf>; 1193 rockchip,php-grf = <&ioc_grf>; 1194 snps,axi-config = <&gmac1_stmmac_axi_setup>; 1195 snps,mixed-burst; 1196 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 1197 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 1198 snps,tso; 1199 status = "disabled"; 1200 1201 mdio1: mdio { 1202 compatible = "snps,dwmac-mdio"; 1203 #address-cells = <0x1>; 1204 #size-cells = <0x0>; 1205 }; 1206 1207 gmac1_stmmac_axi_setup: stmmac-axi-config { 1208 snps,blen = <0 0 0 0 16 8 4>; 1209 snps,rd_osr_lmt = <8>; 1210 snps,wr_osr_lmt = <4>; 1211 }; 1212 1213 gmac1_mtl_rx_setup: rx-queues-config { 1214 snps,rx-queues-to-use = <1>; 1215 queue0 {}; 1216 }; 1217 1218 gmac1_mtl_tx_setup: tx-queues-config { 1219 snps,tx-queues-to-use = <1>; 1220 queue0 {}; 1221 }; 1222 }; 1223 1224 sdmmc: mmc@2a310000 { 1225 compatible = "rockchip,rk3576-dw-mshc"; 1226 reg = <0x0 0x2a310000 0x0 0x4000>; 1227 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>; 1228 clock-names = "biu", "ciu"; 1229 fifo-depth = <0x100>; 1230 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 1231 max-frequency = <200000000>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4 &sdmmc0_pwren>; 1234 power-domains = <&power RK3576_PD_SDGMAC>; 1235 resets = <&cru SRST_H_SDMMC0>; 1236 reset-names = "reset"; 1237 status = "disabled"; 1238 }; 1239 1240 sdhci: mmc@2a330000 { 1241 compatible = "rockchip,rk3576-dwcmshc", "rockchip,rk3588-dwcmshc"; 1242 reg = <0x0 0x2a330000 0x0 0x10000>; 1243 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 1244 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 1245 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 1246 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 1247 <&cru TCLK_EMMC>; 1248 clock-names = "core", "bus", "axi", "block", "timer"; 1249 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1250 max-frequency = <200000000>; 1251 pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>, 1252 <&emmc_cmd>, <&emmc_strb>; 1253 pinctrl-names = "default"; 1254 power-domains = <&power RK3576_PD_NVM>; 1255 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 1256 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 1257 <&cru SRST_T_EMMC>; 1258 reset-names = "core", "bus", "axi", "block", "timer"; 1259 supports-cqe; 1260 status = "disabled"; 1261 }; 1262 1263 gic: interrupt-controller@2a701000 { 1264 compatible = "arm,gic-400"; 1265 reg = <0x0 0x2a701000 0 0x10000>, 1266 <0x0 0x2a702000 0 0x10000>, 1267 <0x0 0x2a704000 0 0x10000>, 1268 <0x0 0x2a706000 0 0x10000>; 1269 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1270 interrupt-controller; 1271 #interrupt-cells = <3>; 1272 #address-cells = <2>; 1273 #size-cells = <2>; 1274 }; 1275 1276 dmac0: dma-controller@2ab90000 { 1277 compatible = "arm,pl330", "arm,primecell"; 1278 reg = <0x0 0x2ab90000 0x0 0x4000>; 1279 arm,pl330-periph-burst; 1280 clocks = <&cru ACLK_DMAC0>; 1281 clock-names = "apb_pclk"; 1282 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1283 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1284 #dma-cells = <1>; 1285 }; 1286 1287 dmac1: dma-controller@2abb0000 { 1288 compatible = "arm,pl330", "arm,primecell"; 1289 reg = <0x0 0x2abb0000 0x0 0x4000>; 1290 arm,pl330-periph-burst; 1291 clocks = <&cru ACLK_DMAC1>; 1292 clock-names = "apb_pclk"; 1293 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1295 #dma-cells = <1>; 1296 }; 1297 1298 dmac2: dma-controller@2abd0000 { 1299 compatible = "arm,pl330", "arm,primecell"; 1300 reg = <0x0 0x2abd0000 0x0 0x4000>; 1301 arm,pl330-periph-burst; 1302 clocks = <&cru ACLK_DMAC2>; 1303 clock-names = "apb_pclk"; 1304 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1305 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1306 #dma-cells = <1>; 1307 }; 1308 1309 i2c1: i2c@2ac40000 { 1310 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1311 reg = <0x0 0x2ac40000 0x0 0x1000>; 1312 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1313 clock-names = "i2c", "pclk"; 1314 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1315 pinctrl-names = "default"; 1316 pinctrl-0 = <&i2c1m0_xfer>; 1317 #address-cells = <1>; 1318 #size-cells = <0>; 1319 status = "disabled"; 1320 }; 1321 1322 i2c2: i2c@2ac50000 { 1323 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1324 reg = <0x0 0x2ac50000 0x0 0x1000>; 1325 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1326 clock-names = "i2c", "pclk"; 1327 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1328 pinctrl-names = "default"; 1329 pinctrl-0 = <&i2c2m0_xfer>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 i2c3: i2c@2ac60000 { 1336 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1337 reg = <0x0 0x2ac60000 0x0 0x1000>; 1338 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1339 clock-names = "i2c", "pclk"; 1340 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1341 pinctrl-names = "default"; 1342 pinctrl-0 = <&i2c3m0_xfer>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 i2c4: i2c@2ac70000 { 1349 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1350 reg = <0x0 0x2ac70000 0x0 0x1000>; 1351 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1352 clock-names = "i2c", "pclk"; 1353 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 1354 pinctrl-names = "default"; 1355 pinctrl-0 = <&i2c4m0_xfer>; 1356 #address-cells = <1>; 1357 #size-cells = <0>; 1358 status = "disabled"; 1359 }; 1360 1361 i2c5: i2c@2ac80000 { 1362 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1363 reg = <0x0 0x2ac80000 0x0 0x1000>; 1364 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1365 clock-names = "i2c", "pclk"; 1366 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 1367 pinctrl-names = "default"; 1368 pinctrl-0 = <&i2c5m0_xfer>; 1369 #address-cells = <1>; 1370 #size-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 1375 i2c6: i2c@2ac90000 { 1376 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1377 reg = <0x0 0x2ac90000 0x0 0x1000>; 1378 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1379 clock-names = "i2c", "pclk"; 1380 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&i2c6m0_xfer>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 status = "disabled"; 1386 }; 1387 1388 i2c7: i2c@2aca0000 { 1389 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1390 reg = <0x0 0x2aca0000 0x0 0x1000>; 1391 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1392 clock-names = "i2c", "pclk"; 1393 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1394 pinctrl-names = "default"; 1395 pinctrl-0 = <&i2c7m0_xfer>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 status = "disabled"; 1399 }; 1400 1401 i2c8: i2c@2acb0000 { 1402 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1403 reg = <0x0 0x2acb0000 0x0 0x1000>; 1404 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 1405 clock-names = "i2c", "pclk"; 1406 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1407 pinctrl-names = "default"; 1408 pinctrl-0 = <&i2c8m0_xfer>; 1409 #address-cells = <1>; 1410 #size-cells = <0>; 1411 status = "disabled"; 1412 }; 1413 1414 timer0: timer@2acc0000 { 1415 compatible = "rockchip,rk3576-timer", "rockchip,rk3288-timer"; 1416 reg = <0x0 0x2acc0000 0x0 0x20>; 1417 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_TIMER0>; 1418 clock-names = "pclk", "timer"; 1419 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1420 }; 1421 1422 wdt: watchdog@2ace0000 { 1423 compatible = "rockchip,rk3576-wdt", "snps,dw-wdt"; 1424 reg = <0x0 0x2ace0000 0x0 0x100>; 1425 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 1426 clock-names = "tclk", "pclk"; 1427 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1428 status = "disabled"; 1429 }; 1430 1431 spi0: spi@2acf0000 { 1432 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1433 reg = <0x0 0x2acf0000 0x0 0x1000>; 1434 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 1435 clock-names = "spiclk", "apb_pclk"; 1436 dmas = <&dmac0 14>, <&dmac0 15>; 1437 dma-names = "tx", "rx"; 1438 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 1439 num-cs = <2>; 1440 pinctrl-names = "default"; 1441 pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 status = "disabled"; 1445 }; 1446 1447 spi1: spi@2ad00000 { 1448 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1449 reg = <0x0 0x2ad00000 0x0 0x1000>; 1450 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 1451 clock-names = "spiclk", "apb_pclk"; 1452 dmas = <&dmac0 16>, <&dmac0 17>; 1453 dma-names = "tx", "rx"; 1454 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1455 num-cs = <2>; 1456 pinctrl-names = "default"; 1457 pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 1463 spi2: spi@2ad10000 { 1464 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1465 reg = <0x0 0x2ad10000 0x0 0x1000>; 1466 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 1467 clock-names = "spiclk", "apb_pclk"; 1468 dmas = <&dmac1 15>, <&dmac1 16>; 1469 dma-names = "tx", "rx"; 1470 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1471 num-cs = <2>; 1472 pinctrl-names = "default"; 1473 pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 status = "disabled"; 1477 }; 1478 1479 spi3: spi@2ad20000 { 1480 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1481 reg = <0x0 0x2ad20000 0x0 0x1000>; 1482 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 1483 clock-names = "spiclk", "apb_pclk"; 1484 dmas = <&dmac1 17>, <&dmac1 18>; 1485 dma-names = "tx", "rx"; 1486 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1487 num-cs = <2>; 1488 pinctrl-names = "default"; 1489 pinctrl-0 = <&spi3m0_csn0 &spi3m0_csn1 &spi3m0_pins>; 1490 #address-cells = <1>; 1491 #size-cells = <0>; 1492 status = "disabled"; 1493 }; 1494 1495 spi4: spi@2ad30000 { 1496 compatible = "rockchip,rk3576-spi", "rockchip,rk3066-spi"; 1497 reg = <0x0 0x2ad30000 0x0 0x1000>; 1498 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 1499 clock-names = "spiclk", "apb_pclk"; 1500 dmas = <&dmac2 12>, <&dmac2 13>; 1501 dma-names = "tx", "rx"; 1502 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 1503 num-cs = <2>; 1504 pinctrl-names = "default"; 1505 pinctrl-0 = <&spi4m0_csn0 &spi4m0_csn1 &spi4m0_pins>; 1506 #address-cells = <1>; 1507 #size-cells = <0>; 1508 status = "disabled"; 1509 }; 1510 1511 uart0: serial@2ad40000 { 1512 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1513 reg = <0x0 0x2ad40000 0x0 0x100>; 1514 reg-shift = <2>; 1515 reg-io-width = <4>; 1516 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1517 clock-names = "baudclk", "apb_pclk"; 1518 dmas = <&dmac0 6>, <&dmac0 7>; 1519 dma-names = "tx", "rx"; 1520 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1521 pinctrl-0 = <&uart0m0_xfer>; 1522 pinctrl-names = "default"; 1523 status = "disabled"; 1524 }; 1525 1526 uart2: serial@2ad50000 { 1527 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1528 reg = <0x0 0x2ad50000 0x0 0x100>; 1529 reg-shift = <2>; 1530 reg-io-width = <4>; 1531 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1532 clock-names = "baudclk", "apb_pclk"; 1533 dmas = <&dmac0 10>, <&dmac0 11>; 1534 dma-names = "tx", "rx"; 1535 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1536 pinctrl-names = "default"; 1537 pinctrl-0 = <&uart2m0_xfer>; 1538 status = "disabled"; 1539 }; 1540 1541 uart3: serial@2ad60000 { 1542 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1543 reg = <0x0 0x2ad60000 0x0 0x100>; 1544 reg-shift = <2>; 1545 reg-io-width = <4>; 1546 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1547 clock-names = "baudclk", "apb_pclk"; 1548 dmas = <&dmac0 12>, <&dmac0 13>; 1549 dma-names = "tx", "rx"; 1550 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1551 pinctrl-0 = <&uart3m0_xfer>; 1552 pinctrl-names = "default"; 1553 status = "disabled"; 1554 }; 1555 1556 uart4: serial@2ad70000 { 1557 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1558 reg = <0x0 0x2ad70000 0x0 0x100>; 1559 reg-shift = <2>; 1560 reg-io-width = <4>; 1561 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1562 clock-names = "baudclk", "apb_pclk"; 1563 dmas = <&dmac1 9>, <&dmac1 10>; 1564 dma-names = "tx", "rx"; 1565 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1566 pinctrl-0 = <&uart4m0_xfer>; 1567 pinctrl-names = "default"; 1568 status = "disabled"; 1569 }; 1570 1571 uart5: serial@2ad80000 { 1572 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1573 reg = <0x0 0x2ad80000 0x0 0x100>; 1574 reg-shift = <2>; 1575 reg-io-width = <4>; 1576 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1577 clock-names = "baudclk", "apb_pclk"; 1578 dmas = <&dmac1 11>, <&dmac1 12>; 1579 dma-names = "tx", "rx"; 1580 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1581 pinctrl-0 = <&uart5m0_xfer>; 1582 pinctrl-names = "default"; 1583 status = "disabled"; 1584 }; 1585 1586 uart6: serial@2ad90000 { 1587 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1588 reg = <0x0 0x2ad90000 0x0 0x100>; 1589 reg-shift = <2>; 1590 reg-io-width = <4>; 1591 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1592 clock-names = "baudclk", "apb_pclk"; 1593 dmas = <&dmac1 13>, <&dmac1 14>; 1594 dma-names = "tx", "rx"; 1595 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1596 pinctrl-0 = <&uart6m0_xfer>; 1597 pinctrl-names = "default"; 1598 status = "disabled"; 1599 }; 1600 1601 uart7: serial@2ada0000 { 1602 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1603 reg = <0x0 0x2ada0000 0x0 0x100>; 1604 reg-shift = <2>; 1605 reg-io-width = <4>; 1606 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1607 clock-names = "baudclk", "apb_pclk"; 1608 dmas = <&dmac2 6>, <&dmac2 7>; 1609 dma-names = "tx", "rx"; 1610 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1611 pinctrl-0 = <&uart7m0_xfer>; 1612 pinctrl-names = "default"; 1613 status = "disabled"; 1614 }; 1615 1616 uart8: serial@2adb0000 { 1617 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1618 reg = <0x0 0x2adb0000 0x0 0x100>; 1619 reg-shift = <2>; 1620 reg-io-width = <4>; 1621 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 1622 clock-names = "baudclk", "apb_pclk"; 1623 dmas = <&dmac2 8>, <&dmac2 9>; 1624 dma-names = "tx", "rx"; 1625 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1626 pinctrl-0 = <&uart8m0_xfer>; 1627 pinctrl-names = "default"; 1628 status = "disabled"; 1629 }; 1630 1631 uart9: serial@2adc0000 { 1632 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1633 reg = <0x0 0x2adc0000 0x0 0x100>; 1634 reg-shift = <2>; 1635 reg-io-width = <4>; 1636 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 1637 clock-names = "baudclk", "apb_pclk"; 1638 dmas = <&dmac2 10>, <&dmac2 11>; 1639 dma-names = "tx", "rx"; 1640 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 1641 pinctrl-0 = <&uart9m0_xfer>; 1642 pinctrl-names = "default"; 1643 status = "disabled"; 1644 }; 1645 1646 saradc: adc@2ae00000 { 1647 compatible = "rockchip,rk3576-saradc", "rockchip,rk3588-saradc"; 1648 reg = <0x0 0x2ae00000 0x0 0x10000>; 1649 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1650 clock-names = "saradc", "apb_pclk"; 1651 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 1652 resets = <&cru SRST_P_SARADC>; 1653 reset-names = "saradc-apb"; 1654 #io-channel-cells = <1>; 1655 status = "disabled"; 1656 }; 1657 1658 i2c9: i2c@2ae80000 { 1659 compatible = "rockchip,rk3576-i2c", "rockchip,rk3399-i2c"; 1660 reg = <0x0 0x2ae80000 0x0 0x1000>; 1661 clocks = <&cru CLK_I2C9>, <&cru PCLK_I2C9>; 1662 clock-names = "i2c", "pclk"; 1663 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1664 pinctrl-names = "default"; 1665 pinctrl-0 = <&i2c9m0_xfer>; 1666 resets = <&cru SRST_I2C9>, <&cru SRST_P_I2C9>; 1667 reset-names = "i2c", "apb"; 1668 #address-cells = <1>; 1669 #size-cells = <0>; 1670 status = "disabled"; 1671 }; 1672 1673 uart10: serial@2afc0000 { 1674 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1675 reg = <0x0 0x2afc0000 0x0 0x100>; 1676 reg-shift = <2>; 1677 reg-io-width = <4>; 1678 clocks = <&cru SCLK_UART10>, <&cru PCLK_UART10>; 1679 clock-names = "baudclk", "apb_pclk"; 1680 dmas = <&dmac2 21>, <&dmac2 22>; 1681 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1682 pinctrl-names = "default"; 1683 pinctrl-0 = <&uart10m0_xfer>; 1684 status = "disabled"; 1685 }; 1686 1687 uart11: serial@2afd0000 { 1688 compatible = "rockchip,rk3576-uart", "snps,dw-apb-uart"; 1689 reg = <0x0 0x2afd0000 0x0 0x100>; 1690 reg-shift = <2>; 1691 reg-io-width = <4>; 1692 clocks = <&cru SCLK_UART11>, <&cru PCLK_UART11>; 1693 clock-names = "baudclk", "apb_pclk"; 1694 dmas = <&dmac2 23>, <&dmac2 24>; 1695 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1696 pinctrl-names = "default"; 1697 pinctrl-0 = <&uart11m0_xfer>; 1698 status = "disabled"; 1699 }; 1700 1701 combphy0_ps: phy@2b050000 { 1702 compatible = "rockchip,rk3576-naneng-combphy"; 1703 reg = <0x0 0x2b050000 0x0 0x100>; 1704 #phy-cells = <1>; 1705 clocks = <&cru CLK_REF_PCIE0_PHY>, 1706 <&cru PCLK_PCIE2_COMBOPHY0>, 1707 <&cru PCLK_PCIE0>; 1708 clock-names = "ref", "apb", "pipe"; 1709 assigned-clocks = <&cru CLK_REF_PCIE0_PHY>; 1710 assigned-clock-rates = <100000000>; 1711 resets = <&cru SRST_PCIE0_PIPE_PHY>, 1712 <&cru SRST_P_PCIE2_COMBOPHY0>; 1713 reset-names = "phy", "apb"; 1714 rockchip,pipe-grf = <&php_grf>; 1715 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 1716 status = "disabled"; 1717 }; 1718 1719 combphy1_psu: phy@2b060000 { 1720 compatible = "rockchip,rk3576-naneng-combphy"; 1721 reg = <0x0 0x2b060000 0x0 0x100>; 1722 #phy-cells = <1>; 1723 clocks = <&cru CLK_REF_PCIE1_PHY>, 1724 <&cru PCLK_PCIE2_COMBOPHY1>, 1725 <&cru PCLK_PCIE1>; 1726 clock-names = "ref", "apb", "pipe"; 1727 assigned-clocks = <&cru CLK_REF_PCIE1_PHY>; 1728 assigned-clock-rates = <100000000>; 1729 resets = <&cru SRST_PCIE1_PIPE_PHY>, 1730 <&cru SRST_P_PCIE2_COMBOPHY1>; 1731 reset-names = "phy", "apb"; 1732 rockchip,pipe-grf = <&php_grf>; 1733 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 1734 status = "disabled"; 1735 }; 1736 1737 usbdp_phy: phy@2b010000 { 1738 compatible = "rockchip,rk3576-usbdp-phy"; 1739 reg = <0x0 0x2b010000 0x0 0x10000>; 1740 #phy-cells = <1>; 1741 clocks = <&cru CLK_PHY_REF_SRC >, 1742 <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>, 1743 <&cru PCLK_USBDPPHY>, 1744 <&u2phy0>; 1745 clock-names = "refclk", "immortal", "pclk", "utmi"; 1746 resets = <&cru SRST_USBDP_COMBO_PHY_INIT>, 1747 <&cru SRST_USBDP_COMBO_PHY_CMN>, 1748 <&cru SRST_USBDP_COMBO_PHY_LANE>, 1749 <&cru SRST_USBDP_COMBO_PHY_PCS>, 1750 <&cru SRST_P_USBDPPHY>; 1751 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 1752 rockchip,u2phy-grf = <&usb2phy_grf>; 1753 rockchip,usb-grf = <&usb_grf>; 1754 rockchip,usbdpphy-grf = <&usbdpphy_grf>; 1755 rockchip,vo-grf = <&vo1_grf>; 1756 status = "disabled"; 1757 }; 1758 1759 sram: sram@3ff88000 { 1760 compatible = "mmio-sram"; 1761 reg = <0x0 0x3ff88000 0x0 0x78000>; 1762 ranges = <0x0 0x0 0x3ff88000 0x78000>; 1763 #address-cells = <1>; 1764 #size-cells = <1>; 1765 1766 /* start address and size should be 4k align */ 1767 rkvdec_sram: rkvdec-sram@0 { 1768 reg = <0x0 0x78000>; 1769 }; 1770 }; 1771 1772 scmi_shmem: scmi-shmem@4010f000 { 1773 compatible = "arm,scmi-shmem"; 1774 reg = <0x0 0x4010f000 0x0 0x100>; 1775 }; 1776 1777 pinctrl: pinctrl { 1778 compatible = "rockchip,rk3576-pinctrl"; 1779 rockchip,grf = <&ioc_grf>; 1780 #address-cells = <2>; 1781 #size-cells = <2>; 1782 ranges; 1783 1784 gpio0: gpio@27320000 { 1785 compatible = "rockchip,gpio-bank"; 1786 reg = <0x0 0x27320000 0x0 0x200>; 1787 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 1788 gpio-controller; 1789 gpio-ranges = <&pinctrl 0 0 32>; 1790 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 1791 interrupt-controller; 1792 #gpio-cells = <2>; 1793 #interrupt-cells = <2>; 1794 }; 1795 1796 gpio1: gpio@2ae10000 { 1797 compatible = "rockchip,gpio-bank"; 1798 reg = <0x0 0x2ae10000 0x0 0x200>; 1799 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1800 gpio-controller; 1801 gpio-ranges = <&pinctrl 0 32 32>; 1802 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 1803 interrupt-controller; 1804 #gpio-cells = <2>; 1805 #interrupt-cells = <2>; 1806 }; 1807 1808 gpio2: gpio@2ae20000 { 1809 compatible = "rockchip,gpio-bank"; 1810 reg = <0x0 0x2ae20000 0x0 0x200>; 1811 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1812 gpio-controller; 1813 gpio-ranges = <&pinctrl 0 64 32>; 1814 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 1815 interrupt-controller; 1816 #gpio-cells = <2>; 1817 #interrupt-cells = <2>; 1818 }; 1819 1820 gpio3: gpio@2ae30000 { 1821 compatible = "rockchip,gpio-bank"; 1822 reg = <0x0 0x2ae30000 0x0 0x200>; 1823 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 1824 gpio-controller; 1825 gpio-ranges = <&pinctrl 0 96 32>; 1826 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1827 interrupt-controller; 1828 #gpio-cells = <2>; 1829 #interrupt-cells = <2>; 1830 }; 1831 1832 gpio4: gpio@2ae40000 { 1833 compatible = "rockchip,gpio-bank"; 1834 reg = <0x0 0x2ae40000 0x0 0x200>; 1835 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 1836 gpio-controller; 1837 gpio-ranges = <&pinctrl 0 128 32>; 1838 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1839 interrupt-controller; 1840 #gpio-cells = <2>; 1841 #interrupt-cells = <2>; 1842 }; 1843 }; 1844 }; 1845}; 1846 1847#include "rk3576-pinctrl.dtsi" 1848