1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2/*
3 * Device tree for the WolfVision PF5 mainboard.
4 *
5 * Copyright (C) 2024 WolfVision GmbH.
6 */
7
8/dts-v1/;
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/regulator/ti,tps62864.h>
12#include <dt-bindings/soc/rockchip,vop2.h>
13#include "rk3568.dtsi"
14
15/ {
16	model = "WolfVision PF5";
17	compatible = "wolfvision,rk3568-pf5", "rockchip,rk3568";
18
19	aliases {
20		ethernet0 = &gmac0;
21		mmc0 = &sdhci;
22		rtc0 = &pcf85623;
23		rtc1 = &rk809;
24	};
25
26	chosen: chosen {
27		stdout-path = "serial2:115200n8";
28	};
29
30	hdmi_tx: hdmi-tx-connector {
31		compatible = "hdmi-connector";
32		hdmi-pwr-supply = <&hdmi_tx_5v>;
33		type = "a";
34
35		port {
36			hdmi_tx_in: endpoint {
37				remote-endpoint = <&hdmi_tx_out>;
38			};
39		};
40	};
41
42	hdmi_tx_5v: regulator-hdmi-tx-5v {
43		compatible = "regulator-fixed";
44		enable-active-high;
45		gpio = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>;
46		pinctrl-names = "default";
47		pinctrl-0 = <&hdmi_tx_5v_en>;
48		regulator-name = "hdmi_tx_5v";
49		regulator-min-microvolt = <5000000>;
50		regulator-max-microvolt = <5000000>;
51		vin-supply = <&vcc5v_in>;
52	};
53
54	pdm_codec: pdm-codec {
55		compatible = "dmic-codec";
56		num-channels = <2>;
57		#sound-dai-cells = <0>;
58	};
59
60	pdm_sound: pdm-sound {
61		compatible = "simple-audio-card";
62		simple-audio-card,name = "microphone";
63
64		simple-audio-card,cpu {
65			sound-dai = <&pdm>;
66		};
67
68		simple-audio-card,codec {
69			sound-dai = <&pdm_codec>;
70		};
71	};
72
73	vcc12v_cam: regulator-vcc12v-cam {
74		compatible = "regulator-fixed";
75		enable-active-high;
76		gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_HIGH>;
77		pinctrl-names = "default";
78		pinctrl-0 = <&vcc12v_cam_en>;
79		regulator-name = "12v_cam";
80		regulator-min-microvolt = <12000000>;
81		regulator-max-microvolt = <12000000>;
82		vin-supply = <&vcc12v_in>;
83	};
84
85	vcc12v_in: regulator-vcc12v-in {
86		compatible = "regulator-fixed";
87		regulator-name = "12v_in";
88		regulator-always-on;
89		regulator-boot-on;
90		regulator-min-microvolt = <12000000>;
91		regulator-max-microvolt = <12000000>;
92	};
93
94	vcc3v8_cam: regulator-vcc3v8-cam {
95		compatible = "regulator-fixed";
96		enable-active-high;
97		gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
98		pinctrl-names = "default";
99		pinctrl-0 = <&vcc3v8_cam_en>;
100		regulator-name = "3v8_cam";
101		regulator-min-microvolt = <3800000>;
102		regulator-max-microvolt = <3800000>;
103		vin-supply = <&vcc5v_in>;
104	};
105
106	vcc3v3_sys: regulator-vcc3v3-sys {
107		compatible = "regulator-fixed";
108		regulator-name = "3v3_sys";
109		regulator-always-on;
110		regulator-boot-on;
111		regulator-min-microvolt = <3300000>;
112		regulator-max-microvolt = <3300000>;
113		vin-supply = <&vcc5v_in>;
114	};
115
116	vcc5v_in: regulator-vcc5v-in {
117		compatible = "regulator-fixed";
118		regulator-name = "5v_in";
119		regulator-always-on;
120		regulator-boot-on;
121		regulator-min-microvolt = <5000000>;
122		regulator-max-microvolt = <5000000>;
123		vin-supply = <&vcc12v_in>;
124	};
125};
126
127&combphy0 {
128	status = "okay";
129};
130
131&cpu0 {
132	cpu-supply = <&vcc0v9_cpu>;
133};
134
135&cpu1 {
136	cpu-supply = <&vcc0v9_cpu>;
137};
138
139&cpu2 {
140	cpu-supply = <&vcc0v9_cpu>;
141};
142
143&cpu3 {
144	cpu-supply = <&vcc0v9_cpu>;
145};
146
147&gpu {
148	mali-supply = <&vcc0v9_gpu>;
149	status = "okay";
150};
151
152&hdmi {
153	avdd-0v9-supply = <&vcc0v9a_image>;
154	avdd-1v8-supply = <&vcc1v8a_image>;
155	status = "okay";
156};
157
158&hdmi_in {
159	hdmi_in_vp0: endpoint {
160		remote-endpoint = <&vp0_out_hdmi>;
161	};
162};
163
164&hdmi_out {
165	hdmi_tx_out: endpoint {
166		remote-endpoint = <&hdmi_tx_in>;
167	};
168};
169
170&hdmi_sound {
171	status = "okay";
172};
173
174&i2c0 {
175	status = "okay";
176
177	rk809: pmic@20 {
178		compatible = "rockchip,rk809";
179		reg = <0x20>;
180		interrupt-parent = <&gpio0>;
181		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
182		#clock-cells = <0>;
183		pinctrl-names = "default";
184		pinctrl-0 = <&pmic_int_l>;
185		system-power-controller;
186		vcc1-supply = <&vcc5v_in>;
187		vcc2-supply = <&vcc5v_in>;
188		vcc3-supply = <&vcc5v_in>;
189		vcc4-supply = <&vcc5v_in>;
190		vcc5-supply = <&vcc3v3_sys>;
191		vcc6-supply = <&vcc5v_in>;
192		vcc7-supply = <&vcc3v3_sys>;
193		vcc8-supply = <&vcc3v3_sys>;
194		vcc9-supply = <&vcc3v3_sys>;
195		wakeup-source;
196
197		regulators {
198			vcc0v9_logic: DCDC_REG1 {
199				regulator-name = "0v9_logic";
200				regulator-always-on;
201				regulator-boot-on;
202				regulator-initial-mode = <0x2>;
203				regulator-min-microvolt = <500000>;
204				regulator-max-microvolt = <1350000>;
205				regulator-ramp-delay = <6001>;
206
207				regulator-state-mem {
208					regulator-off-in-suspend;
209				};
210			};
211
212			vcc0v9_gpu: DCDC_REG2 {
213				regulator-name = "0v9_gpu";
214				regulator-always-on;
215				regulator-initial-mode = <0x2>;
216				regulator-min-microvolt = <500000>;
217				regulator-max-microvolt = <1350000>;
218				regulator-ramp-delay = <6001>;
219
220				regulator-state-mem {
221					regulator-off-in-suspend;
222				};
223			};
224
225			vcc1v1_ddr4: DCDC_REG3 {
226				regulator-name = "1v1_ddr4";
227				regulator-always-on;
228				regulator-boot-on;
229				regulator-initial-mode = <0x2>;
230
231				regulator-state-mem {
232					regulator-on-in-suspend;
233				};
234			};
235
236			vcc0v9_npu: DCDC_REG4 {
237				regulator-name = "0v9_npu";
238				regulator-always-on;
239				regulator-initial-mode = <0x2>;
240				regulator-min-microvolt = <900000>;
241				regulator-max-microvolt = <1350000>;
242				regulator-ramp-delay = <6001>;
243
244				regulator-state-mem {
245					regulator-off-in-suspend;
246				};
247			};
248
249			vcc1v8: DCDC_REG5 {
250				regulator-name = "1v8";
251				regulator-always-on;
252				regulator-boot-on;
253				regulator-min-microvolt = <1800000>;
254				regulator-max-microvolt = <1800000>;
255
256				regulator-state-mem {
257					regulator-off-in-suspend;
258				};
259			};
260
261			vcc0v9a_image: LDO_REG1 {
262				regulator-name = "0v9a_image";
263				regulator-min-microvolt = <900000>;
264				regulator-max-microvolt = <900000>;
265
266				regulator-state-mem {
267					regulator-off-in-suspend;
268				};
269			};
270
271			vcc0v9a: LDO_REG2 {
272				regulator-name = "0v9a";
273				regulator-always-on;
274				regulator-boot-on;
275				regulator-min-microvolt = <900000>;
276				regulator-max-microvolt = <900000>;
277
278				regulator-state-mem {
279					regulator-off-in-suspend;
280				};
281			};
282
283			vcc0v9a_pmu: LDO_REG3 {
284				regulator-name = "0v9a_pmu";
285				regulator-always-on;
286				regulator-boot-on;
287				regulator-min-microvolt = <900000>;
288				regulator-max-microvolt = <900000>;
289
290				regulator-state-mem {
291					regulator-on-in-suspend;
292					regulator-suspend-microvolt = <900000>;
293				};
294			};
295
296			vcc3v3_acodec: LDO_REG4 {
297				regulator-name = "3v3_acodec";
298				regulator-always-on;
299				regulator-min-microvolt = <3300000>;
300				regulator-max-microvolt = <3300000>;
301
302				regulator-state-mem {
303					regulator-off-in-suspend;
304				};
305			};
306
307			vcc3v3_sd: LDO_REG5 {
308				regulator-name = "3v3_sd";
309				regulator-always-on;
310				regulator-boot-on;
311				regulator-min-microvolt = <3300000>;
312				regulator-max-microvolt = <3300000>;
313
314				regulator-state-mem {
315					regulator-off-in-suspend;
316				};
317			};
318
319			vcc3v3_pmu: LDO_REG6 {
320				regulator-name = "3v3_pmu";
321				regulator-always-on;
322				regulator-boot-on;
323				regulator-min-microvolt = <3300000>;
324				regulator-max-microvolt = <3300000>;
325
326				regulator-state-mem {
327					regulator-on-in-suspend;
328					regulator-suspend-microvolt = <3300000>;
329				};
330			};
331
332			vcc1v8a: LDO_REG7 {
333				regulator-name = "1v8a";
334				regulator-always-on;
335				regulator-boot-on;
336				regulator-min-microvolt = <1800000>;
337				regulator-max-microvolt = <1800000>;
338
339				regulator-state-mem {
340					regulator-off-in-suspend;
341				};
342			};
343
344			vcc1v8a_pmu: LDO_REG8 {
345				regulator-name = "1v8a_pmu";
346				regulator-always-on;
347				regulator-boot-on;
348				regulator-min-microvolt = <1800000>;
349				regulator-max-microvolt = <1800000>;
350
351				regulator-state-mem {
352					regulator-on-in-suspend;
353					regulator-suspend-microvolt = <1800000>;
354				};
355			};
356
357			vcc1v8a_image: LDO_REG9 {
358				regulator-name = "1v8a_image";
359				regulator-min-microvolt = <1800000>;
360				regulator-max-microvolt = <1800000>;
361
362				regulator-state-mem {
363					regulator-off-in-suspend;
364				};
365			};
366
367			vcc3v3_sw: SWITCH_REG1 {
368				regulator-name = "3v3_sw";
369				regulator-always-on;
370				regulator-boot-on;
371				regulator-min-microvolt = <3300000>;
372				regulator-max-microvolt = <3300000>;
373
374				regulator-state-mem {
375					regulator-off-in-suspend;
376				};
377			};
378		};
379	};
380
381	regulator@42 {
382		compatible = "ti,tps62869";
383		reg = <0x42>;
384
385		regulators {
386			vcc0v9_cpu: SW {
387				regulator-name = "0v9_cpu";
388				regulator-always-on;
389				regulator-boot-on;
390				regulator-initial-mode = <TPS62864_MODE_FPWM>;
391				regulator-min-microvolt = <900000>;
392				regulator-max-microvolt = <1150000>;
393				vin-supply = <&vcc5v_in>;
394
395				regulator-state-mem {
396					regulator-off-in-suspend;
397				};
398			};
399		};
400	};
401
402	pcf85623: rtc@51 {
403		compatible = "nxp,pcf85263";
404		reg = <0x51>;
405		pinctrl-names = "default";
406		pinctrl-0 = <&clk32k_in>;
407		quartz-load-femtofarads = <12500>;
408	};
409};
410
411&i2c3 {
412	pinctrl-names = "default";
413	pinctrl-0 = <&i2c3m0_xfer>;
414};
415
416&i2c4 {
417	pinctrl-names = "default";
418	pinctrl-0 = <&i2c4m1_xfer>;
419};
420
421&i2s0_8ch {
422	status = "okay";
423};
424
425&pdm {
426	pinctrl-0 = <&pdmm0_clk
427		     &pdmm0_sdi0>;
428	status = "okay";
429};
430
431&pinctrl {
432	cam {
433		vcc12v_cam_en: vcc12v-cam-en-pinctrl {
434			rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>;
435		};
436
437		vcc3v8_cam_en: vcc3v8-cam-en-pinctrl {
438			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
439		};
440	};
441
442	hdmitx {
443		hdmi_tx_5v_en: hdmi-tx-5v-en-pinctrl {
444			rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
445		};
446	};
447
448	pmic {
449		pmic_int_l: pmic-int-l-pinctrl {
450			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
451		};
452	};
453};
454
455&pmu_io_domains {
456	pmuio1-supply = <&vcc3v3_pmu>;
457	pmuio2-supply = <&vcc3v3_pmu>;
458	vccio1-supply = <&vcc3v3_acodec>;
459	vccio2-supply = <&vcc1v8>;
460	vccio3-supply = <&vcc3v3_sd>;
461	vccio4-supply = <&vcc1v8>;
462	vccio5-supply = <&vcc1v8>;
463	vccio6-supply = <&vcc3v3_sw>;
464	vccio7-supply = <&vcc3v3_sw>;
465	status = "okay";
466};
467
468&saradc {
469	vref-supply = <&vcc1v8a>;
470	status = "okay";
471};
472
473&sdhci {
474	bus-width = <8>;
475	max-frequency = <200000000>;
476	non-removable;
477	pinctrl-names = "default";
478	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
479	vmmc-supply = <&vcc3v3_sw>;
480	vqmmc-supply = <&vcc1v8>;
481	status = "okay";
482};
483
484&tsadc {
485	rockchip,hw-tshut-mode = <1>;
486	rockchip,hw-tshut-polarity = <0>;
487	status = "okay";
488};
489
490&uart2 {
491	status = "okay";
492};
493
494&usb_host0_xhci {
495	dr_mode = "peripheral";
496	/* The following quirks are required since the bInterval is 1 and we
497	 * handle steady ISOC streaming. See Usecase 3 in commit 729dcffd1ed3
498	 * ("usb: dwc3: gadget: Add support for disabling U1 and U2 entries").
499	 */
500	snps,dis-u1-entry-quirk;
501	snps,dis-u2-entry-quirk;
502	/*
503	 * Without this quirk the available fifosize seems to be miscalculated
504	 * in cases where many endpoints are used. In one particular situation
505	 * 8 IN EPs and 3 OUT EPs where selected and lead to stalled transfers
506	 * without the resize quirk.
507	 */
508	tx-fifo-resize;
509
510	status = "okay";
511};
512
513&usb2phy0 {
514	status = "okay";
515};
516
517&usb2phy0_otg {
518	status = "okay";
519};
520
521&vop {
522	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP2>;
523	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
524	status = "okay";
525};
526
527&vop_mmu {
528	status = "okay";
529};
530
531&vp0 {
532	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
533		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
534		remote-endpoint = <&hdmi_in_vp0>;
535	};
536};
537