1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the R9A08G045S33 SMARC Carrier-II's SoM board.
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11
12/*
13 * On-board switches' states:
14 * @SW_OFF: switch's state is OFF
15 * @SW_ON:  switch's state is ON
16 */
17#define SW_OFF		0
18#define SW_ON		1
19
20/*
21 * SW_CONFIG[x] switches' states:
22 * @SW_CONFIG2:
23 *	SW_OFF - SD0 is connected to eMMC
24 *	SW_ON  - SD0 is connected to uSD0 card
25 * @SW_CONFIG3:
26 *	SW_OFF - SD2 is connected to SoC
27 *	SW_ON  - SCIF1, SSI0, IRQ0, IRQ1 connected to SoC
28 */
29#define SW_CONFIG2	SW_OFF
30#define SW_CONFIG3	SW_ON
31
32/ {
33	compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045";
34
35	aliases {
36		i2c1 = &i2c1;
37		mmc0 = &sdhi0;
38#if SW_CONFIG3 == SW_OFF
39		mmc2 = &sdhi2;
40#else
41		ethernet0 = &eth0;
42		ethernet1 = &eth1;
43#endif
44	};
45
46	memory@48000000 {
47		device_type = "memory";
48		/* First 128MB is reserved for secure area. */
49		reg = <0x0 0x48000000 0x0 0x38000000>;
50	};
51
52	vcc_sdhi0: regulator0 {
53		compatible = "regulator-fixed";
54		regulator-name = "SDHI0 Vcc";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		gpios = <&pinctrl RZG2L_GPIO(2, 1) GPIO_ACTIVE_HIGH>;
58		enable-active-high;
59	};
60
61	vccq_sdhi0: regulator1 {
62		compatible = "regulator-gpio";
63		regulator-name = "SDHI0 VccQ";
64		regulator-min-microvolt = <1800000>;
65		regulator-max-microvolt = <3300000>;
66		gpios = <&pinctrl RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
67		gpios-states = <1>;
68		states = <3300000 1>, <1800000 0>;
69	};
70
71	reg_1p8v: regulator2 {
72		compatible = "regulator-fixed";
73		regulator-name = "fixed-1.8V";
74		regulator-min-microvolt = <1800000>;
75		regulator-max-microvolt = <1800000>;
76		regulator-boot-on;
77		regulator-always-on;
78	};
79
80	reg_3p3v: regulator3 {
81		compatible = "regulator-fixed";
82		regulator-name = "fixed-3.3V";
83		regulator-min-microvolt = <3300000>;
84		regulator-max-microvolt = <3300000>;
85		regulator-boot-on;
86		regulator-always-on;
87	};
88
89	vcc_sdhi2: regulator4 {
90		compatible = "regulator-fixed";
91		regulator-name = "SDHI2 Vcc";
92		regulator-min-microvolt = <3300000>;
93		regulator-max-microvolt = <3300000>;
94		gpios = <&pinctrl RZG2L_GPIO(8, 1) GPIO_ACTIVE_HIGH>;
95		enable-active-high;
96	};
97
98	x3_clk: x3-clock {
99		compatible = "fixed-clock";
100		#clock-cells = <0>;
101		clock-frequency = <24000000>;
102	};
103};
104
105&adc {
106	status = "okay";
107};
108
109#if SW_CONFIG3 == SW_ON
110&eth0 {
111	pinctrl-0 = <&eth0_pins>;
112	pinctrl-names = "default";
113	phy-handle = <&phy0>;
114	phy-mode = "rgmii-id";
115	status = "okay";
116
117	phy0: ethernet-phy@7 {
118		reg = <7>;
119		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 0) IRQ_TYPE_EDGE_FALLING>;
120		rxc-skew-psec = <0>;
121		txc-skew-psec = <0>;
122		rxdv-skew-psec = <0>;
123		txen-skew-psec = <0>;
124		rxd0-skew-psec = <0>;
125		rxd1-skew-psec = <0>;
126		rxd2-skew-psec = <0>;
127		rxd3-skew-psec = <0>;
128		txd0-skew-psec = <0>;
129		txd1-skew-psec = <0>;
130		txd2-skew-psec = <0>;
131		txd3-skew-psec = <0>;
132	};
133};
134
135&eth1 {
136	pinctrl-0 = <&eth1_pins>;
137	pinctrl-names = "default";
138	phy-handle = <&phy1>;
139	phy-mode = "rgmii-id";
140	status = "okay";
141
142	phy1: ethernet-phy@7 {
143		reg = <7>;
144		interrupts-extended = <&pinctrl RZG2L_GPIO(12, 1) IRQ_TYPE_EDGE_FALLING>;
145		rxc-skew-psec = <0>;
146		txc-skew-psec = <0>;
147		rxdv-skew-psec = <0>;
148		txen-skew-psec = <0>;
149		rxd0-skew-psec = <0>;
150		rxd1-skew-psec = <0>;
151		rxd2-skew-psec = <0>;
152		rxd3-skew-psec = <0>;
153		txd0-skew-psec = <0>;
154		txd1-skew-psec = <0>;
155		txd2-skew-psec = <0>;
156		txd3-skew-psec = <0>;
157	};
158};
159#endif
160
161&extal_clk {
162	clock-frequency = <24000000>;
163};
164
165&i2c1 {
166	status = "okay";
167
168	versa3: clock-generator@68 {
169		compatible = "renesas,5l35023";
170		reg = <0x68>;
171		clocks = <&x3_clk>;
172		#clock-cells = <1>;
173		assigned-clocks = <&versa3 0>,
174				  <&versa3 1>,
175				  <&versa3 2>,
176				  <&versa3 3>,
177				  <&versa3 4>,
178				  <&versa3 5>;
179		assigned-clock-rates = <24000000>,
180				       <12288000>,
181				       <11289600>,
182				       <25000000>,
183				       <100000000>,
184				       <100000000>;
185		renesas,settings = [
186		  80 00 11 19 4c 42 dc 2f 06 7d 20 1a 5f 1e f2 27
187		  00 40 00 00 00 00 00 00 06 0c 19 02 3f f0 90 86
188		  a0 80 30 30 9c
189		];
190	};
191};
192
193#if SW_CONFIG2 == SW_ON
194/* SD0 slot */
195&sdhi0 {
196	pinctrl-0 = <&sdhi0_pins>;
197	pinctrl-1 = <&sdhi0_uhs_pins>;
198	pinctrl-names = "default", "state_uhs";
199	vmmc-supply = <&vcc_sdhi0>;
200	vqmmc-supply = <&vccq_sdhi0>;
201	bus-width = <4>;
202	sd-uhs-sdr50;
203	sd-uhs-sdr104;
204	max-frequency = <125000000>;
205	status = "okay";
206};
207#else
208/* eMMC */
209&sdhi0 {
210	pinctrl-0 = <&sdhi0_emmc_pins>;
211	pinctrl-1 = <&sdhi0_emmc_pins>;
212	pinctrl-names = "default", "state_uhs";
213	vmmc-supply = <&vcc_sdhi0>;
214	vqmmc-supply = <&reg_1p8v>;
215	bus-width = <8>;
216	mmc-hs200-1_8v;
217	non-removable;
218	fixed-emmc-driver-type = <1>;
219	max-frequency = <125000000>;
220	status = "okay";
221};
222#endif
223
224#if SW_CONFIG3 == SW_OFF
225&sdhi2 {
226	pinctrl-0 = <&sdhi2_pins>;
227	pinctrl-names = "default";
228	vmmc-supply = <&vcc_sdhi2>;
229	bus-width = <4>;
230	max-frequency = <50000000>;
231	status = "okay";
232};
233#endif
234
235&pinctrl {
236#if SW_CONFIG3 == SW_ON
237	eth0-phy-irq-hog {
238		gpio-hog;
239		gpios = <RZG2L_GPIO(12, 0) GPIO_ACTIVE_LOW>;
240		input;
241		line-name = "eth0-phy-irq";
242	};
243#endif
244
245	eth0_pins: eth0 {
246		txc {
247			pinmux = <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* ET0_TXC */
248			power-source = <1800>;
249			output-enable;
250			input-enable;
251			drive-strength-microamp = <5200>;
252		};
253
254		tx_ctl {
255			pinmux = <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* ET0_TX_CTL */
256			power-source = <1800>;
257			output-enable;
258			drive-strength-microamp = <5200>;
259		};
260
261		mux {
262			pinmux = <RZG2L_PORT_PINMUX(1, 2, 1)>,	/* ET0_TXD0 */
263				 <RZG2L_PORT_PINMUX(1, 3, 1)>,	/* ET0_TXD1 */
264				 <RZG2L_PORT_PINMUX(1, 4, 1)>,	/* ET0_TXD2 */
265				 <RZG2L_PORT_PINMUX(2, 0, 1)>,	/* ET0_TXD3 */
266				 <RZG2L_PORT_PINMUX(3, 0, 1)>,	/* ET0_RXC */
267				 <RZG2L_PORT_PINMUX(3, 1, 1)>,	/* ET0_RX_CTL */
268				 <RZG2L_PORT_PINMUX(3, 2, 1)>,	/* ET0_RXD0 */
269				 <RZG2L_PORT_PINMUX(3, 3, 1)>,	/* ET0_RXD1 */
270				 <RZG2L_PORT_PINMUX(4, 0, 1)>,	/* ET0_RXD2 */
271				 <RZG2L_PORT_PINMUX(4, 1, 1)>,	/* ET0_RXD3 */
272				 <RZG2L_PORT_PINMUX(4, 3, 1)>,	/* ET0_MDC */
273				 <RZG2L_PORT_PINMUX(4, 4, 1)>,	/* ET0_MDIO */
274				 <RZG2L_PORT_PINMUX(4, 5, 1)>;	/* ET0_LINKSTA */
275			power-source = <1800>;
276		};
277	};
278
279#if SW_CONFIG3 == SW_ON
280	eth1-phy-irq-hog {
281		gpio-hog;
282		gpios = <RZG2L_GPIO(12, 1) GPIO_ACTIVE_LOW>;
283		input;
284		line-name = "eth1-phy-irq";
285	};
286#endif
287
288	eth1_pins: eth1 {
289		txc {
290			pinmux = <RZG2L_PORT_PINMUX(7, 0, 1)>;	/* ET1_TXC */
291			power-source = <1800>;
292			output-enable;
293			input-enable;
294			drive-strength-microamp = <5200>;
295		};
296
297		tx_ctl {
298			pinmux = <RZG2L_PORT_PINMUX(7, 1, 1)>;	/* ET1_TX_CTL */
299			power-source = <1800>;
300			output-enable;
301			drive-strength-microamp = <5200>;
302		};
303
304		mux {
305			pinmux = <RZG2L_PORT_PINMUX(7, 2, 1)>,	/* ET1_TXD0 */
306				 <RZG2L_PORT_PINMUX(7, 3, 1)>,	/* ET1_TXD1 */
307				 <RZG2L_PORT_PINMUX(7, 4, 1)>,	/* ET1_TXD2 */
308				 <RZG2L_PORT_PINMUX(8, 0, 1)>,	/* ET1_TXD3 */
309				 <RZG2L_PORT_PINMUX(8, 4, 1)>,	/* ET1_RXC */
310				 <RZG2L_PORT_PINMUX(9, 0, 1)>,	/* ET1_RX_CTL */
311				 <RZG2L_PORT_PINMUX(9, 1, 1)>,	/* ET1_RXD0 */
312				 <RZG2L_PORT_PINMUX(9, 2, 1)>,	/* ET1_RXD1 */
313				 <RZG2L_PORT_PINMUX(9, 3, 1)>,	/* ET1_RXD2 */
314				 <RZG2L_PORT_PINMUX(10, 0, 1)>,	/* ET1_RXD3 */
315				 <RZG2L_PORT_PINMUX(10, 2, 1)>,	/* ET1_MDC */
316				 <RZG2L_PORT_PINMUX(10, 3, 1)>,	/* ET1_MDIO */
317				 <RZG2L_PORT_PINMUX(10, 4, 1)>;	/* ET1_LINKSTA */
318			power-source = <1800>;
319		};
320	};
321
322	sdhi0_pins: sd0 {
323		data {
324			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
325			power-source = <3300>;
326		};
327
328		ctrl {
329			pins = "SD0_CLK", "SD0_CMD";
330			power-source = <3300>;
331		};
332
333		cd {
334			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
335		};
336	};
337
338	sdhi0_uhs_pins: sd0-uhs {
339		data {
340			pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
341			power-source = <1800>;
342		};
343
344		ctrl {
345			pins = "SD0_CLK", "SD0_CMD";
346			power-source = <1800>;
347		};
348
349		cd {
350			pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
351		};
352	};
353
354	sdhi0_emmc_pins: sd0-emmc {
355		pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
356		       "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7",
357		       "SD0_CLK", "SD0_CMD", "SD0_RST#";
358		power-source = <1800>;
359	};
360
361	sdhi2_pins: sd2 {
362		data {
363			pins = "P11_2", "P11_3", "P12_0", "P12_1";
364			input-enable;
365		};
366
367		ctrl {
368			pins = "P11_1";
369			input-enable;
370		};
371
372		mux {
373			pinmux = <RZG2L_PORT_PINMUX(11, 0, 8)>, /* SD2_CLK */
374				 <RZG2L_PORT_PINMUX(11, 1, 8)>, /* SD2_CMD */
375				 <RZG2L_PORT_PINMUX(11, 2, 8)>, /* SD2_DATA0 */
376				 <RZG2L_PORT_PINMUX(11, 3, 8)>, /* SD2_DATA1 */
377				 <RZG2L_PORT_PINMUX(12, 0, 8)>, /* SD2_DATA2 */
378				 <RZG2L_PORT_PINMUX(12, 1, 8)>, /* SD2_DATA3 */
379				 <RZG2L_PORT_PINMUX(14, 1, 7)>; /* SD2_CD# */
380		};
381	};
382};
383
384&rtc {
385	status = "okay";
386};
387
388&vbattb {
389	assigned-clocks = <&vbattb VBATTB_MUX>;
390	assigned-clock-parents = <&vbattb VBATTB_XC>;
391	quartz-load-femtofarads = <12500>;
392	status = "okay";
393};
394
395&vbattb_xtal {
396	clock-frequency = <32768>;
397};
398
399&wdt0 {
400	timeout-sec = <60>;
401	status = "okay";
402};
403