1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3E SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g047"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 audio_extal_clk: audio-clk { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; 19 /* This value must be overridden by the board */ 20 clock-frequency = <0>; 21 }; 22 23 /* 24 * The default cluster table is based on the assumption that the PLLCA55 clock 25 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 26 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 27 * clocked to 1.8GHz as well). The table below should be overridden in the board 28 * DTS based on the PLLCA55 clock frequency. 29 */ 30 cluster0_opp: opp-table-0 { 31 compatible = "operating-points-v2"; 32 33 opp-1700000000 { 34 opp-hz = /bits/ 64 <1700000000>; 35 opp-microvolt = <900000>; 36 clock-latency-ns = <300000>; 37 }; 38 opp-850000000 { 39 opp-hz = /bits/ 64 <850000000>; 40 opp-microvolt = <800000>; 41 clock-latency-ns = <300000>; 42 }; 43 opp-425000000 { 44 opp-hz = /bits/ 64 <425000000>; 45 opp-microvolt = <800000>; 46 clock-latency-ns = <300000>; 47 }; 48 opp-212500000 { 49 opp-hz = /bits/ 64 <212500000>; 50 opp-microvolt = <800000>; 51 clock-latency-ns = <300000>; 52 opp-suspend; 53 }; 54 }; 55 56 cpus { 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 cpu0: cpu@0 { 61 compatible = "arm,cortex-a55"; 62 reg = <0>; 63 device_type = "cpu"; 64 next-level-cache = <&L3_CA55>; 65 enable-method = "psci"; 66 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; 67 operating-points-v2 = <&cluster0_opp>; 68 }; 69 70 cpu1: cpu@100 { 71 compatible = "arm,cortex-a55"; 72 reg = <0x100>; 73 device_type = "cpu"; 74 next-level-cache = <&L3_CA55>; 75 enable-method = "psci"; 76 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 cpu2: cpu@200 { 81 compatible = "arm,cortex-a55"; 82 reg = <0x200>; 83 device_type = "cpu"; 84 next-level-cache = <&L3_CA55>; 85 enable-method = "psci"; 86 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; 87 operating-points-v2 = <&cluster0_opp>; 88 }; 89 90 cpu3: cpu@300 { 91 compatible = "arm,cortex-a55"; 92 reg = <0x300>; 93 device_type = "cpu"; 94 next-level-cache = <&L3_CA55>; 95 enable-method = "psci"; 96 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; 97 operating-points-v2 = <&cluster0_opp>; 98 }; 99 100 L3_CA55: cache-controller-0 { 101 compatible = "cache"; 102 cache-unified; 103 cache-size = <0x100000>; 104 cache-level = <3>; 105 }; 106 }; 107 108 psci { 109 compatible = "arm,psci-1.0", "arm,psci-0.2"; 110 method = "smc"; 111 }; 112 113 qextal_clk: qextal-clk { 114 compatible = "fixed-clock"; 115 #clock-cells = <0>; 116 /* This value must be overridden by the board */ 117 clock-frequency = <0>; 118 }; 119 120 rtxin_clk: rtxin-clk { 121 compatible = "fixed-clock"; 122 #clock-cells = <0>; 123 /* This value must be overridden by the board */ 124 clock-frequency = <0>; 125 }; 126 127 soc: soc { 128 compatible = "simple-bus"; 129 interrupt-parent = <&gic>; 130 #address-cells = <2>; 131 #size-cells = <2>; 132 ranges; 133 134 pinctrl: pinctrl@10410000 { 135 compatible = "renesas,r9a09g047-pinctrl"; 136 reg = <0 0x10410000 0 0x10000>; 137 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; 138 gpio-controller; 139 #gpio-cells = <2>; 140 gpio-ranges = <&pinctrl 0 0 232>; 141 #interrupt-cells = <2>; 142 interrupt-controller; 143 power-domains = <&cpg>; 144 resets = <&cpg 0xa5>, <&cpg 0xa6>; 145 }; 146 147 cpg: clock-controller@10420000 { 148 compatible = "renesas,r9a09g047-cpg"; 149 reg = <0 0x10420000 0 0x10000>; 150 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 151 clock-names = "audio_extal", "rtxin", "qextal"; 152 #clock-cells = <2>; 153 #reset-cells = <1>; 154 #power-domain-cells = <0>; 155 }; 156 157 scif0: serial@11c01400 { 158 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 159 reg = <0 0x11c01400 0 0x400>; 160 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 168 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 169 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 170 "tei", "tei-dri", "rxi-edge", "txi-edge"; 171 clocks = <&cpg CPG_MOD 0x8f>; 172 clock-names = "fck"; 173 power-domains = <&cpg>; 174 resets = <&cpg 0x95>; 175 status = "disabled"; 176 }; 177 178 i2c0: i2c@14400400 { 179 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 180 reg = <0 0x14400400 0 0x400>; 181 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 183 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 184 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 189 interrupt-names = "tei", "ri", "ti", "spi", "sti", 190 "naki", "ali", "tmoi"; 191 clocks = <&cpg CPG_MOD 0x94>; 192 resets = <&cpg 0x98>; 193 power-domains = <&cpg>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 status = "disabled"; 197 }; 198 199 i2c1: i2c@14400800 { 200 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 201 reg = <0 0x14400800 0 0x400>; 202 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 204 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 205 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 210 interrupt-names = "tei", "ri", "ti", "spi", "sti", 211 "naki", "ali", "tmoi"; 212 clocks = <&cpg CPG_MOD 0x95>; 213 resets = <&cpg 0x99>; 214 power-domains = <&cpg>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 status = "disabled"; 218 }; 219 220 i2c2: i2c@14400c00 { 221 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 222 reg = <0 0x14400c00 0 0x400>; 223 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 225 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 226 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-names = "tei", "ri", "ti", "spi", "sti", 232 "naki", "ali", "tmoi"; 233 clocks = <&cpg CPG_MOD 0x96>; 234 resets = <&cpg 0x9a>; 235 power-domains = <&cpg>; 236 #address-cells = <1>; 237 #size-cells = <0>; 238 status = "disabled"; 239 }; 240 241 i2c3: i2c@14401000 { 242 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 243 reg = <0 0x14401000 0 0x400>; 244 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 246 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 247 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-names = "tei", "ri", "ti", "spi", "sti", 253 "naki", "ali", "tmoi"; 254 clocks = <&cpg CPG_MOD 0x97>; 255 resets = <&cpg 0x9b>; 256 power-domains = <&cpg>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 status = "disabled"; 260 }; 261 262 i2c4: i2c@14401400 { 263 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 264 reg = <0 0x14401400 0 0x400>; 265 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 267 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 268 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 272 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 273 interrupt-names = "tei", "ri", "ti", "spi", "sti", 274 "naki", "ali", "tmoi"; 275 clocks = <&cpg CPG_MOD 0x98>; 276 resets = <&cpg 0x9c>; 277 power-domains = <&cpg>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 status = "disabled"; 281 }; 282 283 i2c5: i2c@14401800 { 284 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 285 reg = <0 0x14401800 0 0x400>; 286 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 288 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 289 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 294 interrupt-names = "tei", "ri", "ti", "spi", "sti", 295 "naki", "ali", "tmoi"; 296 clocks = <&cpg CPG_MOD 0x99>; 297 resets = <&cpg 0x9d>; 298 power-domains = <&cpg>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 status = "disabled"; 302 }; 303 304 i2c6: i2c@14401c00 { 305 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 306 reg = <0 0x14401c00 0 0x400>; 307 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 310 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 315 interrupt-names = "tei", "ri", "ti", "spi", "sti", 316 "naki", "ali", "tmoi"; 317 clocks = <&cpg CPG_MOD 0x9a>; 318 resets = <&cpg 0x9e>; 319 power-domains = <&cpg>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 status = "disabled"; 323 }; 324 325 i2c7: i2c@14402000 { 326 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 327 reg = <0 0x14402000 0 0x400>; 328 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 336 interrupt-names = "tei", "ri", "ti", "spi", "sti", 337 "naki", "ali", "tmoi"; 338 clocks = <&cpg CPG_MOD 0x9b>; 339 resets = <&cpg 0x9f>; 340 power-domains = <&cpg>; 341 #address-cells = <1>; 342 #size-cells = <0>; 343 status = "disabled"; 344 }; 345 346 i2c8: i2c@11c01000 { 347 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 348 reg = <0 0x11c01000 0 0x400>; 349 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "tei", "ri", "ti", "spi", "sti", 358 "naki", "ali", "tmoi"; 359 clocks = <&cpg CPG_MOD 0x93>; 360 resets = <&cpg 0xa0>; 361 power-domains = <&cpg>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 status = "disabled"; 365 }; 366 367 gic: interrupt-controller@14900000 { 368 compatible = "arm,gic-v3"; 369 reg = <0x0 0x14900000 0 0x20000>, 370 <0x0 0x14940000 0 0x80000>; 371 #interrupt-cells = <3>; 372 #address-cells = <0>; 373 interrupt-controller; 374 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 375 }; 376 }; 377 378 timer { 379 compatible = "arm,armv8-timer"; 380 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 381 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 382 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 383 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 384 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 385 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 386 }; 387}; 388