1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3S SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/r9a08g045-cpg.h> 10#include <dt-bindings/clock/renesas,r9a08g045-vbattb.h> 11 12/ { 13 compatible = "renesas,r9a08g045"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 audio_clk1: audio1-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by boards that provide it. */ 21 clock-frequency = <0>; 22 }; 23 24 audio_clk2: audio2-clk { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 /* This value must be overridden by boards that provide it. */ 28 clock-frequency = <0>; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 compatible = "arm,cortex-a55"; 37 reg = <0>; 38 device_type = "cpu"; 39 #cooling-cells = <2>; 40 next-level-cache = <&L3_CA55>; 41 enable-method = "psci"; 42 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 43 }; 44 45 L3_CA55: cache-controller-0 { 46 compatible = "cache"; 47 cache-level = <3>; 48 cache-unified; 49 cache-size = <0x40000>; 50 }; 51 }; 52 53 extal_clk: extal-clk { 54 compatible = "fixed-clock"; 55 #clock-cells = <0>; 56 /* This value must be overridden by the board. */ 57 clock-frequency = <0>; 58 }; 59 60 psci { 61 compatible = "arm,psci-1.0", "arm,psci-0.2"; 62 method = "smc"; 63 }; 64 65 soc: soc { 66 compatible = "simple-bus"; 67 interrupt-parent = <&gic>; 68 #address-cells = <2>; 69 #size-cells = <2>; 70 ranges; 71 72 scif0: serial@1004b800 { 73 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 74 reg = <0 0x1004b800 0 0x400>; 75 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 79 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 81 interrupt-names = "eri", "rxi", "txi", 82 "bri", "dri", "tei"; 83 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 84 clock-names = "fck"; 85 power-domains = <&cpg>; 86 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 87 status = "disabled"; 88 }; 89 90 scif1: serial@1004bc00 { 91 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 92 reg = <0 0x1004bc00 0 0x400>; 93 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 94 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 95 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 96 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 97 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 98 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 99 interrupt-names = "eri", "rxi", "txi", 100 "bri", "dri", "tei"; 101 clocks = <&cpg CPG_MOD R9A08G045_SCIF1_CLK_PCK>; 102 clock-names = "fck"; 103 power-domains = <&cpg>; 104 resets = <&cpg R9A08G045_SCIF1_RST_SYSTEM_N>; 105 status = "disabled"; 106 }; 107 108 scif2: serial@1004c000 { 109 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 110 reg = <0 0x1004c000 0 0x400>; 111 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 112 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 113 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 114 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 115 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 116 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 117 interrupt-names = "eri", "rxi", "txi", 118 "bri", "dri", "tei"; 119 clocks = <&cpg CPG_MOD R9A08G045_SCIF2_CLK_PCK>; 120 clock-names = "fck"; 121 power-domains = <&cpg>; 122 resets = <&cpg R9A08G045_SCIF2_RST_SYSTEM_N>; 123 status = "disabled"; 124 }; 125 126 scif3: serial@1004c400 { 127 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 128 reg = <0 0x1004c400 0 0x400>; 129 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 132 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 133 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 134 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 135 interrupt-names = "eri", "rxi", "txi", 136 "bri", "dri", "tei"; 137 clocks = <&cpg CPG_MOD R9A08G045_SCIF3_CLK_PCK>; 138 clock-names = "fck"; 139 power-domains = <&cpg>; 140 resets = <&cpg R9A08G045_SCIF3_RST_SYSTEM_N>; 141 status = "disabled"; 142 }; 143 144 scif4: serial@1004c800 { 145 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 146 reg = <0 0x1004c800 0 0x400>; 147 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 153 interrupt-names = "eri", "rxi", "txi", 154 "bri", "dri", "tei"; 155 clocks = <&cpg CPG_MOD R9A08G045_SCIF4_CLK_PCK>; 156 clock-names = "fck"; 157 power-domains = <&cpg>; 158 resets = <&cpg R9A08G045_SCIF4_RST_SYSTEM_N>; 159 status = "disabled"; 160 }; 161 162 scif5: serial@1004e000 { 163 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 164 reg = <0 0x1004e000 0 0x400>; 165 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 171 interrupt-names = "eri", "rxi", "txi", 172 "bri", "dri", "tei"; 173 clocks = <&cpg CPG_MOD R9A08G045_SCIF5_CLK_PCK>; 174 clock-names = "fck"; 175 power-domains = <&cpg>; 176 resets = <&cpg R9A08G045_SCIF5_RST_SYSTEM_N>; 177 status = "disabled"; 178 }; 179 180 rtc: rtc@1004ec00 { 181 compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; 182 reg = <0 0x1004ec00 0 0x400>; 183 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 186 interrupt-names = "alarm", "period", "carry"; 187 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb VBATTB_VBATTCLK>; 188 clock-names = "bus", "counter"; 189 power-domains = <&cpg>; 190 resets = <&cpg R9A08G045_VBAT_BRESETN>; 191 status = "disabled"; 192 }; 193 194 adc: adc@10058000 { 195 compatible = "renesas,r9a08g045-adc"; 196 reg = <0 0x10058000 0 0x1000>; 197 interrupts = <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>; 198 clocks = <&cpg CPG_MOD R9A08G045_ADC_ADCLK>, 199 <&cpg CPG_MOD R9A08G045_ADC_PCLK>; 200 clock-names = "adclk", "pclk"; 201 resets = <&cpg R9A08G045_ADC_PRESETN>, 202 <&cpg R9A08G045_ADC_ADRST_N>; 203 reset-names = "presetn", "adrst-n"; 204 power-domains = <&cpg>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 #io-channel-cells = <1>; 208 status = "disabled"; 209 210 channel@0 { 211 reg = <0>; 212 }; 213 214 channel@1 { 215 reg = <1>; 216 }; 217 218 channel@2 { 219 reg = <2>; 220 }; 221 222 channel@3 { 223 reg = <3>; 224 }; 225 226 channel@4 { 227 reg = <4>; 228 }; 229 230 channel@5 { 231 reg = <5>; 232 }; 233 234 channel@6 { 235 reg = <6>; 236 }; 237 238 channel@7 { 239 reg = <7>; 240 }; 241 242 channel@8 { 243 reg = <8>; 244 }; 245 }; 246 247 vbattb: clock-controller@1005c000 { 248 compatible = "renesas,r9a08g045-vbattb"; 249 reg = <0 0x1005c000 0 0x1000>; 250 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattb_xtal>; 252 clock-names = "bclk", "rtx"; 253 #clock-cells = <1>; 254 power-domains = <&cpg>; 255 resets = <&cpg R9A08G045_VBAT_BRESETN>; 256 status = "disabled"; 257 }; 258 259 i2c0: i2c@10090000 { 260 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 261 reg = <0 0x10090000 0 0x400>; 262 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 264 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 265 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 270 interrupt-names = "tei", "ri", "ti", "spi", "sti", 271 "naki", "ali", "tmoi"; 272 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; 273 clock-frequency = <100000>; 274 resets = <&cpg R9A08G045_I2C0_MRST>; 275 power-domains = <&cpg>; 276 #address-cells = <1>; 277 #size-cells = <0>; 278 status = "disabled"; 279 }; 280 281 i2c1: i2c@10090400 { 282 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 283 reg = <0 0x10090400 0 0x400>; 284 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>, 286 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>, 287 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; 292 interrupt-names = "tei", "ri", "ti", "spi", "sti", 293 "naki", "ali", "tmoi"; 294 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; 295 clock-frequency = <100000>; 296 resets = <&cpg R9A08G045_I2C1_MRST>; 297 power-domains = <&cpg>; 298 #address-cells = <1>; 299 #size-cells = <0>; 300 status = "disabled"; 301 }; 302 303 i2c2: i2c@10090800 { 304 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 305 reg = <0 0x10090800 0 0x400>; 306 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>, 308 <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "tei", "ri", "ti", "spi", "sti", 315 "naki", "ali", "tmoi"; 316 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; 317 clock-frequency = <100000>; 318 resets = <&cpg R9A08G045_I2C2_MRST>; 319 power-domains = <&cpg>; 320 #address-cells = <1>; 321 #size-cells = <0>; 322 status = "disabled"; 323 }; 324 325 i2c3: i2c@10090c00 { 326 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; 327 reg = <0 0x10090c00 0 0x400>; 328 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>, 330 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>, 331 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 336 interrupt-names = "tei", "ri", "ti", "spi", "sti", 337 "naki", "ali", "tmoi"; 338 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>; 339 clock-frequency = <100000>; 340 resets = <&cpg R9A08G045_I2C3_MRST>; 341 power-domains = <&cpg>; 342 #address-cells = <1>; 343 #size-cells = <0>; 344 status = "disabled"; 345 }; 346 347 ssi0: ssi@100a8000 { 348 compatible = "renesas,r9a08g045-ssi", 349 "renesas,rz-ssi"; 350 reg = <0 0x100a8000 0 0x400>; 351 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 241 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 242 IRQ_TYPE_EDGE_RISING>; 354 interrupt-names = "int_req", "dma_rx", "dma_tx"; 355 clocks = <&cpg CPG_MOD R9A08G045_SSI0_PCLK2>, 356 <&cpg CPG_MOD R9A08G045_SSI0_PCLK_SFR>, 357 <&audio_clk1>, <&audio_clk2>; 358 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 359 resets = <&cpg R9A08G045_SSI0_RST_M2_REG>; 360 dmas = <&dmac 0x2665>, <&dmac 0x2666>; 361 dma-names = "tx", "rx"; 362 power-domains = <&cpg>; 363 #sound-dai-cells = <0>; 364 status = "disabled"; 365 }; 366 367 ssi1: ssi@100a8400 { 368 compatible = "renesas,r9a08g045-ssi", 369 "renesas,rz-ssi"; 370 reg = <0 0x100a8400 0 0x400>; 371 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 244 IRQ_TYPE_EDGE_RISING>, 373 <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 374 interrupt-names = "int_req", "dma_rx", "dma_tx"; 375 clocks = <&cpg CPG_MOD R9A08G045_SSI1_PCLK2>, 376 <&cpg CPG_MOD R9A08G045_SSI1_PCLK_SFR>, 377 <&audio_clk1>, <&audio_clk2>; 378 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 379 resets = <&cpg R9A08G045_SSI1_RST_M2_REG>; 380 dmas = <&dmac 0x2669>, <&dmac 0x266a>; 381 dma-names = "tx", "rx"; 382 power-domains = <&cpg>; 383 #sound-dai-cells = <0>; 384 status = "disabled"; 385 }; 386 387 ssi2: ssi@100a8800 { 388 compatible = "renesas,r9a08g045-ssi", 389 "renesas,rz-ssi"; 390 reg = <0 0x100a8800 0 0x400>; 391 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>, 393 <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>; 394 interrupt-names = "int_req", "dma_rx", "dma_tx"; 395 clocks = <&cpg CPG_MOD R9A08G045_SSI2_PCLK2>, 396 <&cpg CPG_MOD R9A08G045_SSI2_PCLK_SFR>, 397 <&audio_clk1>, <&audio_clk2>; 398 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 399 resets = <&cpg R9A08G045_SSI2_RST_M2_REG>; 400 dmas = <&dmac 0x266d>, <&dmac 0x266e>; 401 dma-names = "tx", "rx"; 402 power-domains = <&cpg>; 403 #sound-dai-cells = <0>; 404 status = "disabled"; 405 }; 406 407 ssi3: ssi@100a8c00 { 408 compatible = "renesas,r9a08g045-ssi", 409 "renesas,rz-ssi"; 410 reg = <0 0x100a8c00 0 0x400>; 411 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 412 <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>; 414 interrupt-names = "int_req", "dma_rx", "dma_tx"; 415 clocks = <&cpg CPG_MOD R9A08G045_SSI3_PCLK2>, 416 <&cpg CPG_MOD R9A08G045_SSI3_PCLK_SFR>, 417 <&audio_clk1>, <&audio_clk2>; 418 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2"; 419 resets = <&cpg R9A08G045_SSI3_RST_M2_REG>; 420 dmas = <&dmac 0x2671>, <&dmac 0x2672>; 421 dma-names = "tx", "rx"; 422 power-domains = <&cpg>; 423 #sound-dai-cells = <0>; 424 status = "disabled"; 425 }; 426 427 cpg: clock-controller@11010000 { 428 compatible = "renesas,r9a08g045-cpg"; 429 reg = <0 0x11010000 0 0x10000>; 430 clocks = <&extal_clk>; 431 clock-names = "extal"; 432 #clock-cells = <2>; 433 #reset-cells = <1>; 434 #power-domain-cells = <0>; 435 }; 436 437 sysc: system-controller@11020000 { 438 compatible = "renesas,r9a08g045-sysc"; 439 reg = <0 0x11020000 0 0x10000>; 440 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 444 interrupt-names = "lpm_int", "ca55stbydone_int", 445 "cm33stbyr_int", "ca55_deny"; 446 status = "disabled"; 447 }; 448 449 pinctrl: pinctrl@11030000 { 450 compatible = "renesas,r9a08g045-pinctrl"; 451 reg = <0 0x11030000 0 0x10000>; 452 gpio-controller; 453 #gpio-cells = <2>; 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 interrupt-parent = <&irqc>; 457 gpio-ranges = <&pinctrl 0 0 152>; 458 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 459 power-domains = <&cpg>; 460 resets = <&cpg R9A08G045_GPIO_RSTN>, 461 <&cpg R9A08G045_GPIO_PORT_RESETN>, 462 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 463 }; 464 465 irqc: interrupt-controller@11050000 { 466 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; 467 #interrupt-cells = <2>; 468 #address-cells = <0>; 469 interrupt-controller; 470 reg = <0 0x11050000 0 0x10000>; 471 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-names = "nmi", 517 "irq0", "irq1", "irq2", "irq3", 518 "irq4", "irq5", "irq6", "irq7", 519 "tint0", "tint1", "tint2", "tint3", 520 "tint4", "tint5", "tint6", "tint7", 521 "tint8", "tint9", "tint10", "tint11", 522 "tint12", "tint13", "tint14", "tint15", 523 "tint16", "tint17", "tint18", "tint19", 524 "tint20", "tint21", "tint22", "tint23", 525 "tint24", "tint25", "tint26", "tint27", 526 "tint28", "tint29", "tint30", "tint31", 527 "bus-err", "ec7tie1-0", "ec7tie2-0", 528 "ec7tiovf-0"; 529 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, 530 <&cpg CPG_MOD R9A08G045_IA55_PCLK>; 531 clock-names = "clk", "pclk"; 532 power-domains = <&cpg>; 533 resets = <&cpg R9A08G045_IA55_RESETN>; 534 }; 535 536 dmac: dma-controller@11820000 { 537 compatible = "renesas,r9a08g045-dmac", 538 "renesas,rz-dmac"; 539 reg = <0 0x11820000 0 0x10000>, 540 <0 0x11830000 0 0x10000>; 541 interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>, 543 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 544 <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>, 545 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>, 546 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>, 547 <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>, 548 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>, 549 <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>, 550 <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 551 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 552 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 553 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 554 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 555 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 556 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 557 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>; 558 interrupt-names = "error", 559 "ch0", "ch1", "ch2", "ch3", 560 "ch4", "ch5", "ch6", "ch7", 561 "ch8", "ch9", "ch10", "ch11", 562 "ch12", "ch13", "ch14", "ch15"; 563 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>, 564 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>; 565 clock-names = "main", "register"; 566 power-domains = <&cpg>; 567 resets = <&cpg R9A08G045_DMAC_ARESETN>, 568 <&cpg R9A08G045_DMAC_RST_ASYNC>; 569 reset-names = "arst", "rst_async"; 570 #dma-cells = <1>; 571 dma-channels = <16>; 572 }; 573 574 sdhi0: mmc@11c00000 { 575 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 576 reg = <0x0 0x11c00000 0 0x10000>; 577 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 578 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 580 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 581 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 582 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 583 clock-names = "core", "clkh", "cd", "aclk"; 584 resets = <&cpg R9A08G045_SDHI0_IXRST>; 585 power-domains = <&cpg>; 586 status = "disabled"; 587 }; 588 589 sdhi1: mmc@11c10000 { 590 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 591 reg = <0x0 0x11c10000 0 0x10000>; 592 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 595 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 596 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 597 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 598 clock-names = "core", "clkh", "cd", "aclk"; 599 resets = <&cpg R9A08G045_SDHI1_IXRST>; 600 power-domains = <&cpg>; 601 status = "disabled"; 602 }; 603 604 sdhi2: mmc@11c20000 { 605 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi"; 606 reg = <0x0 0x11c20000 0 0x10000>; 607 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 610 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 611 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 612 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 613 clock-names = "core", "clkh", "cd", "aclk"; 614 resets = <&cpg R9A08G045_SDHI2_IXRST>; 615 power-domains = <&cpg>; 616 status = "disabled"; 617 }; 618 619 eth0: ethernet@11c30000 { 620 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 621 reg = <0 0x11c30000 0 0x10000>; 622 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 625 interrupt-names = "mux", "fil", "arp_ns"; 626 phy-mode = "rgmii"; 627 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, 628 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, 629 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; 630 clock-names = "axi", "chi", "refclk"; 631 resets = <&cpg R9A08G045_ETH0_RST_HW_N>; 632 power-domains = <&cpg>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 status = "disabled"; 636 }; 637 638 eth1: ethernet@11c40000 { 639 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 640 reg = <0 0x11c40000 0 0x10000>; 641 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "mux", "fil", "arp_ns"; 645 phy-mode = "rgmii"; 646 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, 647 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, 648 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; 649 clock-names = "axi", "chi", "refclk"; 650 resets = <&cpg R9A08G045_ETH1_RST_HW_N>; 651 power-domains = <&cpg>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 status = "disabled"; 655 }; 656 657 gic: interrupt-controller@12400000 { 658 compatible = "arm,gic-v3"; 659 #interrupt-cells = <3>; 660 #address-cells = <0>; 661 interrupt-controller; 662 reg = <0x0 0x12400000 0 0x20000>, 663 <0x0 0x12440000 0 0x40000>; 664 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 665 }; 666 667 wdt0: watchdog@12800800 { 668 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt"; 669 reg = <0 0x12800800 0 0x400>; 670 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>, 671 <&cpg CPG_MOD R9A08G045_WDT0_CLK>; 672 clock-names = "pclk", "oscclk"; 673 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 675 interrupt-names = "wdt", "perrout"; 676 resets = <&cpg R9A08G045_WDT0_PRESETN>; 677 power-domains = <&cpg>; 678 status = "disabled"; 679 }; 680 }; 681 682 timer { 683 compatible = "arm,armv8-timer"; 684 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 685 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 686 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 687 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 688 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 689 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 690 "hyp-virt"; 691 }; 692 693 vbattb_xtal: vbattb-xtal { 694 compatible = "fixed-clock"; 695 #clock-cells = <0>; 696 /* This value must be overridden by the board. */ 697 clock-frequency = <0>; 698 }; 699}; 700