1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for the Falcon Ethernet sub-board
4 *
5 * Copyright (C) 2021 Glider bv
6 */
7
8/ {
9	aliases {
10		ethernet1 = &avb1;
11		ethernet2 = &avb2;
12		ethernet3 = &avb3;
13		ethernet4 = &avb4;
14		ethernet5 = &avb5;
15	};
16};
17
18&avb1 {
19	pinctrl-0 = <&avb1_pins>;
20	pinctrl-names = "default";
21	phy-handle = <&avb1_phy>;
22	status = "okay";
23
24	mdio {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		reset-gpios = <&gpio5 15 GPIO_ACTIVE_LOW>;
29		reset-post-delay-us = <4000>;
30
31		avb1_phy: ethernet-phy@7 {
32			compatible = "ethernet-phy-ieee802.3-c45";
33			reg = <7>;
34			interrupts-extended = <&gpio5 16 IRQ_TYPE_LEVEL_LOW>;
35		};
36	};
37};
38
39&avb2 {
40	pinctrl-0 = <&avb2_pins>;
41	pinctrl-names = "default";
42	phy-handle = <&avb2_phy>;
43	status = "okay";
44
45	mdio {
46		#address-cells = <1>;
47		#size-cells = <0>;
48
49		reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
50		reset-post-delay-us = <4000>;
51
52		avb2_phy: ethernet-phy@7 {
53			compatible = "ethernet-phy-ieee802.3-c45";
54			reg = <7>;
55			interrupts-extended = <&gpio6 16 IRQ_TYPE_LEVEL_LOW>;
56		};
57	};
58};
59
60&avb3 {
61	pinctrl-0 = <&avb3_pins>;
62	pinctrl-names = "default";
63	phy-handle = <&avb3_phy>;
64	status = "okay";
65
66	mdio {
67		#address-cells = <1>;
68		#size-cells = <0>;
69
70		reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>;
71		reset-post-delay-us = <4000>;
72
73		avb3_phy: ethernet-phy@7 {
74			compatible = "ethernet-phy-ieee802.3-c45";
75			reg = <7>;
76			interrupts-extended = <&gpio7 16 IRQ_TYPE_LEVEL_LOW>;
77		};
78	};
79};
80
81&avb4 {
82	pinctrl-0 = <&avb4_pins>;
83	pinctrl-names = "default";
84	phy-handle = <&avb4_phy>;
85	status = "okay";
86
87	mdio {
88		#address-cells = <1>;
89		#size-cells = <0>;
90
91		reset-gpios = <&gpio8 15 GPIO_ACTIVE_LOW>;
92		reset-post-delay-us = <4000>;
93
94		avb4_phy: ethernet-phy@7 {
95			compatible = "ethernet-phy-ieee802.3-c45";
96			reg = <7>;
97			interrupts-extended = <&gpio8 16 IRQ_TYPE_LEVEL_LOW>;
98		};
99	};
100};
101
102&avb5 {
103	pinctrl-0 = <&avb5_pins>;
104	pinctrl-names = "default";
105	phy-handle = <&avb5_phy>;
106	status = "okay";
107
108	mdio {
109		#address-cells = <1>;
110		#size-cells = <0>;
111
112		reset-gpios = <&gpio9 15 GPIO_ACTIVE_LOW>;
113		reset-post-delay-us = <4000>;
114
115		avb5_phy: ethernet-phy@7 {
116			compatible = "ethernet-phy-ieee802.3-c45";
117			reg = <7>;
118			interrupts-extended = <&gpio9 16 IRQ_TYPE_LEVEL_LOW>;
119		};
120	};
121};
122
123&i2c0 {
124	eeprom@53 {
125		compatible = "rohm,br24g01", "atmel,24c01";
126		label = "ethernet-sub-board-id";
127		reg = <0x53>;
128		pagesize = <8>;
129	};
130};
131
132&pfc {
133	avb1_pins: avb1 {
134		mux {
135			groups = "avb1_link", "avb1_mdio", "avb1_rgmii",
136				 "avb1_txcrefclk";
137			function = "avb1";
138		};
139
140		link {
141			groups = "avb1_link";
142			bias-disable;
143		};
144
145		mdio {
146			groups = "avb1_mdio";
147			drive-strength = <24>;
148			bias-disable;
149		};
150
151		rgmii {
152			groups = "avb1_rgmii";
153			drive-strength = <24>;
154			bias-disable;
155		};
156	};
157
158	avb2_pins: avb2 {
159		mux {
160			groups = "avb2_link", "avb2_mdio", "avb2_rgmii",
161				 "avb2_txcrefclk";
162			function = "avb2";
163		};
164
165		link {
166			groups = "avb2_link";
167			bias-disable;
168		};
169
170		mdio {
171			groups = "avb2_mdio";
172			drive-strength = <24>;
173			bias-disable;
174		};
175
176		rgmii {
177			groups = "avb2_rgmii";
178			drive-strength = <24>;
179			bias-disable;
180		};
181	};
182
183	avb3_pins: avb3 {
184		mux {
185			groups = "avb3_link", "avb3_mdio", "avb3_rgmii",
186				 "avb3_txcrefclk";
187			function = "avb3";
188		};
189
190		link {
191			groups = "avb3_link";
192			bias-disable;
193		};
194
195		mdio {
196			groups = "avb3_mdio";
197			drive-strength = <24>;
198			bias-disable;
199		};
200
201		rgmii {
202			groups = "avb3_rgmii";
203			drive-strength = <24>;
204			bias-disable;
205		};
206	};
207
208	avb4_pins: avb4 {
209		mux {
210			groups = "avb4_link", "avb4_mdio", "avb4_rgmii",
211				 "avb4_txcrefclk";
212			function = "avb4";
213		};
214
215		link {
216			groups = "avb4_link";
217			bias-disable;
218		};
219
220		mdio {
221			groups = "avb4_mdio";
222			drive-strength = <24>;
223			bias-disable;
224		};
225
226		rgmii {
227			groups = "avb4_rgmii";
228			drive-strength = <24>;
229			bias-disable;
230		};
231	};
232
233	avb5_pins: avb5 {
234		mux {
235			groups = "avb5_link", "avb5_mdio", "avb5_rgmii",
236				 "avb5_txcrefclk";
237			function = "avb5";
238		};
239
240		link {
241			groups = "avb5_link";
242			bias-disable;
243		};
244
245		mdio {
246			groups = "avb5_mdio";
247			drive-strength = <24>;
248			bias-disable;
249		};
250
251		rgmii {
252			groups = "avb5_rgmii";
253			drive-strength = <24>;
254			bias-disable;
255		};
256	};
257};
258