1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8750-gcc.h> 8#include <dt-bindings/clock/qcom,sm8750-tcsr.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/interconnect/qcom,icc.h> 11#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom,rpmhpd.h> 14#include <dt-bindings/power/qcom-rpmpd.h> 15#include <dt-bindings/soc/qcom,rpmh-rsc.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "qcom,oryon"; 30 reg = <0x0 0x0>; 31 enable-method = "psci"; 32 next-level-cache = <&l2_0>; 33 power-domains = <&cpu_pd0>; 34 power-domain-names = "psci"; 35 36 l2_0: l2-cache { 37 compatible = "cache"; 38 cache-level = <2>; 39 cache-unified; 40 }; 41 }; 42 43 cpu1: cpu@100 { 44 device_type = "cpu"; 45 compatible = "qcom,oryon"; 46 reg = <0x0 0x100>; 47 enable-method = "psci"; 48 next-level-cache = <&l2_0>; 49 power-domains = <&cpu_pd1>; 50 power-domain-names = "psci"; 51 }; 52 53 cpu2: cpu@200 { 54 device_type = "cpu"; 55 compatible = "qcom,oryon"; 56 reg = <0x0 0x200>; 57 enable-method = "psci"; 58 next-level-cache = <&l2_0>; 59 power-domains = <&cpu_pd2>; 60 power-domain-names = "psci"; 61 }; 62 63 cpu3: cpu@300 { 64 device_type = "cpu"; 65 compatible = "qcom,oryon"; 66 reg = <0x0 0x300>; 67 enable-method = "psci"; 68 next-level-cache = <&l2_0>; 69 power-domains = <&cpu_pd3>; 70 power-domain-names = "psci"; 71 }; 72 73 cpu4: cpu@400 { 74 device_type = "cpu"; 75 compatible = "qcom,oryon"; 76 reg = <0x0 0x400>; 77 enable-method = "psci"; 78 next-level-cache = <&l2_0>; 79 power-domains = <&cpu_pd4>; 80 power-domain-names = "psci"; 81 }; 82 83 cpu5: cpu@500 { 84 device_type = "cpu"; 85 compatible = "qcom,oryon"; 86 reg = <0x0 0x500>; 87 enable-method = "psci"; 88 next-level-cache = <&l2_0>; 89 power-domains = <&cpu_pd5>; 90 power-domain-names = "psci"; 91 }; 92 93 cpu6: cpu@10000 { 94 device_type = "cpu"; 95 compatible = "qcom,oryon"; 96 reg = <0x0 0x10000>; 97 enable-method = "psci"; 98 next-level-cache = <&L2_1>; 99 power-domains = <&cpu_pd6>; 100 power-domain-names = "psci"; 101 102 L2_1: l2-cache { 103 compatible = "cache"; 104 cache-level = <2>; 105 cache-unified; 106 }; 107 }; 108 109 cpu7: cpu@10100 { 110 device_type = "cpu"; 111 compatible = "qcom,oryon"; 112 reg = <0x0 0x10100>; 113 enable-method = "psci"; 114 next-level-cache = <&L2_1>; 115 power-domains = <&cpu_pd7>; 116 power-domain-names = "psci"; 117 }; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&cpu0>; 123 }; 124 125 core1 { 126 cpu = <&cpu1>; 127 }; 128 129 core2 { 130 cpu = <&cpu2>; 131 }; 132 133 core3 { 134 cpu = <&cpu3>; 135 }; 136 137 core4 { 138 cpu = <&cpu4>; 139 }; 140 141 core5 { 142 cpu = <&cpu5>; 143 }; 144 }; 145 146 cluster1 { 147 core0 { 148 cpu = <&cpu6>; 149 }; 150 151 core1 { 152 cpu = <&cpu7>; 153 }; 154 }; 155 }; 156 157 idle-states { 158 entry-method = "psci"; 159 160 cluster0_c4: cpu-sleep-0 { 161 compatible = "arm,idle-state"; 162 idle-state-name = "ret"; 163 arm,psci-suspend-param = <0x00000004>; 164 entry-latency-us = <93>; 165 exit-latency-us = <129>; 166 min-residency-us = <560>; 167 }; 168 169 cluster1_c4: cpu-sleep-1 { 170 compatible = "arm,idle-state"; 171 idle-state-name = "ret"; 172 arm,psci-suspend-param = <0x00000004>; 173 entry-latency-us = <172>; 174 exit-latency-us = <130>; 175 min-residency-us = <686>; 176 }; 177 178 }; 179 180 domain-idle-states { 181 cluster_cl5: cluster-sleep-0 { 182 compatible = "domain-idle-state"; 183 arm,psci-suspend-param = <0x01000054>; 184 entry-latency-us = <2150>; 185 exit-latency-us = <1983>; 186 min-residency-us = <9144>; 187 }; 188 189 domain_ss3: domain-sleep-0 { 190 compatible = "domain-idle-state"; 191 arm,psci-suspend-param = <0x0200c354>; 192 entry-latency-us = <2800>; 193 exit-latency-us = <4400>; 194 min-residency-us = <10150>; 195 }; 196 }; 197 }; 198 199 firmware { 200 scm: scm { 201 compatible = "qcom,scm-sm8750", "qcom,scm"; 202 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 203 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 204 }; 205 }; 206 207 clk_virt: interconnect-0 { 208 compatible = "qcom,sm8750-clk-virt"; 209 #interconnect-cells = <2>; 210 qcom,bcm-voters = <&apps_bcm_voter>; 211 }; 212 213 mc_virt: interconnect-1 { 214 compatible = "qcom,sm8750-mc-virt"; 215 #interconnect-cells = <2>; 216 qcom,bcm-voters = <&apps_bcm_voter>; 217 }; 218 219 memory@a0000000 { 220 device_type = "memory"; 221 /* We expect the bootloader to fill in the size */ 222 reg = <0x0 0xa0000000 0x0 0x0>; 223 }; 224 225 pmu { 226 compatible = "arm,armv8-pmuv3"; 227 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 228 }; 229 230 psci { 231 compatible = "arm,psci-1.0"; 232 method = "smc"; 233 234 cpu_pd0: power-domain-cpu0 { 235 #power-domain-cells = <0>; 236 power-domains = <&cluster_pd>; 237 domain-idle-states = <&cluster0_c4>; 238 }; 239 240 cpu_pd1: power-domain-cpu1 { 241 #power-domain-cells = <0>; 242 power-domains = <&cluster_pd>; 243 domain-idle-states = <&cluster0_c4>; 244 }; 245 246 cpu_pd2: power-domain-cpu2 { 247 #power-domain-cells = <0>; 248 power-domains = <&cluster_pd>; 249 domain-idle-states = <&cluster0_c4>; 250 }; 251 252 cpu_pd3: power-domain-cpu3 { 253 #power-domain-cells = <0>; 254 power-domains = <&cluster_pd>; 255 domain-idle-states = <&cluster0_c4>; 256 }; 257 258 cpu_pd4: power-domain-cpu4 { 259 #power-domain-cells = <0>; 260 power-domains = <&cluster_pd>; 261 domain-idle-states = <&cluster0_c4>; 262 }; 263 264 cpu_pd5: power-domain-cpu5 { 265 #power-domain-cells = <0>; 266 power-domains = <&cluster_pd>; 267 domain-idle-states = <&cluster0_c4>; 268 }; 269 270 cpu_pd6: power-domain-cpu6 { 271 #power-domain-cells = <0>; 272 power-domains = <&cluster_pd>; 273 domain-idle-states = <&cluster1_c4>; 274 }; 275 276 cpu_pd7: power-domain-cpu7 { 277 #power-domain-cells = <0>; 278 power-domains = <&cluster_pd>; 279 domain-idle-states = <&cluster1_c4>; 280 }; 281 282 cluster_pd: power-domain-cluster { 283 #power-domain-cells = <0>; 284 domain-idle-states = <&cluster_cl5>; 285 power-domains = <&system_pd>; 286 }; 287 288 system_pd: power-domain-system { 289 #power-domain-cells = <0>; 290 domain-idle-states = <&domain_ss3>; 291 }; 292 }; 293 294 reserved-memory { 295 #address-cells = <2>; 296 #size-cells = <2>; 297 ranges; 298 299 gunyah_hyp_mem: gunyah-hyp@80000000 { 300 reg = <0x0 0x80000000 0x0 0xe00000>; 301 no-map; 302 }; 303 304 cpusys_vm_mem: cpusys-vm-mem@80e00000 { 305 reg = <0x0 0x80e00000 0x0 0x40000>; 306 no-map; 307 }; 308 309 cpucp_mem: cpucp@81200000 { 310 reg = <0x0 0x81200000 0x0 0x200000>; 311 no-map; 312 }; 313 314 xbl_dtlog_mem: xbl-dtlog@81a00000 { 315 reg = <0x0 0x81a00000 0x0 0x40000>; 316 no-map; 317 }; 318 319 aop_image_mem: aop-image@81c00000 { 320 reg = <0x0 0x81c00000 0x0 0x60000>; 321 no-map; 322 }; 323 324 aop_cmd_db_mem: aop-cmd-db@81c60000 { 325 compatible = "qcom,cmd-db"; 326 reg = <0x0 0x81c60000 0x0 0x20000>; 327 no-map; 328 }; 329 330 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 331 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 332 reg = <0x0 0x81c80000 0x0 0x74000>; 333 no-map; 334 }; 335 336 /* Secdata region can be reused by apps */ 337 338 smem_mem: smem@81d00000 { 339 compatible = "qcom,smem"; 340 reg = <0x0 0x81d00000 0x0 0x200000>; 341 hwlocks = <&tcsr_mutex 3>; 342 no-map; 343 }; 344 345 pdp_ns_shared_mem: pdp-ns-shared@81f00000 { 346 reg = <0x0 0x81f00000 0x0 0x100000>; 347 no-map; 348 }; 349 350 cpucp_scandump_mem: cpucp-scandump@82000000 { 351 reg = <0x0 0x82000000 0x0 0x380000>; 352 no-map; 353 }; 354 355 adsp_mhi_mem: adsp-mhi@82380000 { 356 reg = <0x0 0x82380000 0x0 0x20000>; 357 no-map; 358 }; 359 360 soccp_sdi_mem: soccp-sdi@823a0000 { 361 reg = <0x0 0x823a0000 0x0 0x40000>; 362 no-map; 363 }; 364 365 pmic_minii_dump_mem: pmic-minii-dump@823e0000 { 366 reg = <0x0 0x823e0000 0x0 0x80000>; 367 no-map; 368 }; 369 370 pvmfw_mem: pvmfw@824a0000 { 371 reg = <0x0 0x824a0000 0x0 0x100000>; 372 no-map; 373 }; 374 375 global_sync_mem: global-sync@82600000 { 376 reg = <0x0 0x82600000 0x0 0x100000>; 377 no-map; 378 }; 379 380 tz_stat_mem: tz-stat@82700000 { 381 reg = <0x0 0x82700000 0x0 0x100000>; 382 no-map; 383 }; 384 385 qdss_mem: qdss@82800000 { 386 reg = <0x0 0x82800000 0x0 0x2000000>; 387 no-map; 388 }; 389 390 dsm_partition_1_mem: dsm-partition-1@84a00000 { 391 reg = <0x0 0x84a00000 0x0 0x4900000>; 392 no-map; 393 }; 394 395 dsm_partition_2_mem: dsm-partition-2@89300000 { 396 reg = <0x0 0x89300000 0x0 0xa80000>; 397 no-map; 398 }; 399 400 mpss_mem: mpss@8ba00000 { 401 reg = <0x0 0x8ba00000 0x0 0xf600000>; 402 no-map; 403 }; 404 405 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 406 reg = <0x0 0x9b000000 0x0 0x80000>; 407 no-map; 408 }; 409 410 ipa_fw_mem: ipa-fw@9b080000 { 411 reg = <0x0 0x9b080000 0x0 0x10000>; 412 no-map; 413 }; 414 415 ipa_gsi_mem: ipa-gsi@9b090000 { 416 reg = <0x0 0x9b090000 0x0 0xa000>; 417 no-map; 418 }; 419 420 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 421 reg = <0x0 0x9b09a000 0x0 0x2000>; 422 no-map; 423 }; 424 425 spss_region_mem: spss@9b0a0000 { 426 reg = <0x0 0x9b0a0000 0x0 0x1e0000>; 427 no-map; 428 }; 429 430 /* First part of the "SPU secure shared memory" region */ 431 spu_tz_shared_mem: spu-tz-shared@9b280000 { 432 reg = <0x0 0x9b280000 0x0 0x40000>; 433 no-map; 434 }; 435 436 /* Second part of the "SPU secure shared memory" region */ 437 spu_modem_shared_mem: spu-modem-shared@9b2c0000 { 438 reg = <0x0 0x9b2c0000 0x0 0x40000>; 439 no-map; 440 }; 441 442 camera_mem: camera@9b300000 { 443 reg = <0x0 0x9b300000 0x0 0x800000>; 444 no-map; 445 }; 446 447 camera_2_mem: camera-2@9bb00000 { 448 reg = <0x0 0x9bb00000 0x0 0x800000>; 449 no-map; 450 }; 451 452 video_mem: video@9c300000 { 453 reg = <0x0 0x9c300000 0x0 0x800000>; 454 no-map; 455 }; 456 457 cvp_mem: cvp@9cb00000 { 458 reg = <0x0 0x9cb00000 0x0 0x700000>; 459 no-map; 460 }; 461 462 cdsp_mem: cdsp@9d200000 { 463 reg = <0x0 0x9d200000 0x0 0x1900000>; 464 no-map; 465 }; 466 467 q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 { 468 reg = <0x0 0x9eb00000 0x0 0x80000>; 469 no-map; 470 }; 471 472 soccp_mem: soccp@9ec00000 { 473 reg = <0x0 0x9ec00000 0x0 0x180000>; 474 no-map; 475 }; 476 477 q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 { 478 reg = <0x0 0x9ed80000 0x0 0x80000>; 479 no-map; 480 }; 481 482 adspslpi_mem: adspslpi@9ee00000 { 483 reg = <0x0 0x9ee00000 0x0 0x3a80000>; 484 no-map; 485 }; 486 487 xbl_ramdump_mem: xbl-ramdump@b8000000 { 488 reg = <0x0 0xb8000000 0x0 0x1c0000>; 489 no-map; 490 }; 491 492 hwfence_shbuf: hwfence-shbuf@d4e23000 { 493 no-map; 494 reg = <0x0 0xd4e23000 0x0 0x2dd000>; 495 }; 496 497 /* Merged tz_reserved, xbl_sc, and qtee regions */ 498 tz_merged_mem: tz-merged@d8000000 { 499 reg = <0x0 0xd8000000 0x0 0x600000>; 500 no-map; 501 }; 502 503 trust_ui_vm_mem: trust-ui-vm@f3800000 { 504 reg = <0x0 0xf3800000 0x0 0x4400000>; 505 no-map; 506 }; 507 508 oem_vm_mem: oem-vm@f7c00000 { 509 reg = <0x0 0xf7c00000 0x0 0x4c00000>; 510 no-map; 511 }; 512 513 llcc_lpi_mem: llcc-lpi@ff800000 { 514 reg = <0x0 0xff800000 0x0 0x800000>; 515 no-map; 516 }; 517 }; 518 519 soc: soc@0 { 520 compatible = "simple-bus"; 521 522 #address-cells = <2>; 523 #size-cells = <2>; 524 dma-ranges = <0 0 0 0 0x10 0>; 525 ranges = <0 0 0 0 0x10 0>; 526 527 gcc: clock-controller@100000 { 528 compatible = "qcom,sm8750-gcc"; 529 reg = <0x0 0x00100000 0x0 0x1f4200>; 530 531 clocks = <&bi_tcxo_div2>, 532 <0>, 533 <&sleep_clk>, 534 <0>, 535 <0>, 536 <0>, 537 <0>, 538 <0>; 539 540 #clock-cells = <1>; 541 #reset-cells = <1>; 542 #power-domain-cells = <1>; 543 }; 544 545 gpi_dma2: dma-controller@800000 { 546 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 547 reg = <0x0 0x00800000 0x0 0x60000>; 548 549 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 561 562 dma-channels = <12>; 563 dma-channel-mask = <0x1e>; 564 #dma-cells = <3>; 565 566 iommus = <&apps_smmu 0x436 0x0>; 567 568 status = "disabled"; 569 }; 570 571 qupv3_2: geniqup@8c0000 { 572 compatible = "qcom,geni-se-qup"; 573 reg = <0x0 0x008c0000 0x0 0x2000>; 574 575 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 576 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 577 clock-names = "m-ahb", 578 "s-ahb"; 579 580 iommus = <&apps_smmu 0x423 0x0>; 581 582 #address-cells = <2>; 583 #size-cells = <2>; 584 ranges; 585 586 status = "disabled"; 587 588 i2c8: i2c@880000 { 589 compatible = "qcom,geni-i2c"; 590 reg = <0x0 0x00880000 0x0 0x4000>; 591 592 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 593 594 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 595 clock-names = "se"; 596 597 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 598 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 599 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 600 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 601 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 602 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 603 interconnect-names = "qup-core", 604 "qup-config", 605 "qup-memory"; 606 607 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 608 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 609 dma-names = "tx", 610 "rx"; 611 612 pinctrl-0 = <&qup_i2c8_data_clk>; 613 pinctrl-names = "default"; 614 615 #address-cells = <1>; 616 #size-cells = <0>; 617 618 status = "disabled"; 619 }; 620 621 spi8: spi@880000 { 622 compatible = "qcom,geni-spi"; 623 reg = <0x0 0x00880000 0x0 0x4000>; 624 625 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 626 627 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 628 clock-names = "se"; 629 630 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 631 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 632 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 633 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 634 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 635 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 636 interconnect-names = "qup-core", 637 "qup-config", 638 "qup-memory"; 639 640 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 641 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 642 dma-names = "tx", 643 "rx"; 644 645 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 646 pinctrl-names = "default"; 647 648 #address-cells = <1>; 649 #size-cells = <0>; 650 651 status = "disabled"; 652 }; 653 654 i2c9: i2c@884000 { 655 compatible = "qcom,geni-i2c"; 656 reg = <0x0 0x00884000 0x0 0x4000>; 657 658 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 659 660 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 661 clock-names = "se"; 662 663 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 664 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 665 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 666 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 667 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 668 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 669 interconnect-names = "qup-core", 670 "qup-config", 671 "qup-memory"; 672 673 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 674 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 675 dma-names = "tx", 676 "rx"; 677 678 pinctrl-0 = <&qup_i2c9_data_clk>; 679 pinctrl-names = "default"; 680 681 #address-cells = <1>; 682 #size-cells = <0>; 683 684 status = "disabled"; 685 }; 686 687 spi9: spi@884000 { 688 compatible = "qcom,geni-spi"; 689 reg = <0x0 0x00884000 0x0 0x4000>; 690 691 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 692 693 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 694 clock-names = "se"; 695 696 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 697 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 698 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 699 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 700 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 701 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 702 interconnect-names = "qup-core", 703 "qup-config", 704 "qup-memory"; 705 706 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 707 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 708 dma-names = "tx", 709 "rx"; 710 711 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 712 pinctrl-names = "default"; 713 714 #address-cells = <1>; 715 #size-cells = <0>; 716 717 status = "disabled"; 718 }; 719 720 i2c10: i2c@888000 { 721 compatible = "qcom,geni-i2c"; 722 reg = <0x0 0x00888000 0x0 0x4000>; 723 724 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 725 726 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 727 clock-names = "se"; 728 729 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 730 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 731 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 732 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 733 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 734 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 735 interconnect-names = "qup-core", 736 "qup-config", 737 "qup-memory"; 738 739 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 740 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 741 dma-names = "tx", 742 "rx"; 743 744 pinctrl-0 = <&qup_i2c10_data_clk>; 745 pinctrl-names = "default"; 746 747 #address-cells = <1>; 748 #size-cells = <0>; 749 750 status = "disabled"; 751 }; 752 753 spi10: spi@888000 { 754 compatible = "qcom,geni-spi"; 755 reg = <0x0 0x00888000 0x0 0x4000>; 756 757 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 758 759 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 760 clock-names = "se"; 761 762 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 763 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 764 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 765 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 766 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 767 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 768 interconnect-names = "qup-core", 769 "qup-config", 770 "qup-memory"; 771 772 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 773 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 774 dma-names = "tx", 775 "rx"; 776 777 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 778 pinctrl-names = "default"; 779 780 #address-cells = <1>; 781 #size-cells = <0>; 782 783 status = "disabled"; 784 }; 785 786 i2c11: i2c@88c000 { 787 compatible = "qcom,geni-i2c"; 788 reg = <0x0 0x0088c000 0x0 0x4000>; 789 790 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 791 792 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 793 clock-names = "se"; 794 795 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 796 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 797 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 798 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 799 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 800 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 801 interconnect-names = "qup-core", 802 "qup-config", 803 "qup-memory"; 804 805 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 806 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 807 dma-names = "tx", 808 "rx"; 809 810 pinctrl-0 = <&qup_i2c11_data_clk>; 811 pinctrl-names = "default"; 812 813 #address-cells = <1>; 814 #size-cells = <0>; 815 816 status = "disabled"; 817 }; 818 819 spi11: spi@88c000 { 820 compatible = "qcom,geni-spi"; 821 reg = <0x0 0x0088c000 0x0 0x4000>; 822 823 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 824 825 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 826 clock-names = "se"; 827 828 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 829 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 830 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 831 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 832 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 833 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 834 interconnect-names = "qup-core", 835 "qup-config", 836 "qup-memory"; 837 838 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 839 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 840 dma-names = "tx", 841 "rx"; 842 843 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 844 pinctrl-names = "default"; 845 846 #address-cells = <1>; 847 #size-cells = <0>; 848 849 status = "disabled"; 850 }; 851 852 i2c12: i2c@890000 { 853 compatible = "qcom,geni-i2c"; 854 reg = <0x0 0x00890000 0x0 0x4000>; 855 856 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 857 858 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 859 clock-names = "se"; 860 861 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 862 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 863 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 864 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 865 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 866 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 867 interconnect-names = "qup-core", 868 "qup-config", 869 "qup-memory"; 870 871 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 872 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 873 dma-names = "tx", 874 "rx"; 875 876 pinctrl-0 = <&qup_i2c12_data_clk>; 877 pinctrl-names = "default"; 878 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 status = "disabled"; 883 }; 884 885 spi12: spi@890000 { 886 compatible = "qcom,geni-spi"; 887 reg = <0x0 0x00890000 0x0 0x4000>; 888 889 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 890 891 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 892 clock-names = "se"; 893 894 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 895 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 896 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 897 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 898 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 899 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 900 interconnect-names = "qup-core", 901 "qup-config", 902 "qup-memory"; 903 904 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 905 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 906 dma-names = "tx", 907 "rx"; 908 909 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 910 pinctrl-names = "default"; 911 912 #address-cells = <1>; 913 #size-cells = <0>; 914 915 status = "disabled"; 916 }; 917 918 i2c13: i2c@894000 { 919 compatible = "qcom,geni-i2c"; 920 reg = <0x0 0x00894000 0x0 0x4000>; 921 922 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 923 924 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 925 clock-names = "se"; 926 927 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 928 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 929 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 930 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 931 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 932 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 933 interconnect-names = "qup-core", 934 "qup-config", 935 "qup-memory"; 936 937 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 938 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 939 dma-names = "tx", 940 "rx"; 941 942 pinctrl-0 = <&qup_i2c13_data_clk>; 943 pinctrl-names = "default"; 944 945 #address-cells = <1>; 946 #size-cells = <0>; 947 948 status = "disabled"; 949 }; 950 951 spi13: spi@894000 { 952 compatible = "qcom,geni-spi"; 953 reg = <0x0 0x00894000 0x0 0x4000>; 954 955 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 956 957 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 958 clock-names = "se"; 959 960 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 961 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 962 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 963 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 964 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 965 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 966 interconnect-names = "qup-core", 967 "qup-config", 968 "qup-memory"; 969 970 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 971 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 972 dma-names = "tx", 973 "rx"; 974 975 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 976 pinctrl-names = "default"; 977 978 #address-cells = <1>; 979 #size-cells = <0>; 980 981 status = "disabled"; 982 }; 983 984 uart14: serial@898000 { 985 compatible = "qcom,geni-uart"; 986 reg = <0x0 0x00898000 0x0 0x4000>; 987 988 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 989 990 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 991 clock-names = "se"; 992 993 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 994 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 995 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 996 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 997 interconnect-names = "qup-core", 998 "qup-config"; 999 1000 pinctrl-0 = <&qup_uart14_default>; 1001 pinctrl-names = "default"; 1002 1003 status = "disabled"; 1004 }; 1005 1006 i2c15: i2c@89c000 { 1007 compatible = "qcom,geni-i2c"; 1008 reg = <0x0 0x0089c000 0x0 0x4000>; 1009 1010 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1011 1012 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1013 clock-names = "se"; 1014 1015 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1016 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1017 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1018 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1019 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1020 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1021 interconnect-names = "qup-core", 1022 "qup-config", 1023 "qup-memory"; 1024 1025 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1026 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1027 dma-names = "tx", 1028 "rx"; 1029 1030 pinctrl-0 = <&qup_i2c15_data_clk>; 1031 pinctrl-names = "default"; 1032 1033 #address-cells = <1>; 1034 #size-cells = <0>; 1035 1036 status = "disabled"; 1037 }; 1038 1039 spi15: spi@89c000 { 1040 compatible = "qcom,geni-spi"; 1041 reg = <0x0 0x0089c000 0x0 0x4000>; 1042 1043 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1044 1045 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1046 clock-names = "se"; 1047 1048 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1049 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1050 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1051 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1052 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1053 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1054 interconnect-names = "qup-core", 1055 "qup-config", 1056 "qup-memory"; 1057 1058 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1059 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1060 dma-names = "tx", 1061 "rx"; 1062 1063 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1064 pinctrl-names = "default"; 1065 1066 #address-cells = <1>; 1067 #size-cells = <0>; 1068 1069 status = "disabled"; 1070 }; 1071 }; 1072 1073 i2c_master_hub_0: geniqup@9c0000 { 1074 compatible = "qcom,geni-se-i2c-master-hub"; 1075 reg = <0x0 0x009c0000 0x0 0x2000>; 1076 1077 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1078 clock-names = "s-ahb"; 1079 1080 #address-cells = <2>; 1081 #size-cells = <2>; 1082 ranges; 1083 1084 status = "disabled"; 1085 1086 i2c_hub_0: i2c@980000 { 1087 compatible = "qcom,geni-i2c-master-hub"; 1088 reg = <0x0 0x00980000 0x0 0x4000>; 1089 1090 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1091 1092 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1093 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1094 clock-names = "se", 1095 "core"; 1096 1097 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1098 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1099 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1100 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1101 interconnect-names = "qup-core", 1102 "qup-config"; 1103 1104 pinctrl-0 = <&hub_i2c0_data_clk>; 1105 pinctrl-names = "default"; 1106 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 1110 status = "disabled"; 1111 }; 1112 1113 i2c_hub_1: i2c@984000 { 1114 compatible = "qcom,geni-i2c-master-hub"; 1115 reg = <0x0 0x00984000 0x0 0x4000>; 1116 1117 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1118 1119 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1120 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1121 clock-names = "se", 1122 "core"; 1123 1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1125 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1126 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1127 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1128 interconnect-names = "qup-core", 1129 "qup-config"; 1130 1131 pinctrl-0 = <&hub_i2c1_data_clk>; 1132 pinctrl-names = "default"; 1133 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 1137 status = "disabled"; 1138 }; 1139 1140 i2c_hub_2: i2c@988000 { 1141 compatible = "qcom,geni-i2c-master-hub"; 1142 reg = <0x0 0x00988000 0x0 0x4000>; 1143 1144 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1145 1146 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1147 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1148 clock-names = "se", 1149 "core"; 1150 1151 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1152 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1153 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1154 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1155 interconnect-names = "qup-core", 1156 "qup-config"; 1157 1158 pinctrl-0 = <&hub_i2c2_data_clk>; 1159 pinctrl-names = "default"; 1160 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 1164 status = "disabled"; 1165 }; 1166 1167 i2c_hub_3: i2c@98c000 { 1168 compatible = "qcom,geni-i2c-master-hub"; 1169 reg = <0x0 0x0098c000 0x0 0x4000>; 1170 1171 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1172 1173 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1174 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1175 clock-names = "se", 1176 "core"; 1177 1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1179 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1180 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1181 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1182 interconnect-names = "qup-core", 1183 "qup-config"; 1184 1185 pinctrl-0 = <&hub_i2c3_data_clk>; 1186 pinctrl-names = "default"; 1187 1188 #address-cells = <1>; 1189 #size-cells = <0>; 1190 1191 status = "disabled"; 1192 }; 1193 1194 i2c_hub_4: i2c@990000 { 1195 compatible = "qcom,geni-i2c-master-hub"; 1196 reg = <0x0 0x00990000 0x0 0x4000>; 1197 1198 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1199 1200 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1201 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1202 clock-names = "se", 1203 "core"; 1204 1205 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1206 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1207 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1208 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1209 interconnect-names = "qup-core", 1210 "qup-config"; 1211 1212 pinctrl-0 = <&hub_i2c4_data_clk>; 1213 pinctrl-names = "default"; 1214 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 1218 status = "disabled"; 1219 }; 1220 1221 i2c_hub_5: i2c@994000 { 1222 compatible = "qcom,geni-i2c-master-hub"; 1223 reg = <0x0 0x00994000 0x0 0x4000>; 1224 1225 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1226 1227 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1228 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1229 clock-names = "se", 1230 "core"; 1231 1232 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1233 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1234 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1235 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1236 interconnect-names = "qup-core", 1237 "qup-config"; 1238 1239 pinctrl-0 = <&hub_i2c5_data_clk>; 1240 pinctrl-names = "default"; 1241 1242 #address-cells = <1>; 1243 #size-cells = <0>; 1244 1245 status = "disabled"; 1246 }; 1247 1248 i2c_hub_6: i2c@998000 { 1249 compatible = "qcom,geni-i2c-master-hub"; 1250 reg = <0x0 0x00998000 0x0 0x4000>; 1251 1252 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1253 1254 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1255 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1256 clock-names = "se", 1257 "core"; 1258 1259 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1260 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1261 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1262 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1263 interconnect-names = "qup-core", 1264 "qup-config"; 1265 1266 pinctrl-0 = <&hub_i2c6_data_clk>; 1267 pinctrl-names = "default"; 1268 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 1272 status = "disabled"; 1273 }; 1274 1275 i2c_hub_7: i2c@99c000 { 1276 compatible = "qcom,geni-i2c-master-hub"; 1277 reg = <0x0 0x0099c000 0x0 0x4000>; 1278 1279 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1280 1281 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1282 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1283 clock-names = "se", 1284 "core"; 1285 1286 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1287 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1288 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1289 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1290 interconnect-names = "qup-core", 1291 "qup-config"; 1292 1293 pinctrl-0 = <&hub_i2c7_data_clk>; 1294 pinctrl-names = "default"; 1295 1296 #address-cells = <1>; 1297 #size-cells = <0>; 1298 1299 status = "disabled"; 1300 }; 1301 1302 i2c_hub_8: i2c@9a0000 { 1303 compatible = "qcom,geni-i2c-master-hub"; 1304 reg = <0x0 0x009a0000 0x0 0x4000>; 1305 1306 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1307 1308 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1309 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1310 clock-names = "se", 1311 "core"; 1312 1313 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1314 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1316 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1317 interconnect-names = "qup-core", 1318 "qup-config"; 1319 1320 pinctrl-0 = <&hub_i2c8_data_clk>; 1321 pinctrl-names = "default"; 1322 1323 #address-cells = <1>; 1324 #size-cells = <0>; 1325 1326 status = "disabled"; 1327 }; 1328 1329 i2c_hub_9: i2c@9a4000 { 1330 compatible = "qcom,geni-i2c-master-hub"; 1331 reg = <0x0 0x009a4000 0x0 0x4000>; 1332 1333 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1334 1335 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1336 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1337 clock-names = "se", 1338 "core"; 1339 1340 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1341 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1342 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1343 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1344 interconnect-names = "qup-core", 1345 "qup-config"; 1346 1347 pinctrl-0 = <&hub_i2c9_data_clk>; 1348 pinctrl-names = "default"; 1349 1350 #address-cells = <1>; 1351 #size-cells = <0>; 1352 1353 status = "disabled"; 1354 }; 1355 }; 1356 1357 gpi_dma1: dma-controller@a00000 { 1358 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 1359 reg = <0x0 0x00a00000 0x0 0x60000>; 1360 1361 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1373 1374 dma-channels = <12>; 1375 dma-channel-mask = <0x1e>; 1376 #dma-cells = <3>; 1377 1378 iommus = <&apps_smmu 0xb6 0x0>; 1379 1380 status = "disabled"; 1381 }; 1382 1383 qupv3_1: geniqup@ac0000 { 1384 compatible = "qcom,geni-se-qup"; 1385 reg = <0x0 0x00ac0000 0x0 0x2000>; 1386 1387 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1388 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1389 clock-names = "m-ahb", 1390 "s-ahb"; 1391 1392 iommus = <&apps_smmu 0xa3 0x0>; 1393 1394 #address-cells = <2>; 1395 #size-cells = <2>; 1396 ranges; 1397 1398 status = "disabled"; 1399 1400 i2c0: i2c@a80000 { 1401 compatible = "qcom,geni-i2c"; 1402 reg = <0x0 0x00a80000 0x0 0x4000>; 1403 1404 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1405 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1407 clock-names = "se"; 1408 1409 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1410 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1411 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1412 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1413 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1414 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1415 interconnect-names = "qup-core", 1416 "qup-config", 1417 "qup-memory"; 1418 1419 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1420 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1421 dma-names = "tx", 1422 "rx"; 1423 1424 pinctrl-0 = <&qup_i2c0_data_clk>; 1425 pinctrl-names = "default"; 1426 1427 #address-cells = <1>; 1428 #size-cells = <0>; 1429 1430 status = "disabled"; 1431 }; 1432 1433 spi0: spi@a80000 { 1434 compatible = "qcom,geni-spi"; 1435 reg = <0x0 0x00a80000 0x0 0x4000>; 1436 1437 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1438 1439 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1440 clock-names = "se"; 1441 1442 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1443 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1444 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1445 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1446 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1447 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1448 interconnect-names = "qup-core", 1449 "qup-config", 1450 "qup-memory"; 1451 1452 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1453 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1454 dma-names = "tx", 1455 "rx"; 1456 1457 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1458 pinctrl-names = "default"; 1459 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 1463 status = "disabled"; 1464 }; 1465 1466 i2c1: i2c@a84000 { 1467 compatible = "qcom,geni-i2c"; 1468 reg = <0x0 0x00a84000 0x0 0x4000>; 1469 1470 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1471 1472 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1473 clock-names = "se"; 1474 1475 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1476 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1477 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1478 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1479 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1480 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1481 interconnect-names = "qup-core", 1482 "qup-config", 1483 "qup-memory"; 1484 1485 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1486 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1487 dma-names = "tx", 1488 "rx"; 1489 1490 pinctrl-0 = <&qup_i2c1_data_clk>; 1491 pinctrl-names = "default"; 1492 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 1496 status = "disabled"; 1497 }; 1498 1499 spi1: spi@a84000 { 1500 compatible = "qcom,geni-spi"; 1501 reg = <0x0 0x00a84000 0x0 0x4000>; 1502 1503 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1504 1505 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1506 clock-names = "se"; 1507 1508 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1509 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1510 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1511 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1512 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1513 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1514 interconnect-names = "qup-core", 1515 "qup-config", 1516 "qup-memory"; 1517 1518 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1519 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1520 dma-names = "tx", 1521 "rx"; 1522 1523 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1524 pinctrl-names = "default"; 1525 1526 #address-cells = <1>; 1527 #size-cells = <0>; 1528 1529 status = "disabled"; 1530 }; 1531 1532 i2c2: i2c@a88000 { 1533 compatible = "qcom,geni-i2c"; 1534 reg = <0x0 0x00a88000 0x0 0x4000>; 1535 1536 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1537 1538 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1539 clock-names = "se"; 1540 1541 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1542 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1543 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1544 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1545 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1546 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1547 interconnect-names = "qup-core", 1548 "qup-config", 1549 "qup-memory"; 1550 1551 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1552 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1553 dma-names = "tx", 1554 "rx"; 1555 1556 pinctrl-0 = <&qup_i2c2_data_clk>; 1557 pinctrl-names = "default"; 1558 1559 #address-cells = <1>; 1560 #size-cells = <0>; 1561 1562 status = "disabled"; 1563 }; 1564 1565 spi2: spi@a88000 { 1566 compatible = "qcom,geni-spi"; 1567 reg = <0x0 0x00a88000 0x0 0x4000>; 1568 1569 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1570 1571 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1572 clock-names = "se"; 1573 1574 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1575 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1576 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1577 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1578 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1579 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1580 interconnect-names = "qup-core", 1581 "qup-config", 1582 "qup-memory"; 1583 1584 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1585 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1586 dma-names = "tx", 1587 "rx"; 1588 1589 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1590 pinctrl-names = "default"; 1591 1592 #address-cells = <1>; 1593 #size-cells = <0>; 1594 1595 status = "disabled"; 1596 }; 1597 1598 i2c3: i2c@a8c000 { 1599 compatible = "qcom,geni-i2c"; 1600 reg = <0x0 0x00a8c000 0x0 0x4000>; 1601 1602 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1603 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1605 clock-names = "se"; 1606 1607 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1608 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1609 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1610 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1611 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1612 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1613 interconnect-names = "qup-core", 1614 "qup-config", 1615 "qup-memory"; 1616 1617 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1618 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1619 dma-names = "tx", 1620 "rx"; 1621 1622 pinctrl-0 = <&qup_i2c3_data_clk>; 1623 pinctrl-names = "default"; 1624 1625 #address-cells = <1>; 1626 #size-cells = <0>; 1627 1628 status = "disabled"; 1629 }; 1630 1631 spi3: spi@a8c000 { 1632 compatible = "qcom,geni-spi"; 1633 reg = <0x0 0x00a8c000 0x0 0x4000>; 1634 1635 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1636 1637 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1638 clock-names = "se"; 1639 1640 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1641 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1642 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1643 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1644 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1645 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1646 interconnect-names = "qup-core", 1647 "qup-config", 1648 "qup-memory"; 1649 1650 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1651 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1652 dma-names = "tx", 1653 "rx"; 1654 1655 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1656 pinctrl-names = "default"; 1657 1658 #address-cells = <1>; 1659 #size-cells = <0>; 1660 1661 status = "disabled"; 1662 }; 1663 1664 i2c4: i2c@a90000 { 1665 compatible = "qcom,geni-i2c"; 1666 reg = <0x0 0x00a90000 0x0 0x4000>; 1667 1668 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1669 1670 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1671 clock-names = "se"; 1672 1673 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1674 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1675 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1676 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1677 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1678 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1679 interconnect-names = "qup-core", 1680 "qup-config", 1681 "qup-memory"; 1682 1683 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1684 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1685 dma-names = "tx", 1686 "rx"; 1687 1688 pinctrl-0 = <&qup_i2c4_data_clk>; 1689 pinctrl-names = "default"; 1690 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 1694 status = "disabled"; 1695 }; 1696 1697 spi4: spi@a90000 { 1698 compatible = "qcom,geni-spi"; 1699 reg = <0x0 0x00a90000 0x0 0x4000>; 1700 1701 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1702 1703 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1704 clock-names = "se"; 1705 1706 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1707 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1708 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1709 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1710 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1711 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1712 interconnect-names = "qup-core", 1713 "qup-config", 1714 "qup-memory"; 1715 1716 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1717 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1718 dma-names = "tx", 1719 "rx"; 1720 1721 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1722 pinctrl-names = "default"; 1723 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 1727 status = "disabled"; 1728 }; 1729 1730 i2c5: i2c@a94000 { 1731 compatible = "qcom,geni-i2c"; 1732 reg = <0x0 0x00a94000 0x0 0x4000>; 1733 1734 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1735 1736 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1737 clock-names = "se"; 1738 1739 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1740 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1741 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1742 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1743 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1744 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1745 interconnect-names = "qup-core", 1746 "qup-config", 1747 "qup-memory"; 1748 1749 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1750 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1751 dma-names = "tx", 1752 "rx"; 1753 1754 pinctrl-0 = <&qup_i2c5_data_clk>; 1755 pinctrl-names = "default"; 1756 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 1760 status = "disabled"; 1761 }; 1762 1763 spi5: spi@a94000 { 1764 compatible = "qcom,geni-spi"; 1765 reg = <0x0 0x00a94000 0x0 0x4000>; 1766 1767 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1768 1769 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1770 clock-names = "se"; 1771 1772 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1773 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1774 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1775 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1776 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1777 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1778 interconnect-names = "qup-core", 1779 "qup-config", 1780 "qup-memory"; 1781 1782 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1783 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1784 dma-names = "tx", 1785 "rx"; 1786 1787 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1788 pinctrl-names = "default"; 1789 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 1793 status = "disabled"; 1794 }; 1795 1796 i2c6: i2c@a98000 { 1797 compatible = "qcom,geni-i2c"; 1798 reg = <0x0 0x00a98000 0x0 0x4000>; 1799 1800 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1801 1802 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1803 clock-names = "se"; 1804 1805 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1806 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1807 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1808 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1809 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1810 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1811 interconnect-names = "qup-core", 1812 "qup-config", 1813 "qup-memory"; 1814 1815 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1816 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1817 dma-names = "tx", 1818 "rx"; 1819 1820 pinctrl-0 = <&qup_i2c6_data_clk>; 1821 pinctrl-names = "default"; 1822 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 1826 status = "disabled"; 1827 }; 1828 1829 spi6: spi@a98000 { 1830 compatible = "qcom,geni-spi"; 1831 reg = <0x0 0x00a98000 0x0 0x4000>; 1832 1833 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1834 1835 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1836 clock-names = "se"; 1837 1838 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1839 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1840 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1841 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1842 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1843 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1844 interconnect-names = "qup-core", 1845 "qup-config", 1846 "qup-memory"; 1847 1848 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1849 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1850 dma-names = "tx", 1851 "rx"; 1852 1853 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1854 pinctrl-names = "default"; 1855 1856 #address-cells = <1>; 1857 #size-cells = <0>; 1858 1859 status = "disabled"; 1860 }; 1861 1862 uart7: serial@a9c000 { 1863 compatible = "qcom,geni-debug-uart"; 1864 reg = <0x0 0x00a9c000 0x0 0x4000>; 1865 1866 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1867 1868 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1869 clock-names = "se"; 1870 1871 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1872 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1873 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1874 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1875 interconnect-names = "qup-core", 1876 "qup-config"; 1877 1878 1879 pinctrl-0 = <&qup_uart7_default>; 1880 pinctrl-names = "default"; 1881 1882 status = "disabled"; 1883 }; 1884 }; 1885 1886 cnoc_main: interconnect@1500000 { 1887 compatible = "qcom,sm8750-cnoc-main"; 1888 reg = <0x0 0x01500000 0x0 0x16080>; 1889 qcom,bcm-voters = <&apps_bcm_voter>; 1890 #interconnect-cells = <2>; 1891 }; 1892 1893 config_noc: interconnect@1600000 { 1894 compatible = "qcom,sm8750-config-noc"; 1895 reg = <0x0 0x01600000 0x0 0x6200>; 1896 qcom,bcm-voters = <&apps_bcm_voter>; 1897 #interconnect-cells = <2>; 1898 }; 1899 1900 system_noc: interconnect@1680000 { 1901 compatible = "qcom,sm8750-system-noc"; 1902 reg = <0x0 0x01680000 0x0 0x1d080>; 1903 qcom,bcm-voters = <&apps_bcm_voter>; 1904 #interconnect-cells = <2>; 1905 }; 1906 1907 pcie_noc: interconnect@16c0000 { 1908 compatible = "qcom,sm8750-pcie-anoc"; 1909 reg = <0x0 0x016c0000 0x0 0x11400>; 1910 qcom,bcm-voters = <&apps_bcm_voter>; 1911 #interconnect-cells = <2>; 1912 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1913 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1914 1915 }; 1916 1917 aggre1_noc: interconnect@16e0000 { 1918 compatible = "qcom,sm8750-aggre1-noc"; 1919 reg = <0x0 0x016e0000 0x0 0x16400>; 1920 qcom,bcm-voters = <&apps_bcm_voter>; 1921 #interconnect-cells = <2>; 1922 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1923 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 1924 1925 }; 1926 1927 aggre2_noc: interconnect@1700000 { 1928 compatible = "qcom,sm8750-aggre2-noc"; 1929 reg = <0x0 0x01700000 0x0 0x1f400>; 1930 qcom,bcm-voters = <&apps_bcm_voter>; 1931 #interconnect-cells = <2>; 1932 clocks = <&rpmhcc RPMH_IPA_CLK>; 1933 }; 1934 1935 mmss_noc: interconnect@1780000 { 1936 compatible = "qcom,sm8750-mmss-noc"; 1937 reg = <0x0 0x01780000 0x0 0x5b800>; 1938 qcom,bcm-voters = <&apps_bcm_voter>; 1939 #interconnect-cells = <2>; 1940 }; 1941 1942 tcsr_mutex: hwlock@1f40000 { 1943 compatible = "qcom,tcsr-mutex"; 1944 reg = <0x0 0x01f40000 0x0 0x20000>; 1945 #hwlock-cells = <1>; 1946 }; 1947 1948 lpass_ag_noc: interconnect@7e40000 { 1949 compatible = "qcom,sm8750-lpass-ag-noc"; 1950 reg = <0x0 0x07e40000 0x0 0xe080>; 1951 qcom,bcm-voters = <&apps_bcm_voter>; 1952 #interconnect-cells = <2>; 1953 }; 1954 1955 lpass_lpiaon_noc: interconnect@7400000 { 1956 compatible = "qcom,sm8750-lpass-lpiaon-noc"; 1957 reg = <0x0 0x07400000 0x0 0x19080>; 1958 qcom,bcm-voters = <&apps_bcm_voter>; 1959 #interconnect-cells = <2>; 1960 }; 1961 1962 lpass_lpicx_noc: interconnect@7420000 { 1963 compatible = "qcom,sm8750-lpass-lpicx-noc"; 1964 reg = <0x0 0x07420000 0x0 0x44080>; 1965 qcom,bcm-voters = <&apps_bcm_voter>; 1966 #interconnect-cells = <2>; 1967 }; 1968 1969 pdc: interrupt-controller@b220000 { 1970 compatible = "qcom,sm8750-pdc", "qcom,pdc"; 1971 reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; 1972 1973 qcom,pdc-ranges = <0 745 51>, <51 527 47>, 1974 <98 609 32>, <130 717 12>, 1975 <142 251 5>, <147 796 16>; 1976 #interrupt-cells = <2>; 1977 interrupt-parent = <&intc>; 1978 interrupt-controller; 1979 }; 1980 1981 spmi_bus: spmi@c400000 { 1982 compatible = "qcom,spmi-pmic-arb"; 1983 reg = <0x0 0x0c400000 0x0 0x3000>, 1984 <0x0 0x0c500000 0x0 0x400000>, 1985 <0x0 0x0c440000 0x0 0x80000>, 1986 <0x0 0x0c4c0000 0x0 0x10000>, 1987 <0x0 0x0c42d000 0x0 0x4000>; 1988 reg-names = "core", 1989 "chnls", 1990 "obsrvr", 1991 "intr", 1992 "cnfg"; 1993 1994 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1995 interrupt-names = "periph_irq"; 1996 1997 qcom,ee = <0>; 1998 qcom,channel = <0>; 1999 qcom,bus-id = <0>; 2000 2001 interrupt-controller; 2002 #interrupt-cells = <4>; 2003 2004 #address-cells = <2>; 2005 #size-cells = <0>; 2006 }; 2007 2008 tlmm: pinctrl@f100000 { 2009 compatible = "qcom,sm8750-tlmm"; 2010 reg = <0x0 0x0f100000 0x0 0x102000>; 2011 2012 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2013 2014 gpio-controller; 2015 #gpio-cells = <2>; 2016 2017 interrupt-controller; 2018 #interrupt-cells = <2>; 2019 2020 gpio-ranges = <&tlmm 0 0 216>; 2021 wakeup-parent = <&pdc>; 2022 2023 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 2024 /* SDA, SCL */ 2025 pins = "gpio64", "gpio65"; 2026 function = "i2chub0_se0"; 2027 drive-strength = <2>; 2028 bias-pull-up; 2029 }; 2030 2031 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 2032 /* SDA, SCL */ 2033 pins = "gpio66", "gpio67"; 2034 function = "i2chub0_se1"; 2035 drive-strength = <2>; 2036 bias-pull-up; 2037 }; 2038 2039 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 2040 /* SDA, SCL */ 2041 pins = "gpio68", "gpio69"; 2042 function = "i2chub0_se2"; 2043 drive-strength = <2>; 2044 bias-pull-up; 2045 }; 2046 2047 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 2048 /* SDA, SCL */ 2049 pins = "gpio70", "gpio71"; 2050 function = "i2chub0_se3"; 2051 drive-strength = <2>; 2052 bias-pull-up; 2053 }; 2054 2055 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 2056 /* SDA, SCL */ 2057 pins = "gpio72", "gpio73"; 2058 function = "i2chub0_se4"; 2059 drive-strength = <2>; 2060 bias-pull-up; 2061 }; 2062 2063 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 2064 /* SDA, SCL */ 2065 pins = "gpio74", "gpio75"; 2066 function = "i2chub0_se5"; 2067 drive-strength = <2>; 2068 bias-pull-up; 2069 }; 2070 2071 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 2072 /* SDA, SCL */ 2073 pins = "gpio76", "gpio77"; 2074 function = "i2chub0_se6"; 2075 drive-strength = <2>; 2076 bias-pull-up; 2077 }; 2078 2079 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 2080 /* SDA, SCL */ 2081 pins = "gpio82", "gpio83"; 2082 function = "i2chub0_se7"; 2083 drive-strength = <2>; 2084 bias-pull-up; 2085 }; 2086 2087 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 2088 /* SDA, SCL */ 2089 pins = "gpio206", "gpio207"; 2090 function = "i2chub0_se8"; 2091 drive-strength = <2>; 2092 bias-pull-up; 2093 }; 2094 2095 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 2096 /* SDA, SCL */ 2097 pins = "gpio80", "gpio81"; 2098 function = "i2chub0_se9"; 2099 drive-strength = <2>; 2100 bias-pull-up; 2101 }; 2102 2103 pcie0_default_state: pcie0-default-state { 2104 perst-pins { 2105 pins = "gpio102"; 2106 function = "gpio"; 2107 drive-strength = <2>; 2108 bias-pull-down; 2109 }; 2110 2111 clkreq-pins { 2112 pins = "gpio103"; 2113 function = "pcie0_clk_req_n"; 2114 drive-strength = <2>; 2115 bias-pull-up; 2116 }; 2117 2118 wake-pins { 2119 pins = "gpio104"; 2120 function = "gpio"; 2121 drive-strength = <2>; 2122 bias-pull-up; 2123 }; 2124 }; 2125 2126 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2127 /* SDA, SCL */ 2128 pins = "gpio32", "gpio33"; 2129 function = "qup1_se0"; 2130 drive-strength = <2>; 2131 bias-pull-up; 2132 }; 2133 2134 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2135 /* SDA, SCL */ 2136 pins = "gpio36", "gpio37"; 2137 function = "qup1_se1"; 2138 drive-strength = <2>; 2139 bias-pull-up; 2140 }; 2141 2142 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2143 /* SDA, SCL */ 2144 pins = "gpio40", "gpio41"; 2145 function = "qup1_se2"; 2146 drive-strength = <2>; 2147 bias-pull-up; 2148 }; 2149 2150 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2151 /* SDA, SCL */ 2152 pins = "gpio44", "gpio45"; 2153 function = "qup1_se3"; 2154 drive-strength = <2>; 2155 bias-pull-up; 2156 }; 2157 2158 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2159 /* SDA, SCL */ 2160 pins = "gpio48", "gpio49"; 2161 function = "qup1_se4"; 2162 drive-strength = <2>; 2163 bias-pull-up; 2164 }; 2165 2166 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2167 /* SDA, SCL */ 2168 pins = "gpio52", "gpio53"; 2169 function = "qup1_se5"; 2170 drive-strength = <2>; 2171 bias-pull-up; 2172 }; 2173 2174 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2175 /* SDA, SCL */ 2176 pins = "gpio56", "gpio57"; 2177 function = "qup1_se6"; 2178 drive-strength = <2>; 2179 bias-pull-up; 2180 }; 2181 2182 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2183 /* SDA, SCL */ 2184 pins = "gpio0", "gpio1"; 2185 function = "qup2_se0"; 2186 drive-strength = <2>; 2187 bias-pull-up; 2188 }; 2189 2190 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2191 /* SDA, SCL */ 2192 pins = "gpio4", "gpio5"; 2193 function = "qup2_se1"; 2194 drive-strength = <2>; 2195 bias-pull-up; 2196 }; 2197 2198 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2199 /* SDA, SCL */ 2200 pins = "gpio8", "gpio9"; 2201 function = "qup2_se2"; 2202 drive-strength = <2>; 2203 bias-pull-up; 2204 }; 2205 2206 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 2207 /* SDA, SCL */ 2208 pins = "gpio12", "gpio13"; 2209 function = "qup2_se3"; 2210 drive-strength = <2>; 2211 bias-pull-up; 2212 }; 2213 2214 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 2215 /* SDA, SCL */ 2216 pins = "gpio16", "gpio17"; 2217 function = "qup2_se4"; 2218 drive-strength = <2>; 2219 bias-pull-up; 2220 }; 2221 2222 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 2223 /* SDA, SCL */ 2224 pins = "gpio20", "gpio21"; 2225 function = "qup2_se5"; 2226 drive-strength = <2>; 2227 bias-pull-up; 2228 }; 2229 2230 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 2231 /* SDA, SCL */ 2232 pins = "gpio28", "gpio29"; 2233 function = "qup2_se7"; 2234 drive-strength = <2>; 2235 bias-pull-up; 2236 }; 2237 2238 qup_spi0_cs: qup-spi0-cs-state { 2239 pins = "gpio35"; 2240 function = "qup1_se0"; 2241 drive-strength = <6>; 2242 bias-disable; 2243 }; 2244 2245 qup_spi0_data_clk: qup-spi0-data-clk-state { 2246 /* MISO, MOSI, CLK */ 2247 pins = "gpio32", "gpio33", "gpio34"; 2248 function = "qup1_se0"; 2249 drive-strength = <6>; 2250 bias-disable; 2251 }; 2252 2253 qup_spi1_cs: qup-spi1-cs-state { 2254 pins = "gpio39"; 2255 function = "qup1_se1"; 2256 drive-strength = <6>; 2257 bias-disable; 2258 }; 2259 2260 qup_spi1_data_clk: qup-spi1-data-clk-state { 2261 /* MISO, MOSI, CLK */ 2262 pins = "gpio36", "gpio37", "gpio38"; 2263 function = "qup1_se1"; 2264 drive-strength = <6>; 2265 bias-disable; 2266 }; 2267 2268 qup_spi2_cs: qup-spi2-cs-state { 2269 pins = "gpio43"; 2270 function = "qup1_se2"; 2271 drive-strength = <6>; 2272 bias-disable; 2273 }; 2274 2275 qup_spi2_data_clk: qup-spi2-data-clk-state { 2276 /* MISO, MOSI, CLK */ 2277 pins = "gpio40", "gpio41", "gpio42"; 2278 function = "qup1_se2"; 2279 drive-strength = <6>; 2280 bias-disable; 2281 }; 2282 2283 qup_spi3_cs: qup-spi3-cs-state { 2284 pins = "gpio47"; 2285 function = "qup1_se3"; 2286 drive-strength = <6>; 2287 bias-disable; 2288 }; 2289 2290 qup_spi3_data_clk: qup-spi3-data-clk-state { 2291 /* MISO, MOSI, CLK */ 2292 pins = "gpio44", "gpio45", "gpio46"; 2293 function = "qup1_se3"; 2294 drive-strength = <6>; 2295 bias-disable; 2296 }; 2297 2298 qup_spi4_cs: qup-spi4-cs-state { 2299 pins = "gpio51"; 2300 function = "qup1_se4"; 2301 drive-strength = <6>; 2302 bias-disable; 2303 }; 2304 2305 qup_spi4_data_clk: qup-spi4-data-clk-state { 2306 /* MISO, MOSI, CLK */ 2307 pins = "gpio48", "gpio49", "gpio50"; 2308 function = "qup1_se4"; 2309 drive-strength = <6>; 2310 bias-disable; 2311 }; 2312 2313 qup_spi5_cs: qup-spi5-cs-state { 2314 pins = "gpio55"; 2315 function = "qup1_se5"; 2316 drive-strength = <6>; 2317 bias-disable; 2318 }; 2319 2320 qup_spi5_data_clk: qup-spi5-data-clk-state { 2321 /* MISO, MOSI, CLK */ 2322 pins = "gpio52", "gpio53", "gpio54"; 2323 function = "qup1_se5"; 2324 drive-strength = <6>; 2325 bias-disable; 2326 }; 2327 2328 qup_spi6_cs: qup-spi6-cs-state { 2329 pins = "gpio59"; 2330 function = "qup1_se6"; 2331 drive-strength = <6>; 2332 bias-disable; 2333 }; 2334 2335 qup_spi6_data_clk: qup-spi6-data-clk-state { 2336 /* MISO, MOSI, CLK */ 2337 pins = "gpio56", "gpio57", "gpio58"; 2338 function = "qup1_se6"; 2339 drive-strength = <6>; 2340 bias-disable; 2341 }; 2342 2343 qup_spi8_cs: qup-spi8-cs-state { 2344 pins = "gpio3"; 2345 function = "qup2_se0"; 2346 drive-strength = <6>; 2347 bias-disable; 2348 }; 2349 2350 qup_spi8_data_clk: qup-spi8-data-clk-state { 2351 /* MISO, MOSI, CLK */ 2352 pins = "gpio0", "gpio1", "gpio2"; 2353 function = "qup2_se0"; 2354 drive-strength = <6>; 2355 bias-disable; 2356 }; 2357 2358 qup_spi9_cs: qup-spi9-cs-state { 2359 pins = "gpio7"; 2360 function = "qup2_se1"; 2361 drive-strength = <6>; 2362 bias-disable; 2363 }; 2364 2365 qup_spi9_data_clk: qup-spi9-data-clk-state { 2366 /* MISO, MOSI, CLK */ 2367 pins = "gpio4", "gpio5", "gpio6"; 2368 function = "qup2_se1"; 2369 drive-strength = <6>; 2370 bias-disable; 2371 }; 2372 2373 qup_spi10_cs: qup-spi10-cs-state { 2374 pins = "gpio11"; 2375 function = "qup2_se2"; 2376 drive-strength = <6>; 2377 bias-disable; 2378 }; 2379 2380 qup_spi10_data_clk: qup-spi10-data-clk-state { 2381 /* MISO, MOSI, CLK */ 2382 pins = "gpio8", "gpio9", "gpio10"; 2383 function = "qup2_se2"; 2384 drive-strength = <6>; 2385 bias-disable; 2386 }; 2387 2388 qup_spi11_cs: qup-spi11-cs-state { 2389 pins = "gpio15"; 2390 function = "qup2_se3"; 2391 drive-strength = <6>; 2392 bias-disable; 2393 }; 2394 2395 qup_spi11_data_clk: qup-spi11-data-clk-state { 2396 /* MISO, MOSI, CLK */ 2397 pins = "gpio12", "gpio13", "gpio14"; 2398 function = "qup2_se3"; 2399 drive-strength = <6>; 2400 bias-disable; 2401 }; 2402 2403 qup_spi12_cs: qup-spi12-cs-state { 2404 pins = "gpio19"; 2405 function = "qup2_se4"; 2406 drive-strength = <6>; 2407 bias-disable; 2408 }; 2409 2410 qup_spi12_data_clk: qup-spi12-data-clk-state { 2411 /* MISO, MOSI, CLK */ 2412 pins = "gpio16", "gpio17", "gpio18"; 2413 function = "qup2_se4"; 2414 drive-strength = <6>; 2415 bias-disable; 2416 }; 2417 2418 qup_spi13_cs: qup-spi13-cs-state { 2419 pins = "gpio23"; 2420 function = "qup2_se5"; 2421 drive-strength = <6>; 2422 bias-pull-up; 2423 }; 2424 2425 qup_spi13_data_clk: qup-spi13-data-clk-state { 2426 /* MISO, MOSI, CLK */ 2427 pins = "gpio20", "gpio21", "gpio22"; 2428 function = "qup2_se5"; 2429 drive-strength = <6>; 2430 bias-disable; 2431 }; 2432 2433 qup_spi15_cs: qup-spi15-cs-state { 2434 pins = "gpio31"; 2435 function = "qup2_se7"; 2436 drive-strength = <6>; 2437 bias-disable; 2438 }; 2439 2440 qup_spi15_data_clk: qup-spi15-data-clk-state { 2441 /* MISO, MOSI, CLK */ 2442 pins = "gpio28", "gpio29", "gpio30"; 2443 function = "qup2_se7"; 2444 drive-strength = <6>; 2445 bias-disable; 2446 }; 2447 2448 qup_uart7_default: qup-uart7-default-state { 2449 /* TX, RX */ 2450 pins = "gpio62", "gpio63"; 2451 function = "qup1_se7"; 2452 drive-strength = <2>; 2453 bias-disable; 2454 }; 2455 2456 qup_uart14_default: qup-uart14-default-state { 2457 /* TX, RX */ 2458 pins = "gpio26", "gpio27"; 2459 function = "qup2_se6"; 2460 drive-strength = <2>; 2461 bias-pull-up; 2462 }; 2463 2464 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 2465 /* CTS, RTS */ 2466 pins = "gpio24", "gpio25"; 2467 function = "qup2_se6"; 2468 drive-strength = <2>; 2469 bias-pull-down; 2470 }; 2471 2472 sdc2_sleep: sdc2-sleep-state { 2473 clk-pins { 2474 pins = "sdc2_clk"; 2475 drive-strength = <2>; 2476 bias-disable; 2477 }; 2478 2479 cmd-pins { 2480 pins = "sdc2_cmd"; 2481 drive-strength = <2>; 2482 bias-pull-up; 2483 }; 2484 2485 data-pins { 2486 pins = "sdc2_data"; 2487 drive-strength = <2>; 2488 bias-pull-up; 2489 }; 2490 }; 2491 2492 sdc2_default: sdc2-default-state { 2493 clk-pins { 2494 pins = "sdc2_clk"; 2495 drive-strength = <16>; 2496 bias-disable; 2497 }; 2498 2499 cmd-pins { 2500 pins = "sdc2_cmd"; 2501 drive-strength = <10>; 2502 bias-pull-up; 2503 }; 2504 2505 data-pins { 2506 pins = "sdc2_data"; 2507 drive-strength = <10>; 2508 bias-pull-up; 2509 }; 2510 }; 2511 }; 2512 2513 tcsrcc: clock-controller@f204008 { 2514 compatible = "qcom,sm8750-tcsr", "syscon"; 2515 reg = <0x0 0x0f204008 0x0 0x3004>; 2516 2517 clocks = <&rpmhcc RPMH_CXO_CLK>; 2518 2519 #clock-cells = <1>; 2520 #reset-cells = <1>; 2521 }; 2522 2523 apps_smmu: iommu@15000000 { 2524 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2525 reg = <0x0 0x15000000 0x0 0x100000>; 2526 2527 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2533 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2534 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2535 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2538 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2539 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2540 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2541 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2542 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2543 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2544 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2545 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2546 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2547 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2548 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2549 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2550 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2554 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2555 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2556 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2557 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2558 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2559 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2560 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2561 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2562 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2563 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2564 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2565 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2566 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2567 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2568 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2569 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2570 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2571 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2572 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2573 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2574 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2575 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2576 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2577 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2578 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2579 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2580 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2581 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2582 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2583 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2584 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2585 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2586 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2587 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2588 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2589 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2590 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 2591 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 2592 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 2593 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 2594 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 2595 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 2596 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 2597 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 2611 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2612 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 2613 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2614 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2615 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 2616 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 2617 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 2618 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 2619 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 2620 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 2621 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 2622 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 2623 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 2624 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 2625 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2626 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 2627 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 2628 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 2629 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 2630 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 2631 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 2632 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 2633 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2634 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 2635 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 2636 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2637 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 2638 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 2639 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 2640 2641 #iommu-cells = <2>; 2642 #global-interrupts = <1>; 2643 2644 dma-coherent; 2645 }; 2646 2647 intc: interrupt-controller@16000000 { 2648 compatible = "arm,gic-v3"; 2649 reg = <0x0 0x16000000 0x0 0x10000>, 2650 <0x0 0x16080000 0x0 0x200000>; 2651 2652 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2653 2654 #interrupt-cells = <3>; 2655 interrupt-controller; 2656 2657 #redistributor-regions = <1>; 2658 redistributor-stride = <0x0 0x40000>; 2659 2660 #address-cells = <2>; 2661 #size-cells = <2>; 2662 ranges; 2663 2664 gic_its: msi-controller@16040000 { 2665 compatible = "arm,gic-v3-its"; 2666 reg = <0x0 0x16040000 0x0 0x20000>; 2667 2668 msi-controller; 2669 #msi-cells = <1>; 2670 }; 2671 }; 2672 2673 apps_rsc: rsc@16500000 { 2674 compatible = "qcom,rpmh-rsc"; 2675 reg = <0x0 0x16500000 0x0 0x10000>, 2676 <0x0 0x16510000 0x0 0x10000>, 2677 <0x0 0x16520000 0x0 0x10000>; 2678 reg-names = "drv-0", 2679 "drv-1", 2680 "drv-2"; 2681 2682 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2683 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2684 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2685 qcom,tcs-offset = <0xd00>; 2686 qcom,drv-id = <2>; 2687 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 2688 <WAKE_TCS 2>, <CONTROL_TCS 0>; 2689 2690 label = "apps_rsc"; 2691 2692 power-domains = <&system_pd>; 2693 2694 apps_bcm_voter: bcm-voter { 2695 compatible = "qcom,bcm-voter"; 2696 }; 2697 2698 rpmhcc: clock-controller { 2699 compatible = "qcom,sm8750-rpmh-clk"; 2700 2701 clocks = <&xo_board>; 2702 clock-names = "xo"; 2703 2704 #clock-cells = <1>; 2705 }; 2706 2707 rpmhpd: power-controller { 2708 compatible = "qcom,sm8750-rpmhpd"; 2709 2710 operating-points-v2 = <&rpmhpd_opp_table>; 2711 2712 #power-domain-cells = <1>; 2713 2714 rpmhpd_opp_table: opp-table { 2715 compatible = "operating-points-v2"; 2716 2717 rpmhpd_opp_ret: opp-16 { 2718 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2719 }; 2720 2721 rpmhpd_opp_min_svs: opp-48 { 2722 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2723 }; 2724 2725 rpmhpd_opp_low_svs_d3: opp-50 { 2726 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 2727 }; 2728 2729 rpmhpd_opp_low_svs_d2: opp-52 { 2730 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 2731 }; 2732 2733 rpmhpd_opp_low_svs_d1: opp-56 { 2734 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2735 }; 2736 2737 rpmhpd_opp_low_svs_d0: opp-60 { 2738 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 2739 }; 2740 2741 rpmhpd_opp_low_svs: opp-64 { 2742 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2743 }; 2744 2745 rpmhpd_opp_low_svs_l1: opp-80 { 2746 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2747 }; 2748 2749 rpmhpd_opp_svs: opp-128 { 2750 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2751 }; 2752 2753 rpmhpd_opp_svs_l0: opp-144 { 2754 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2755 }; 2756 2757 rpmhpd_opp_svs_l1: opp-192 { 2758 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2759 }; 2760 2761 rpmhpd_opp_svs_l2: opp-224 { 2762 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2763 }; 2764 2765 rpmhpd_opp_nom: opp-256 { 2766 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2767 }; 2768 2769 rpmhpd_opp_nom_l1: opp-320 { 2770 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2771 }; 2772 2773 rpmhpd_opp_nom_l2: opp-336 { 2774 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2775 }; 2776 2777 rpmhpd_opp_turbo: opp-384 { 2778 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2779 }; 2780 2781 rpmhpd_opp_turbo_l1: opp-416 { 2782 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2783 }; 2784 2785 rpmhpd_opp_turbo_l2: opp-432 { 2786 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 2787 }; 2788 2789 rpmhpd_opp_turbo_l3: opp-448 { 2790 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 2791 }; 2792 2793 rpmhpd_opp_turbo_l4: opp-452 { 2794 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 2795 }; 2796 2797 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 2798 opp-level = 2799 <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 2800 }; 2801 }; 2802 }; 2803 }; 2804 2805 timer@16800000 { 2806 compatible = "arm,armv7-timer-mem"; 2807 reg = <0x0 0x16800000 0x0 0x1000>; 2808 2809 #address-cells = <2>; 2810 #size-cells = <1>; 2811 ranges = <0 0 0 0 0x20000000>; 2812 2813 frame@16801000 { 2814 reg = <0x0 0x16801000 0x1000>, 2815 <0x0 0x16802000 0x1000>; 2816 2817 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2818 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 2819 2820 frame-number = <0>; 2821 }; 2822 2823 frame@16803000 { 2824 reg = <0x0 0x16803000 0x1000>; 2825 2826 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2827 2828 frame-number = <1>; 2829 2830 status = "disabled"; 2831 }; 2832 2833 frame@16805000 { 2834 reg = <0x0 0x16805000 0x1000>; 2835 2836 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2837 2838 frame-number = <2>; 2839 2840 status = "disabled"; 2841 }; 2842 2843 frame@16807000 { 2844 reg = <0x0 0x16807000 0x1000>; 2845 2846 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2847 2848 frame-number = <3>; 2849 2850 status = "disabled"; 2851 }; 2852 2853 frame@16809000 { 2854 reg = <0x0 0x16809000 0x1000>; 2855 2856 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2857 2858 frame-number = <4>; 2859 2860 status = "disabled"; 2861 }; 2862 2863 frame@1680b000 { 2864 reg = <0x0 0x1680b000 0x1000>; 2865 2866 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2867 2868 frame-number = <5>; 2869 2870 status = "disabled"; 2871 }; 2872 2873 frame@1680d000 { 2874 reg = <0x0 0x1680d000 0x1000>; 2875 2876 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2877 2878 frame-number = <6>; 2879 2880 status = "disabled"; 2881 }; 2882 }; 2883 2884 gem_noc: interconnect@24100000 { 2885 compatible = "qcom,sm8750-gem-noc"; 2886 reg = <0x0 0x24100000 0x0 0x14b080>; 2887 qcom,bcm-voters = <&apps_bcm_voter>; 2888 #interconnect-cells = <2>; 2889 }; 2890 2891 nsp_noc: interconnect@320c0000 { 2892 compatible = "qcom,sm8750-nsp-noc"; 2893 reg = <0x0 0x320c0000 0x0 0x13080>; 2894 qcom,bcm-voters = <&apps_bcm_voter>; 2895 #interconnect-cells = <2>; 2896 }; 2897 }; 2898 2899 timer { 2900 compatible = "arm,armv8-timer"; 2901 2902 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2903 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2904 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2905 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 2906 }; 2907}; 2908