1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-sm8450.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/clock/qcom,sm8450-camcc.h> 10#include <dt-bindings/clock/qcom,sm8450-dispcc.h> 11#include <dt-bindings/clock/qcom,sm8450-gpucc.h> 12#include <dt-bindings/clock/qcom,sm8450-videocc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/interconnect/qcom,icc.h> 21#include <dt-bindings/interconnect/qcom,sm8450.h> 22#include <dt-bindings/reset/qcom,sm8450-gpucc.h> 23#include <dt-bindings/soc/qcom,gpr.h> 24#include <dt-bindings/soc/qcom,rpmh-rsc.h> 25#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 26#include <dt-bindings/thermal/thermal.h> 27 28/ { 29 interrupt-parent = <&intc>; 30 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 chosen { }; 35 36 clocks { 37 xo_board: xo-board { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <76800000>; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 #clock-cells = <0>; 46 clock-frequency = <32764>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "qcom,kryo780"; 57 reg = <0x0 0x0>; 58 enable-method = "psci"; 59 next-level-cache = <&l2_0>; 60 power-domains = <&cpu_pd0>; 61 power-domain-names = "psci"; 62 qcom,freq-domain = <&cpufreq_hw 0>; 63 #cooling-cells = <2>; 64 clocks = <&cpufreq_hw 0>; 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 l3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 cpu1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "qcom,kryo780"; 81 reg = <0x0 0x100>; 82 enable-method = "psci"; 83 next-level-cache = <&l2_100>; 84 power-domains = <&cpu_pd1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 #cooling-cells = <2>; 88 clocks = <&cpufreq_hw 0>; 89 l2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&l3_0>; 94 }; 95 }; 96 97 cpu2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "qcom,kryo780"; 100 reg = <0x0 0x200>; 101 enable-method = "psci"; 102 next-level-cache = <&l2_200>; 103 power-domains = <&cpu_pd2>; 104 power-domain-names = "psci"; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 #cooling-cells = <2>; 107 clocks = <&cpufreq_hw 0>; 108 l2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "qcom,kryo780"; 119 reg = <0x0 0x300>; 120 enable-method = "psci"; 121 next-level-cache = <&l2_300>; 122 power-domains = <&cpu_pd3>; 123 power-domain-names = "psci"; 124 qcom,freq-domain = <&cpufreq_hw 0>; 125 #cooling-cells = <2>; 126 clocks = <&cpufreq_hw 0>; 127 l2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&l3_0>; 132 }; 133 }; 134 135 cpu4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "qcom,kryo780"; 138 reg = <0x0 0x400>; 139 enable-method = "psci"; 140 next-level-cache = <&l2_400>; 141 power-domains = <&cpu_pd4>; 142 power-domain-names = "psci"; 143 qcom,freq-domain = <&cpufreq_hw 1>; 144 #cooling-cells = <2>; 145 clocks = <&cpufreq_hw 1>; 146 l2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&l3_0>; 151 }; 152 }; 153 154 cpu5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "qcom,kryo780"; 157 reg = <0x0 0x500>; 158 enable-method = "psci"; 159 next-level-cache = <&l2_500>; 160 power-domains = <&cpu_pd5>; 161 power-domain-names = "psci"; 162 qcom,freq-domain = <&cpufreq_hw 1>; 163 #cooling-cells = <2>; 164 clocks = <&cpufreq_hw 1>; 165 l2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&l3_0>; 170 }; 171 }; 172 173 cpu6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "qcom,kryo780"; 176 reg = <0x0 0x600>; 177 enable-method = "psci"; 178 next-level-cache = <&l2_600>; 179 power-domains = <&cpu_pd6>; 180 power-domain-names = "psci"; 181 qcom,freq-domain = <&cpufreq_hw 1>; 182 #cooling-cells = <2>; 183 clocks = <&cpufreq_hw 1>; 184 l2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&l3_0>; 189 }; 190 }; 191 192 cpu7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "qcom,kryo780"; 195 reg = <0x0 0x700>; 196 enable-method = "psci"; 197 next-level-cache = <&l2_700>; 198 power-domains = <&cpu_pd7>; 199 power-domain-names = "psci"; 200 qcom,freq-domain = <&cpufreq_hw 2>; 201 #cooling-cells = <2>; 202 clocks = <&cpufreq_hw 2>; 203 l2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&l3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&cpu0>; 215 }; 216 217 core1 { 218 cpu = <&cpu1>; 219 }; 220 221 core2 { 222 cpu = <&cpu2>; 223 }; 224 225 core3 { 226 cpu = <&cpu3>; 227 }; 228 229 core4 { 230 cpu = <&cpu4>; 231 }; 232 233 core5 { 234 cpu = <&cpu5>; 235 }; 236 237 core6 { 238 cpu = <&cpu6>; 239 }; 240 241 core7 { 242 cpu = <&cpu7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 little_cpu_sleep_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <800>; 255 exit-latency-us = <750>; 256 min-residency-us = <4090>; 257 local-timer-stop; 258 }; 259 260 big_cpu_sleep_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <600>; 265 exit-latency-us = <1550>; 266 min-residency-us = <4791>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 cluster_sleep_0: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <1050>; 276 exit-latency-us = <2500>; 277 min-residency-us = <5309>; 278 }; 279 280 cluster_sleep_1: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <2700>; 284 exit-latency-us = <3500>; 285 min-residency-us = <13959>; 286 }; 287 }; 288 }; 289 290 ete-0 { 291 compatible = "arm,embedded-trace-extension"; 292 cpu = <&cpu0>; 293 294 out-ports { 295 port { 296 ete0_out_funnel_ete: endpoint { 297 remote-endpoint = <&funnel_ete_in_ete0>; 298 }; 299 }; 300 }; 301 }; 302 303 ete-1 { 304 compatible = "arm,embedded-trace-extension"; 305 cpu = <&cpu1>; 306 307 out-ports { 308 port { 309 ete1_out_funnel_ete: endpoint { 310 remote-endpoint = <&funnel_ete_in_ete1>; 311 }; 312 }; 313 }; 314 }; 315 316 ete-2 { 317 compatible = "arm,embedded-trace-extension"; 318 cpu = <&cpu2>; 319 320 out-ports { 321 port { 322 ete2_out_funnel_ete: endpoint { 323 remote-endpoint = <&funnel_ete_in_ete2>; 324 }; 325 }; 326 }; 327 }; 328 329 ete-3 { 330 compatible = "arm,embedded-trace-extension"; 331 cpu = <&cpu3>; 332 333 out-ports { 334 port { 335 ete3_out_funnel_ete: endpoint { 336 remote-endpoint = <&funnel_ete_in_ete3>; 337 }; 338 }; 339 }; 340 }; 341 342 ete-4 { 343 compatible = "arm,embedded-trace-extension"; 344 cpu = <&cpu4>; 345 346 out-ports { 347 port { 348 ete4_out_funnel_ete: endpoint { 349 remote-endpoint = <&funnel_ete_in_ete4>; 350 }; 351 }; 352 }; 353 }; 354 355 ete-5 { 356 compatible = "arm,embedded-trace-extension"; 357 cpu = <&cpu5>; 358 359 out-ports { 360 port { 361 ete5_out_funnel_ete: endpoint { 362 remote-endpoint = <&funnel_ete_in_ete5>; 363 }; 364 }; 365 }; 366 }; 367 368 ete-6 { 369 compatible = "arm,embedded-trace-extension"; 370 cpu = <&cpu6>; 371 372 out-ports { 373 port { 374 ete6_out_funnel_ete: endpoint { 375 remote-endpoint = <&funnel_ete_in_ete6>; 376 }; 377 }; 378 }; 379 }; 380 381 ete-7 { 382 compatible = "arm,embedded-trace-extension"; 383 cpu = <&cpu7>; 384 385 out-ports { 386 port { 387 ete7_out_funnel_ete: endpoint { 388 remote-endpoint = <&funnel_ete_in_ete7>; 389 }; 390 }; 391 }; 392 }; 393 394 funnel-ete { 395 compatible = "arm,coresight-static-funnel"; 396 397 out-ports { 398 port { 399 funnel_ete_out_funnel_apss: endpoint { 400 remote-endpoint = 401 <&funnel_apss_in_funnel_ete>; 402 }; 403 }; 404 }; 405 406 in-ports { 407 #address-cells = <1>; 408 #size-cells = <0>; 409 410 port@0 { 411 reg = <0>; 412 funnel_ete_in_ete0: endpoint { 413 remote-endpoint = 414 <&ete0_out_funnel_ete>; 415 }; 416 }; 417 418 port@1 { 419 reg = <1>; 420 funnel_ete_in_ete1: endpoint { 421 remote-endpoint = 422 <&ete1_out_funnel_ete>; 423 }; 424 }; 425 426 port@2 { 427 reg = <2>; 428 funnel_ete_in_ete2: endpoint { 429 remote-endpoint = 430 <&ete2_out_funnel_ete>; 431 }; 432 }; 433 434 port@3 { 435 reg = <3>; 436 funnel_ete_in_ete3: endpoint { 437 remote-endpoint = 438 <&ete3_out_funnel_ete>; 439 }; 440 }; 441 442 port@4 { 443 reg = <4>; 444 funnel_ete_in_ete4: endpoint { 445 remote-endpoint = 446 <&ete4_out_funnel_ete>; 447 }; 448 }; 449 450 port@5 { 451 reg = <5>; 452 funnel_ete_in_ete5: endpoint { 453 remote-endpoint = 454 <&ete5_out_funnel_ete>; 455 }; 456 }; 457 458 port@6 { 459 reg = <6>; 460 funnel_ete_in_ete6: endpoint { 461 remote-endpoint = 462 <&ete6_out_funnel_ete>; 463 }; 464 }; 465 466 port@7 { 467 reg = <7>; 468 funnel_ete_in_ete7: endpoint { 469 remote-endpoint = 470 <&ete7_out_funnel_ete>; 471 }; 472 }; 473 }; 474 }; 475 476 firmware { 477 scm: scm { 478 compatible = "qcom,scm-sm8450", "qcom,scm"; 479 qcom,dload-mode = <&tcsr 0x13000>; 480 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 481 #reset-cells = <1>; 482 }; 483 }; 484 485 clk_virt: interconnect-0 { 486 compatible = "qcom,sm8450-clk-virt"; 487 #interconnect-cells = <2>; 488 qcom,bcm-voters = <&apps_bcm_voter>; 489 }; 490 491 mc_virt: interconnect-1 { 492 compatible = "qcom,sm8450-mc-virt"; 493 #interconnect-cells = <2>; 494 qcom,bcm-voters = <&apps_bcm_voter>; 495 }; 496 497 memory@a0000000 { 498 device_type = "memory"; 499 /* We expect the bootloader to fill in the size */ 500 reg = <0x0 0xa0000000 0x0 0x0>; 501 }; 502 503 pmu { 504 compatible = "arm,armv8-pmuv3"; 505 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 506 }; 507 508 psci { 509 compatible = "arm,psci-1.0"; 510 method = "smc"; 511 512 cpu_pd0: power-domain-cpu0 { 513 #power-domain-cells = <0>; 514 power-domains = <&cluster_pd>; 515 domain-idle-states = <&little_cpu_sleep_0>; 516 }; 517 518 cpu_pd1: power-domain-cpu1 { 519 #power-domain-cells = <0>; 520 power-domains = <&cluster_pd>; 521 domain-idle-states = <&little_cpu_sleep_0>; 522 }; 523 524 cpu_pd2: power-domain-cpu2 { 525 #power-domain-cells = <0>; 526 power-domains = <&cluster_pd>; 527 domain-idle-states = <&little_cpu_sleep_0>; 528 }; 529 530 cpu_pd3: power-domain-cpu3 { 531 #power-domain-cells = <0>; 532 power-domains = <&cluster_pd>; 533 domain-idle-states = <&little_cpu_sleep_0>; 534 }; 535 536 cpu_pd4: power-domain-cpu4 { 537 #power-domain-cells = <0>; 538 power-domains = <&cluster_pd>; 539 domain-idle-states = <&big_cpu_sleep_0>; 540 }; 541 542 cpu_pd5: power-domain-cpu5 { 543 #power-domain-cells = <0>; 544 power-domains = <&cluster_pd>; 545 domain-idle-states = <&big_cpu_sleep_0>; 546 }; 547 548 cpu_pd6: power-domain-cpu6 { 549 #power-domain-cells = <0>; 550 power-domains = <&cluster_pd>; 551 domain-idle-states = <&big_cpu_sleep_0>; 552 }; 553 554 cpu_pd7: power-domain-cpu7 { 555 #power-domain-cells = <0>; 556 power-domains = <&cluster_pd>; 557 domain-idle-states = <&big_cpu_sleep_0>; 558 }; 559 560 cluster_pd: power-domain-cpu-cluster0 { 561 #power-domain-cells = <0>; 562 domain-idle-states = <&cluster_sleep_0>, <&cluster_sleep_1>; 563 }; 564 }; 565 566 qup_opp_table_100mhz: opp-table-qup { 567 compatible = "operating-points-v2"; 568 569 opp-50000000 { 570 opp-hz = /bits/ 64 <50000000>; 571 required-opps = <&rpmhpd_opp_min_svs>; 572 }; 573 574 opp-75000000 { 575 opp-hz = /bits/ 64 <75000000>; 576 required-opps = <&rpmhpd_opp_low_svs>; 577 }; 578 579 opp-100000000 { 580 opp-hz = /bits/ 64 <100000000>; 581 required-opps = <&rpmhpd_opp_svs>; 582 }; 583 }; 584 585 reserved_memory: reserved-memory { 586 #address-cells = <2>; 587 #size-cells = <2>; 588 ranges; 589 590 hyp_mem: memory@80000000 { 591 reg = <0x0 0x80000000 0x0 0x600000>; 592 no-map; 593 }; 594 595 xbl_dt_log_mem: memory@80600000 { 596 reg = <0x0 0x80600000 0x0 0x40000>; 597 no-map; 598 }; 599 600 xbl_ramdump_mem: memory@80640000 { 601 reg = <0x0 0x80640000 0x0 0x180000>; 602 no-map; 603 }; 604 605 xbl_sc_mem: memory@807c0000 { 606 reg = <0x0 0x807c0000 0x0 0x40000>; 607 no-map; 608 }; 609 610 aop_image_mem: memory@80800000 { 611 reg = <0x0 0x80800000 0x0 0x60000>; 612 no-map; 613 }; 614 615 aop_cmd_db_mem: memory@80860000 { 616 compatible = "qcom,cmd-db"; 617 reg = <0x0 0x80860000 0x0 0x20000>; 618 no-map; 619 }; 620 621 aop_config_mem: memory@80880000 { 622 reg = <0x0 0x80880000 0x0 0x20000>; 623 no-map; 624 }; 625 626 tme_crash_dump_mem: memory@808a0000 { 627 reg = <0x0 0x808a0000 0x0 0x40000>; 628 no-map; 629 }; 630 631 tme_log_mem: memory@808e0000 { 632 reg = <0x0 0x808e0000 0x0 0x4000>; 633 no-map; 634 }; 635 636 uefi_log_mem: memory@808e4000 { 637 reg = <0x0 0x808e4000 0x0 0x10000>; 638 no-map; 639 }; 640 641 /* secdata region can be reused by apps */ 642 smem: memory@80900000 { 643 compatible = "qcom,smem"; 644 reg = <0x0 0x80900000 0x0 0x200000>; 645 hwlocks = <&tcsr_mutex 3>; 646 no-map; 647 }; 648 649 cpucp_fw_mem: memory@80b00000 { 650 reg = <0x0 0x80b00000 0x0 0x100000>; 651 no-map; 652 }; 653 654 cdsp_secure_heap: memory@80c00000 { 655 reg = <0x0 0x80c00000 0x0 0x4600000>; 656 no-map; 657 }; 658 659 video_mem: memory@85700000 { 660 reg = <0x0 0x85700000 0x0 0x700000>; 661 no-map; 662 }; 663 664 adsp_mem: memory@85e00000 { 665 reg = <0x0 0x85e00000 0x0 0x2100000>; 666 no-map; 667 }; 668 669 slpi_mem: memory@88000000 { 670 reg = <0x0 0x88000000 0x0 0x1900000>; 671 no-map; 672 }; 673 674 cdsp_mem: memory@89900000 { 675 reg = <0x0 0x89900000 0x0 0x2000000>; 676 no-map; 677 }; 678 679 ipa_fw_mem: memory@8b900000 { 680 reg = <0x0 0x8b900000 0x0 0x10000>; 681 no-map; 682 }; 683 684 ipa_gsi_mem: memory@8b910000 { 685 reg = <0x0 0x8b910000 0x0 0xa000>; 686 no-map; 687 }; 688 689 gpu_micro_code_mem: memory@8b91a000 { 690 reg = <0x0 0x8b91a000 0x0 0x2000>; 691 no-map; 692 }; 693 694 spss_region_mem: memory@8ba00000 { 695 reg = <0x0 0x8ba00000 0x0 0x180000>; 696 no-map; 697 }; 698 699 /* First part of the "SPU secure shared memory" region */ 700 spu_tz_shared_mem: memory@8bb80000 { 701 reg = <0x0 0x8bb80000 0x0 0x60000>; 702 no-map; 703 }; 704 705 /* Second part of the "SPU secure shared memory" region */ 706 spu_modem_shared_mem: memory@8bbe0000 { 707 reg = <0x0 0x8bbe0000 0x0 0x20000>; 708 no-map; 709 }; 710 711 mpss_mem: memory@8bc00000 { 712 reg = <0x0 0x8bc00000 0x0 0x13200000>; 713 no-map; 714 }; 715 716 cvp_mem: memory@9ee00000 { 717 reg = <0x0 0x9ee00000 0x0 0x700000>; 718 no-map; 719 }; 720 721 camera_mem: memory@9f500000 { 722 reg = <0x0 0x9f500000 0x0 0x800000>; 723 no-map; 724 }; 725 726 rmtfs_mem: memory@9fd00000 { 727 compatible = "qcom,rmtfs-mem"; 728 reg = <0x0 0x9fd00000 0x0 0x280000>; 729 no-map; 730 731 qcom,client-id = <1>; 732 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 733 }; 734 735 xbl_sc_mem2: memory@a6e00000 { 736 reg = <0x0 0xa6e00000 0x0 0x40000>; 737 no-map; 738 }; 739 740 global_sync_mem: memory@a6f00000 { 741 reg = <0x0 0xa6f00000 0x0 0x100000>; 742 no-map; 743 }; 744 745 /* uefi region can be reused by APPS */ 746 747 /* Linux kernel image is loaded at 0xa0000000 */ 748 749 oem_vm_mem: memory@bb000000 { 750 reg = <0x0 0xbb000000 0x0 0x5000000>; 751 no-map; 752 }; 753 754 mte_mem: memory@c0000000 { 755 reg = <0x0 0xc0000000 0x0 0x20000000>; 756 no-map; 757 }; 758 759 qheebsp_reserved_mem: memory@e0000000 { 760 reg = <0x0 0xe0000000 0x0 0x600000>; 761 no-map; 762 }; 763 764 cpusys_vm_mem: memory@e0600000 { 765 reg = <0x0 0xe0600000 0x0 0x400000>; 766 no-map; 767 }; 768 769 hyp_reserved_mem: memory@e0a00000 { 770 reg = <0x0 0xe0a00000 0x0 0x100000>; 771 no-map; 772 }; 773 774 trust_ui_vm_mem: memory@e0b00000 { 775 reg = <0x0 0xe0b00000 0x0 0x4af3000>; 776 no-map; 777 }; 778 779 trust_ui_vm_qrtr: memory@e55f3000 { 780 reg = <0x0 0xe55f3000 0x0 0x9000>; 781 no-map; 782 }; 783 784 trust_ui_vm_vblk0_ring: memory@e55fc000 { 785 reg = <0x0 0xe55fc000 0x0 0x4000>; 786 no-map; 787 }; 788 789 trust_ui_vm_swiotlb: memory@e5600000 { 790 reg = <0x0 0xe5600000 0x0 0x100000>; 791 no-map; 792 }; 793 794 tz_stat_mem: memory@e8800000 { 795 reg = <0x0 0xe8800000 0x0 0x100000>; 796 no-map; 797 }; 798 799 tags_mem: memory@e8900000 { 800 reg = <0x0 0xe8900000 0x0 0x1200000>; 801 no-map; 802 }; 803 804 qtee_mem: memory@e9b00000 { 805 reg = <0x0 0xe9b00000 0x0 0x500000>; 806 no-map; 807 }; 808 809 trusted_apps_mem: memory@ea000000 { 810 reg = <0x0 0xea000000 0x0 0x3900000>; 811 no-map; 812 }; 813 814 trusted_apps_ext_mem: memory@ed900000 { 815 reg = <0x0 0xed900000 0x0 0x3b00000>; 816 no-map; 817 }; 818 }; 819 820 smp2p-adsp { 821 compatible = "qcom,smp2p"; 822 qcom,smem = <443>, <429>; 823 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 824 IPCC_MPROC_SIGNAL_SMP2P 825 IRQ_TYPE_EDGE_RISING>; 826 mboxes = <&ipcc IPCC_CLIENT_LPASS 827 IPCC_MPROC_SIGNAL_SMP2P>; 828 829 qcom,local-pid = <0>; 830 qcom,remote-pid = <2>; 831 832 smp2p_adsp_out: master-kernel { 833 qcom,entry-name = "master-kernel"; 834 #qcom,smem-state-cells = <1>; 835 }; 836 837 smp2p_adsp_in: slave-kernel { 838 qcom,entry-name = "slave-kernel"; 839 interrupt-controller; 840 #interrupt-cells = <2>; 841 }; 842 }; 843 844 smp2p-cdsp { 845 compatible = "qcom,smp2p"; 846 qcom,smem = <94>, <432>; 847 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 848 IPCC_MPROC_SIGNAL_SMP2P 849 IRQ_TYPE_EDGE_RISING>; 850 mboxes = <&ipcc IPCC_CLIENT_CDSP 851 IPCC_MPROC_SIGNAL_SMP2P>; 852 853 qcom,local-pid = <0>; 854 qcom,remote-pid = <5>; 855 856 smp2p_cdsp_out: master-kernel { 857 qcom,entry-name = "master-kernel"; 858 #qcom,smem-state-cells = <1>; 859 }; 860 861 smp2p_cdsp_in: slave-kernel { 862 qcom,entry-name = "slave-kernel"; 863 interrupt-controller; 864 #interrupt-cells = <2>; 865 }; 866 }; 867 868 smp2p-modem { 869 compatible = "qcom,smp2p"; 870 qcom,smem = <435>, <428>; 871 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 872 IPCC_MPROC_SIGNAL_SMP2P 873 IRQ_TYPE_EDGE_RISING>; 874 mboxes = <&ipcc IPCC_CLIENT_MPSS 875 IPCC_MPROC_SIGNAL_SMP2P>; 876 877 qcom,local-pid = <0>; 878 qcom,remote-pid = <1>; 879 880 smp2p_modem_out: master-kernel { 881 qcom,entry-name = "master-kernel"; 882 #qcom,smem-state-cells = <1>; 883 }; 884 885 smp2p_modem_in: slave-kernel { 886 qcom,entry-name = "slave-kernel"; 887 interrupt-controller; 888 #interrupt-cells = <2>; 889 }; 890 891 ipa_smp2p_out: ipa-ap-to-modem { 892 qcom,entry-name = "ipa"; 893 #qcom,smem-state-cells = <1>; 894 }; 895 896 ipa_smp2p_in: ipa-modem-to-ap { 897 qcom,entry-name = "ipa"; 898 interrupt-controller; 899 #interrupt-cells = <2>; 900 }; 901 }; 902 903 smp2p-slpi { 904 compatible = "qcom,smp2p"; 905 qcom,smem = <481>, <430>; 906 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 907 IPCC_MPROC_SIGNAL_SMP2P 908 IRQ_TYPE_EDGE_RISING>; 909 mboxes = <&ipcc IPCC_CLIENT_SLPI 910 IPCC_MPROC_SIGNAL_SMP2P>; 911 912 qcom,local-pid = <0>; 913 qcom,remote-pid = <3>; 914 915 smp2p_slpi_out: master-kernel { 916 qcom,entry-name = "master-kernel"; 917 #qcom,smem-state-cells = <1>; 918 }; 919 920 smp2p_slpi_in: slave-kernel { 921 qcom,entry-name = "slave-kernel"; 922 interrupt-controller; 923 #interrupt-cells = <2>; 924 }; 925 }; 926 927 soc: soc@0 { 928 #address-cells = <2>; 929 #size-cells = <2>; 930 ranges = <0 0 0 0 0x10 0>; 931 dma-ranges = <0 0 0 0 0x10 0>; 932 compatible = "simple-bus"; 933 934 gcc: clock-controller@100000 { 935 compatible = "qcom,gcc-sm8450"; 936 reg = <0x0 0x00100000 0x0 0x1f4200>; 937 #clock-cells = <1>; 938 #reset-cells = <1>; 939 #power-domain-cells = <1>; 940 clocks = <&rpmhcc RPMH_CXO_CLK>, 941 <&sleep_clk>, 942 <&pcie0_phy>, 943 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 944 <&pcie1_phy QMP_PCIE_PHY_AUX_CLK>, 945 <&ufs_mem_phy 0>, 946 <&ufs_mem_phy 1>, 947 <&ufs_mem_phy 2>, 948 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 949 clock-names = "bi_tcxo", 950 "sleep_clk", 951 "pcie_0_pipe_clk", 952 "pcie_1_pipe_clk", 953 "pcie_1_phy_aux_clk", 954 "ufs_phy_rx_symbol_0_clk", 955 "ufs_phy_rx_symbol_1_clk", 956 "ufs_phy_tx_symbol_0_clk", 957 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 958 }; 959 960 gpi_dma2: dma-controller@800000 { 961 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 962 #dma-cells = <3>; 963 reg = <0 0x00800000 0 0x60000>; 964 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 965 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 966 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 967 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 968 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 969 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 971 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 973 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 974 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 975 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 976 dma-channels = <12>; 977 dma-channel-mask = <0x7e>; 978 iommus = <&apps_smmu 0x496 0x0>; 979 status = "disabled"; 980 }; 981 982 qupv3_id_2: geniqup@8c0000 { 983 compatible = "qcom,geni-se-qup"; 984 reg = <0x0 0x008c0000 0x0 0x2000>; 985 clock-names = "m-ahb", "s-ahb"; 986 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 987 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 988 iommus = <&apps_smmu 0x483 0x0>; 989 #address-cells = <2>; 990 #size-cells = <2>; 991 ranges; 992 status = "disabled"; 993 994 i2c15: i2c@880000 { 995 compatible = "qcom,geni-i2c"; 996 reg = <0x0 0x00880000 0x0 0x4000>; 997 clock-names = "se"; 998 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 999 pinctrl-names = "default"; 1000 pinctrl-0 = <&qup_i2c15_data_clk>; 1001 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1002 #address-cells = <1>; 1003 #size-cells = <0>; 1004 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1005 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1006 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1007 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1008 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1009 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 status = "disabled"; 1012 }; 1013 1014 spi15: spi@880000 { 1015 compatible = "qcom,geni-spi"; 1016 reg = <0x0 0x00880000 0x0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1019 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1022 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1023 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1024 interconnect-names = "qup-core", "qup-config"; 1025 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1026 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1027 dma-names = "tx", "rx"; 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 status = "disabled"; 1031 }; 1032 1033 i2c16: i2c@884000 { 1034 compatible = "qcom,geni-i2c"; 1035 reg = <0x0 0x00884000 0x0 0x4000>; 1036 clock-names = "se"; 1037 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&qup_i2c16_data_clk>; 1040 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1044 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1045 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1046 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1047 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1048 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1049 dma-names = "tx", "rx"; 1050 status = "disabled"; 1051 }; 1052 1053 spi16: spi@884000 { 1054 compatible = "qcom,geni-spi"; 1055 reg = <0x0 0x00884000 0x0 0x4000>; 1056 clock-names = "se"; 1057 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1058 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1059 pinctrl-names = "default"; 1060 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 1061 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1062 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1063 interconnect-names = "qup-core", "qup-config"; 1064 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1065 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1066 dma-names = "tx", "rx"; 1067 #address-cells = <1>; 1068 #size-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 i2c17: i2c@888000 { 1073 compatible = "qcom,geni-i2c"; 1074 reg = <0x0 0x00888000 0x0 0x4000>; 1075 clock-names = "se"; 1076 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1077 pinctrl-names = "default"; 1078 pinctrl-0 = <&qup_i2c17_data_clk>; 1079 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1083 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1084 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1085 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1086 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1087 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1088 dma-names = "tx", "rx"; 1089 status = "disabled"; 1090 }; 1091 1092 spi17: spi@888000 { 1093 compatible = "qcom,geni-spi"; 1094 reg = <0x0 0x00888000 0x0 0x4000>; 1095 clock-names = "se"; 1096 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1097 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1098 pinctrl-names = "default"; 1099 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1100 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1101 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1102 interconnect-names = "qup-core", "qup-config"; 1103 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1104 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1105 dma-names = "tx", "rx"; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c18: i2c@88c000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0x0 0x0088c000 0x0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c18_data_clk>; 1118 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1122 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1123 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1124 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1125 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1126 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1127 dma-names = "tx", "rx"; 1128 status = "disabled"; 1129 }; 1130 1131 spi18: spi@88c000 { 1132 compatible = "qcom,geni-spi"; 1133 reg = <0 0x0088c000 0 0x4000>; 1134 clock-names = "se"; 1135 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1136 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1137 pinctrl-names = "default"; 1138 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>; 1139 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1140 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1141 interconnect-names = "qup-core", "qup-config"; 1142 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1143 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1144 dma-names = "tx", "rx"; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 status = "disabled"; 1148 }; 1149 1150 i2c19: i2c@890000 { 1151 compatible = "qcom,geni-i2c"; 1152 reg = <0x0 0x00890000 0x0 0x4000>; 1153 clock-names = "se"; 1154 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_i2c19_data_clk>; 1157 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1161 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1162 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1163 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1164 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1165 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1166 dma-names = "tx", "rx"; 1167 status = "disabled"; 1168 }; 1169 1170 spi19: spi@890000 { 1171 compatible = "qcom,geni-spi"; 1172 reg = <0 0x00890000 0 0x4000>; 1173 clock-names = "se"; 1174 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1175 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1176 pinctrl-names = "default"; 1177 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 1178 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1179 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1180 interconnect-names = "qup-core", "qup-config"; 1181 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1182 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1183 dma-names = "tx", "rx"; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 i2c20: i2c@894000 { 1190 compatible = "qcom,geni-i2c"; 1191 reg = <0x0 0x00894000 0x0 0x4000>; 1192 clock-names = "se"; 1193 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1194 pinctrl-names = "default"; 1195 pinctrl-0 = <&qup_i2c20_data_clk>; 1196 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1197 #address-cells = <1>; 1198 #size-cells = <0>; 1199 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1200 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1201 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1202 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1203 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1204 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1205 dma-names = "tx", "rx"; 1206 status = "disabled"; 1207 }; 1208 1209 uart20: serial@894000 { 1210 compatible = "qcom,geni-uart"; 1211 reg = <0 0x00894000 0 0x4000>; 1212 clock-names = "se"; 1213 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1214 pinctrl-names = "default"; 1215 pinctrl-0 = <&qup_uart20_default>; 1216 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1217 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1218 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1219 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1220 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1221 interconnect-names = "qup-core", 1222 "qup-config"; 1223 status = "disabled"; 1224 }; 1225 1226 spi20: spi@894000 { 1227 compatible = "qcom,geni-spi"; 1228 reg = <0 0x00894000 0 0x4000>; 1229 clock-names = "se"; 1230 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1231 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1232 pinctrl-names = "default"; 1233 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 1234 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1235 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1236 interconnect-names = "qup-core", "qup-config"; 1237 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1238 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1239 dma-names = "tx", "rx"; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 i2c21: i2c@898000 { 1246 compatible = "qcom,geni-i2c"; 1247 reg = <0x0 0x00898000 0x0 0x4000>; 1248 clock-names = "se"; 1249 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1250 pinctrl-names = "default"; 1251 pinctrl-0 = <&qup_i2c21_data_clk>; 1252 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1256 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1257 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1258 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1259 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>, 1260 <&gpi_dma2 1 6 QCOM_GPI_I2C>; 1261 dma-names = "tx", "rx"; 1262 status = "disabled"; 1263 }; 1264 1265 spi21: spi@898000 { 1266 compatible = "qcom,geni-spi"; 1267 reg = <0 0x00898000 0 0x4000>; 1268 clock-names = "se"; 1269 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1270 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1271 pinctrl-names = "default"; 1272 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 1273 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1274 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>; 1275 interconnect-names = "qup-core", "qup-config"; 1276 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>, 1277 <&gpi_dma2 1 6 QCOM_GPI_SPI>; 1278 dma-names = "tx", "rx"; 1279 #address-cells = <1>; 1280 #size-cells = <0>; 1281 status = "disabled"; 1282 }; 1283 }; 1284 1285 gpi_dma0: dma-controller@900000 { 1286 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1287 #dma-cells = <3>; 1288 reg = <0 0x00900000 0 0x60000>; 1289 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1290 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1291 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1292 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1293 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1294 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1295 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1296 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1297 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1299 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1300 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1301 dma-channels = <12>; 1302 dma-channel-mask = <0x7e>; 1303 iommus = <&apps_smmu 0x5b6 0x0>; 1304 status = "disabled"; 1305 }; 1306 1307 qupv3_id_0: geniqup@9c0000 { 1308 compatible = "qcom,geni-se-qup"; 1309 reg = <0x0 0x009c0000 0x0 0x2000>; 1310 clock-names = "m-ahb", "s-ahb"; 1311 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1312 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1313 iommus = <&apps_smmu 0x5a3 0x0>; 1314 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>; 1315 interconnect-names = "qup-core"; 1316 #address-cells = <2>; 1317 #size-cells = <2>; 1318 ranges; 1319 status = "disabled"; 1320 1321 i2c0: i2c@980000 { 1322 compatible = "qcom,geni-i2c"; 1323 reg = <0x0 0x00980000 0x0 0x4000>; 1324 clock-names = "se"; 1325 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1326 pinctrl-names = "default"; 1327 pinctrl-0 = <&qup_i2c0_data_clk>; 1328 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1332 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1333 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1334 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1335 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1336 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1337 dma-names = "tx", "rx"; 1338 status = "disabled"; 1339 }; 1340 1341 spi0: spi@980000 { 1342 compatible = "qcom,geni-spi"; 1343 reg = <0x0 0x00980000 0x0 0x4000>; 1344 clock-names = "se"; 1345 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1346 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1347 pinctrl-names = "default"; 1348 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1349 power-domains = <&rpmhpd RPMHPD_CX>; 1350 operating-points-v2 = <&qup_opp_table_100mhz>; 1351 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1352 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1353 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1354 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1355 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1356 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1357 dma-names = "tx", "rx"; 1358 #address-cells = <1>; 1359 #size-cells = <0>; 1360 status = "disabled"; 1361 }; 1362 1363 i2c1: i2c@984000 { 1364 compatible = "qcom,geni-i2c"; 1365 reg = <0x0 0x00984000 0x0 0x4000>; 1366 clock-names = "se"; 1367 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1368 pinctrl-names = "default"; 1369 pinctrl-0 = <&qup_i2c1_data_clk>; 1370 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1374 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1375 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1376 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1377 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1378 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1379 dma-names = "tx", "rx"; 1380 status = "disabled"; 1381 }; 1382 1383 spi1: spi@984000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0x0 0x00984000 0x0 0x4000>; 1386 clock-names = "se"; 1387 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1388 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1389 pinctrl-names = "default"; 1390 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1391 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1392 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1393 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1394 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1395 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1396 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1397 dma-names = "tx", "rx"; 1398 #address-cells = <1>; 1399 #size-cells = <0>; 1400 status = "disabled"; 1401 }; 1402 1403 i2c2: i2c@988000 { 1404 compatible = "qcom,geni-i2c"; 1405 reg = <0x0 0x00988000 0x0 0x4000>; 1406 clock-names = "se"; 1407 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1408 pinctrl-names = "default"; 1409 pinctrl-0 = <&qup_i2c2_data_clk>; 1410 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1411 #address-cells = <1>; 1412 #size-cells = <0>; 1413 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1414 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1415 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1416 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1417 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1418 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1419 dma-names = "tx", "rx"; 1420 status = "disabled"; 1421 }; 1422 1423 spi2: spi@988000 { 1424 compatible = "qcom,geni-spi"; 1425 reg = <0x0 0x00988000 0x0 0x4000>; 1426 clock-names = "se"; 1427 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1428 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1429 pinctrl-names = "default"; 1430 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1431 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1432 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1433 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1434 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1435 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1436 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1437 dma-names = "tx", "rx"; 1438 #address-cells = <1>; 1439 #size-cells = <0>; 1440 status = "disabled"; 1441 }; 1442 1443 1444 i2c3: i2c@98c000 { 1445 compatible = "qcom,geni-i2c"; 1446 reg = <0x0 0x0098c000 0x0 0x4000>; 1447 clock-names = "se"; 1448 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1449 pinctrl-names = "default"; 1450 pinctrl-0 = <&qup_i2c3_data_clk>; 1451 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1452 #address-cells = <1>; 1453 #size-cells = <0>; 1454 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1455 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1456 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1457 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1458 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1459 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1460 dma-names = "tx", "rx"; 1461 status = "disabled"; 1462 }; 1463 1464 spi3: spi@98c000 { 1465 compatible = "qcom,geni-spi"; 1466 reg = <0x0 0x0098c000 0x0 0x4000>; 1467 clock-names = "se"; 1468 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1469 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1470 pinctrl-names = "default"; 1471 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1472 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1473 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1474 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1475 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1476 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1477 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1478 dma-names = "tx", "rx"; 1479 #address-cells = <1>; 1480 #size-cells = <0>; 1481 status = "disabled"; 1482 }; 1483 1484 i2c4: i2c@990000 { 1485 compatible = "qcom,geni-i2c"; 1486 reg = <0x0 0x00990000 0x0 0x4000>; 1487 clock-names = "se"; 1488 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1489 pinctrl-names = "default"; 1490 pinctrl-0 = <&qup_i2c4_data_clk>; 1491 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1492 #address-cells = <1>; 1493 #size-cells = <0>; 1494 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1495 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1496 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1497 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1498 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1499 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1500 dma-names = "tx", "rx"; 1501 status = "disabled"; 1502 }; 1503 1504 spi4: spi@990000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0x0 0x00990000 0x0 0x4000>; 1507 clock-names = "se"; 1508 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1509 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1510 pinctrl-names = "default"; 1511 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1512 power-domains = <&rpmhpd RPMHPD_CX>; 1513 operating-points-v2 = <&qup_opp_table_100mhz>; 1514 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1515 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1516 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1517 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1518 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1519 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1520 dma-names = "tx", "rx"; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 status = "disabled"; 1524 }; 1525 1526 i2c5: i2c@994000 { 1527 compatible = "qcom,geni-i2c"; 1528 reg = <0x0 0x00994000 0x0 0x4000>; 1529 clock-names = "se"; 1530 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1531 pinctrl-names = "default"; 1532 pinctrl-0 = <&qup_i2c5_data_clk>; 1533 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1534 #address-cells = <1>; 1535 #size-cells = <0>; 1536 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1537 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1538 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1539 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1540 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1541 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1542 dma-names = "tx", "rx"; 1543 status = "disabled"; 1544 }; 1545 1546 spi5: spi@994000 { 1547 compatible = "qcom,geni-spi"; 1548 reg = <0x0 0x00994000 0x0 0x4000>; 1549 clock-names = "se"; 1550 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1551 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1552 pinctrl-names = "default"; 1553 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1554 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1555 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1556 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1557 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1558 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1559 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1560 dma-names = "tx", "rx"; 1561 #address-cells = <1>; 1562 #size-cells = <0>; 1563 status = "disabled"; 1564 }; 1565 1566 1567 i2c6: i2c@998000 { 1568 compatible = "qcom,geni-i2c"; 1569 reg = <0x0 0x00998000 0x0 0x4000>; 1570 clock-names = "se"; 1571 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1572 pinctrl-names = "default"; 1573 pinctrl-0 = <&qup_i2c6_data_clk>; 1574 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1578 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1579 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1580 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1581 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1582 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1583 dma-names = "tx", "rx"; 1584 status = "disabled"; 1585 }; 1586 1587 spi6: spi@998000 { 1588 compatible = "qcom,geni-spi"; 1589 reg = <0x0 0x00998000 0x0 0x4000>; 1590 clock-names = "se"; 1591 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1592 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1593 pinctrl-names = "default"; 1594 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1595 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1596 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1597 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1598 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1599 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1600 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1601 dma-names = "tx", "rx"; 1602 #address-cells = <1>; 1603 #size-cells = <0>; 1604 status = "disabled"; 1605 }; 1606 1607 uart7: serial@99c000 { 1608 compatible = "qcom,geni-debug-uart"; 1609 reg = <0 0x0099c000 0 0x4000>; 1610 clock-names = "se"; 1611 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1612 pinctrl-names = "default"; 1613 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1614 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1615 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1616 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1617 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1618 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1619 interconnect-names = "qup-core", 1620 "qup-config"; 1621 status = "disabled"; 1622 }; 1623 }; 1624 1625 gpi_dma1: dma-controller@a00000 { 1626 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; 1627 #dma-cells = <3>; 1628 reg = <0 0x00a00000 0 0x60000>; 1629 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1630 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1631 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1632 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1633 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1636 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1641 dma-channels = <12>; 1642 dma-channel-mask = <0x7e>; 1643 iommus = <&apps_smmu 0x56 0x0>; 1644 status = "disabled"; 1645 }; 1646 1647 qupv3_id_1: geniqup@ac0000 { 1648 compatible = "qcom,geni-se-qup"; 1649 reg = <0x0 0x00ac0000 0x0 0x6000>; 1650 clock-names = "m-ahb", "s-ahb"; 1651 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1652 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1653 iommus = <&apps_smmu 0x43 0x0>; 1654 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>; 1655 interconnect-names = "qup-core"; 1656 #address-cells = <2>; 1657 #size-cells = <2>; 1658 ranges; 1659 status = "disabled"; 1660 1661 i2c8: i2c@a80000 { 1662 compatible = "qcom,geni-i2c"; 1663 reg = <0x0 0x00a80000 0x0 0x4000>; 1664 clock-names = "se"; 1665 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1666 pinctrl-names = "default"; 1667 pinctrl-0 = <&qup_i2c8_data_clk>; 1668 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1669 #address-cells = <1>; 1670 #size-cells = <0>; 1671 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1672 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1673 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1674 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1675 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1676 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1677 dma-names = "tx", "rx"; 1678 status = "disabled"; 1679 }; 1680 1681 spi8: spi@a80000 { 1682 compatible = "qcom,geni-spi"; 1683 reg = <0x0 0x00a80000 0x0 0x4000>; 1684 clock-names = "se"; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1686 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1687 pinctrl-names = "default"; 1688 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1690 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1691 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1692 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1693 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1694 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1695 dma-names = "tx", "rx"; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 status = "disabled"; 1699 }; 1700 1701 i2c9: i2c@a84000 { 1702 compatible = "qcom,geni-i2c"; 1703 reg = <0x0 0x00a84000 0x0 0x4000>; 1704 clock-names = "se"; 1705 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1706 pinctrl-names = "default"; 1707 pinctrl-0 = <&qup_i2c9_data_clk>; 1708 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1709 #address-cells = <1>; 1710 #size-cells = <0>; 1711 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1712 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1713 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1714 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1715 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1716 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1717 dma-names = "tx", "rx"; 1718 status = "disabled"; 1719 }; 1720 1721 spi9: spi@a84000 { 1722 compatible = "qcom,geni-spi"; 1723 reg = <0x0 0x00a84000 0x0 0x4000>; 1724 clock-names = "se"; 1725 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1726 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1727 pinctrl-names = "default"; 1728 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1729 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1730 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1731 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1732 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1733 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1734 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1735 dma-names = "tx", "rx"; 1736 #address-cells = <1>; 1737 #size-cells = <0>; 1738 status = "disabled"; 1739 }; 1740 1741 i2c10: i2c@a88000 { 1742 compatible = "qcom,geni-i2c"; 1743 reg = <0x0 0x00a88000 0x0 0x4000>; 1744 clock-names = "se"; 1745 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1746 pinctrl-names = "default"; 1747 pinctrl-0 = <&qup_i2c10_data_clk>; 1748 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1752 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1753 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1754 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1755 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1756 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1757 dma-names = "tx", "rx"; 1758 status = "disabled"; 1759 }; 1760 1761 spi10: spi@a88000 { 1762 compatible = "qcom,geni-spi"; 1763 reg = <0x0 0x00a88000 0x0 0x4000>; 1764 clock-names = "se"; 1765 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1766 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1767 pinctrl-names = "default"; 1768 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1769 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1770 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1771 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1772 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1773 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1774 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1775 dma-names = "tx", "rx"; 1776 #address-cells = <1>; 1777 #size-cells = <0>; 1778 status = "disabled"; 1779 }; 1780 1781 i2c11: i2c@a8c000 { 1782 compatible = "qcom,geni-i2c"; 1783 reg = <0x0 0x00a8c000 0x0 0x4000>; 1784 clock-names = "se"; 1785 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1786 pinctrl-names = "default"; 1787 pinctrl-0 = <&qup_i2c11_data_clk>; 1788 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1789 #address-cells = <1>; 1790 #size-cells = <0>; 1791 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1792 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1793 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1794 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1795 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1796 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1797 dma-names = "tx", "rx"; 1798 status = "disabled"; 1799 }; 1800 1801 spi11: spi@a8c000 { 1802 compatible = "qcom,geni-spi"; 1803 reg = <0x0 0x00a8c000 0x0 0x4000>; 1804 clock-names = "se"; 1805 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1806 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1807 pinctrl-names = "default"; 1808 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1809 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1810 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1811 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1812 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1813 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1814 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1815 dma-names = "tx", "rx"; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 status = "disabled"; 1819 }; 1820 1821 i2c12: i2c@a90000 { 1822 compatible = "qcom,geni-i2c"; 1823 reg = <0x0 0x00a90000 0x0 0x4000>; 1824 clock-names = "se"; 1825 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1826 pinctrl-names = "default"; 1827 pinctrl-0 = <&qup_i2c12_data_clk>; 1828 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1832 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1833 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1834 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1835 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1836 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1837 dma-names = "tx", "rx"; 1838 status = "disabled"; 1839 }; 1840 1841 spi12: spi@a90000 { 1842 compatible = "qcom,geni-spi"; 1843 reg = <0x0 0x00a90000 0x0 0x4000>; 1844 clock-names = "se"; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1846 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1847 pinctrl-names = "default"; 1848 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1849 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1850 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1851 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1852 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1853 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1854 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1855 dma-names = "tx", "rx"; 1856 #address-cells = <1>; 1857 #size-cells = <0>; 1858 status = "disabled"; 1859 }; 1860 1861 i2c13: i2c@a94000 { 1862 compatible = "qcom,geni-i2c"; 1863 reg = <0 0x00a94000 0 0x4000>; 1864 clock-names = "se"; 1865 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1866 pinctrl-names = "default"; 1867 pinctrl-0 = <&qup_i2c13_data_clk>; 1868 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1869 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1870 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1871 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1872 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1873 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1874 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1875 dma-names = "tx", "rx"; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 status = "disabled"; 1879 }; 1880 1881 spi13: spi@a94000 { 1882 compatible = "qcom,geni-spi"; 1883 reg = <0x0 0x00a94000 0x0 0x4000>; 1884 clock-names = "se"; 1885 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1886 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1887 pinctrl-names = "default"; 1888 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1889 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1890 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1891 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1892 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1893 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1894 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1895 dma-names = "tx", "rx"; 1896 #address-cells = <1>; 1897 #size-cells = <0>; 1898 status = "disabled"; 1899 }; 1900 1901 i2c14: i2c@a98000 { 1902 compatible = "qcom,geni-i2c"; 1903 reg = <0 0x00a98000 0 0x4000>; 1904 clock-names = "se"; 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1906 pinctrl-names = "default"; 1907 pinctrl-0 = <&qup_i2c14_data_clk>; 1908 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1909 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1910 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1911 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1912 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1913 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1914 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1915 dma-names = "tx", "rx"; 1916 #address-cells = <1>; 1917 #size-cells = <0>; 1918 status = "disabled"; 1919 }; 1920 1921 spi14: spi@a98000 { 1922 compatible = "qcom,geni-spi"; 1923 reg = <0x0 0x00a98000 0x0 0x4000>; 1924 clock-names = "se"; 1925 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1926 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1927 pinctrl-names = "default"; 1928 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1929 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1930 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>, 1931 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1932 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1933 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1934 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1935 dma-names = "tx", "rx"; 1936 #address-cells = <1>; 1937 #size-cells = <0>; 1938 status = "disabled"; 1939 }; 1940 }; 1941 1942 rng: rng@10c3000 { 1943 compatible = "qcom,sm8450-trng", "qcom,trng"; 1944 reg = <0 0x010c3000 0 0x1000>; 1945 }; 1946 1947 pcie0: pcie@1c00000 { 1948 compatible = "qcom,pcie-sm8450-pcie0"; 1949 reg = <0 0x01c00000 0 0x3000>, 1950 <0 0x60000000 0 0xf1d>, 1951 <0 0x60000f20 0 0xa8>, 1952 <0 0x60001000 0 0x1000>, 1953 <0 0x60100000 0 0x100000>; 1954 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1955 device_type = "pci"; 1956 linux,pci-domain = <0>; 1957 bus-range = <0x00 0xff>; 1958 num-lanes = <1>; 1959 1960 #address-cells = <3>; 1961 #size-cells = <2>; 1962 1963 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1964 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1965 1966 msi-map = <0x0 &gic_its 0x5980 0x1>, 1967 <0x100 &gic_its 0x5981 0x1>; 1968 msi-map-mask = <0xff00>; 1969 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1970 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1971 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1972 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1973 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1974 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1975 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1976 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1977 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1978 interrupt-names = "msi0", 1979 "msi1", 1980 "msi2", 1981 "msi3", 1982 "msi4", 1983 "msi5", 1984 "msi6", 1985 "msi7", 1986 "global"; 1987 #interrupt-cells = <1>; 1988 interrupt-map-mask = <0 0 0 0x7>; 1989 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1990 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1991 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1992 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1993 1994 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 1995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1996 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1997 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 1998 interconnect-names = "pcie-mem", "cpu-pcie"; 1999 2000 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2001 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 2002 <&pcie0_phy>, 2003 <&rpmhcc RPMH_CXO_CLK>, 2004 <&gcc GCC_PCIE_0_AUX_CLK>, 2005 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2006 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2007 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2008 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2009 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2010 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2011 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2012 clock-names = "pipe", 2013 "pipe_mux", 2014 "phy_pipe", 2015 "ref", 2016 "aux", 2017 "cfg", 2018 "bus_master", 2019 "bus_slave", 2020 "slave_q2a", 2021 "ddrss_sf_tbu", 2022 "aggre0", 2023 "aggre1"; 2024 2025 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2026 <0x100 &apps_smmu 0x1c01 0x1>; 2027 2028 resets = <&gcc GCC_PCIE_0_BCR>; 2029 reset-names = "pci"; 2030 2031 power-domains = <&gcc PCIE_0_GDSC>; 2032 2033 phys = <&pcie0_phy>; 2034 phy-names = "pciephy"; 2035 2036 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; 2037 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; 2038 2039 pinctrl-names = "default"; 2040 pinctrl-0 = <&pcie0_default_state>; 2041 2042 operating-points-v2 = <&pcie0_opp_table>; 2043 2044 status = "disabled"; 2045 2046 pcie0_opp_table: opp-table { 2047 compatible = "operating-points-v2"; 2048 2049 /* GEN 1 x1 */ 2050 opp-2500000 { 2051 opp-hz = /bits/ 64 <2500000>; 2052 required-opps = <&rpmhpd_opp_low_svs>; 2053 opp-peak-kBps = <250000 1>; 2054 }; 2055 2056 /* GEN 2 x1 */ 2057 opp-5000000 { 2058 opp-hz = /bits/ 64 <5000000>; 2059 required-opps = <&rpmhpd_opp_low_svs>; 2060 opp-peak-kBps = <500000 1>; 2061 }; 2062 2063 /* GEN 3 x1 */ 2064 opp-8000000 { 2065 opp-hz = /bits/ 64 <8000000>; 2066 required-opps = <&rpmhpd_opp_nom>; 2067 opp-peak-kBps = <984500 1>; 2068 }; 2069 }; 2070 2071 pcieport0: pcie@0 { 2072 device_type = "pci"; 2073 reg = <0x0 0x0 0x0 0x0 0x0>; 2074 bus-range = <0x01 0xff>; 2075 2076 #address-cells = <3>; 2077 #size-cells = <2>; 2078 ranges; 2079 }; 2080 }; 2081 2082 pcie0_phy: phy@1c06000 { 2083 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; 2084 reg = <0 0x01c06000 0 0x2000>; 2085 2086 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2087 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2088 <&gcc GCC_PCIE_0_CLKREF_EN>, 2089 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2090 <&gcc GCC_PCIE_0_PIPE_CLK>; 2091 clock-names = "aux", 2092 "cfg_ahb", 2093 "ref", 2094 "rchng", 2095 "pipe"; 2096 2097 clock-output-names = "pcie_0_pipe_clk"; 2098 #clock-cells = <0>; 2099 2100 #phy-cells = <0>; 2101 2102 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2103 reset-names = "phy"; 2104 2105 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2106 assigned-clock-rates = <100000000>; 2107 2108 status = "disabled"; 2109 }; 2110 2111 pcie1: pcie@1c08000 { 2112 compatible = "qcom,pcie-sm8450-pcie1"; 2113 reg = <0 0x01c08000 0 0x3000>, 2114 <0 0x40000000 0 0xf1d>, 2115 <0 0x40000f20 0 0xa8>, 2116 <0 0x40001000 0 0x1000>, 2117 <0 0x40100000 0 0x100000>; 2118 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2119 device_type = "pci"; 2120 linux,pci-domain = <1>; 2121 bus-range = <0x00 0xff>; 2122 num-lanes = <2>; 2123 2124 #address-cells = <3>; 2125 #size-cells = <2>; 2126 2127 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2128 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2129 2130 msi-map = <0x0 &gic_its 0x5a00 0x1>, 2131 <0x100 &gic_its 0x5a01 0x1>; 2132 msi-map-mask = <0xff00>; 2133 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2142 interrupt-names = "msi0", 2143 "msi1", 2144 "msi2", 2145 "msi3", 2146 "msi4", 2147 "msi5", 2148 "msi6", 2149 "msi7", 2150 "global"; 2151 #interrupt-cells = <1>; 2152 interrupt-map-mask = <0 0 0 0x7>; 2153 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2154 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2155 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2156 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2157 2158 interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS 2159 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2160 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2161 &config_noc SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; 2162 interconnect-names = "pcie-mem", "cpu-pcie"; 2163 2164 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2165 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2166 <&pcie1_phy QMP_PCIE_PIPE_CLK>, 2167 <&rpmhcc RPMH_CXO_CLK>, 2168 <&gcc GCC_PCIE_1_AUX_CLK>, 2169 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2170 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2171 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2172 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2173 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2174 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2175 clock-names = "pipe", 2176 "pipe_mux", 2177 "phy_pipe", 2178 "ref", 2179 "aux", 2180 "cfg", 2181 "bus_master", 2182 "bus_slave", 2183 "slave_q2a", 2184 "ddrss_sf_tbu", 2185 "aggre1"; 2186 2187 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2188 <0x100 &apps_smmu 0x1c81 0x1>; 2189 2190 resets = <&gcc GCC_PCIE_1_BCR>; 2191 reset-names = "pci"; 2192 2193 power-domains = <&gcc PCIE_1_GDSC>; 2194 2195 phys = <&pcie1_phy>; 2196 phy-names = "pciephy"; 2197 2198 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; 2199 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; 2200 2201 pinctrl-names = "default"; 2202 pinctrl-0 = <&pcie1_default_state>; 2203 2204 operating-points-v2 = <&pcie1_opp_table>; 2205 2206 status = "disabled"; 2207 2208 pcie1_opp_table: opp-table { 2209 compatible = "operating-points-v2"; 2210 2211 /* GEN 1 x1 */ 2212 opp-2500000 { 2213 opp-hz = /bits/ 64 <2500000>; 2214 required-opps = <&rpmhpd_opp_low_svs>; 2215 opp-peak-kBps = <250000 1>; 2216 }; 2217 2218 /* GEN 1 x2 and GEN 2 x1 */ 2219 opp-5000000 { 2220 opp-hz = /bits/ 64 <5000000>; 2221 required-opps = <&rpmhpd_opp_low_svs>; 2222 opp-peak-kBps = <500000 1>; 2223 }; 2224 2225 /* GEN 2 x2 */ 2226 opp-10000000 { 2227 opp-hz = /bits/ 64 <10000000>; 2228 required-opps = <&rpmhpd_opp_low_svs>; 2229 opp-peak-kBps = <1000000 1>; 2230 }; 2231 2232 /* GEN 3 x1 */ 2233 opp-8000000 { 2234 opp-hz = /bits/ 64 <8000000>; 2235 required-opps = <&rpmhpd_opp_nom>; 2236 opp-peak-kBps = <984500 1>; 2237 }; 2238 2239 /* GEN 3 x2 and GEN 4 x1 */ 2240 opp-16000000 { 2241 opp-hz = /bits/ 64 <16000000>; 2242 required-opps = <&rpmhpd_opp_nom>; 2243 opp-peak-kBps = <1969000 1>; 2244 }; 2245 2246 /* GEN 4 x2 */ 2247 opp-32000000 { 2248 opp-hz = /bits/ 64 <32000000>; 2249 required-opps = <&rpmhpd_opp_nom>; 2250 opp-peak-kBps = <3938000 1>; 2251 }; 2252 }; 2253 2254 pcie@0 { 2255 device_type = "pci"; 2256 reg = <0x0 0x0 0x0 0x0 0x0>; 2257 bus-range = <0x01 0xff>; 2258 2259 #address-cells = <3>; 2260 #size-cells = <2>; 2261 ranges; 2262 }; 2263 }; 2264 2265 pcie1_phy: phy@1c0e000 { 2266 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy"; 2267 reg = <0 0x01c0e000 0 0x2000>; 2268 2269 clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, 2270 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2271 <&gcc GCC_PCIE_1_CLKREF_EN>, 2272 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, 2273 <&gcc GCC_PCIE_1_PIPE_CLK>; 2274 clock-names = "aux", 2275 "cfg_ahb", 2276 "ref", 2277 "rchng", 2278 "pipe"; 2279 2280 clock-output-names = "pcie_1_pipe_clk"; 2281 #clock-cells = <1>; 2282 2283 #phy-cells = <0>; 2284 2285 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2286 reset-names = "phy"; 2287 2288 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; 2289 assigned-clock-rates = <100000000>; 2290 2291 status = "disabled"; 2292 }; 2293 2294 config_noc: interconnect@1500000 { 2295 compatible = "qcom,sm8450-config-noc"; 2296 reg = <0 0x01500000 0 0x1c000>; 2297 #interconnect-cells = <2>; 2298 qcom,bcm-voters = <&apps_bcm_voter>; 2299 }; 2300 2301 system_noc: interconnect@1680000 { 2302 compatible = "qcom,sm8450-system-noc"; 2303 reg = <0 0x01680000 0 0x1e200>; 2304 #interconnect-cells = <2>; 2305 qcom,bcm-voters = <&apps_bcm_voter>; 2306 }; 2307 2308 pcie_noc: interconnect@16c0000 { 2309 compatible = "qcom,sm8450-pcie-anoc"; 2310 reg = <0 0x016c0000 0 0xe280>; 2311 #interconnect-cells = <2>; 2312 qcom,bcm-voters = <&apps_bcm_voter>; 2313 }; 2314 2315 aggre1_noc: interconnect@16e0000 { 2316 compatible = "qcom,sm8450-aggre1-noc"; 2317 reg = <0 0x016e0000 0 0x1c080>; 2318 #interconnect-cells = <2>; 2319 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2320 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2321 qcom,bcm-voters = <&apps_bcm_voter>; 2322 }; 2323 2324 aggre2_noc: interconnect@1700000 { 2325 compatible = "qcom,sm8450-aggre2-noc"; 2326 reg = <0 0x01700000 0 0x31080>; 2327 #interconnect-cells = <2>; 2328 qcom,bcm-voters = <&apps_bcm_voter>; 2329 clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, 2330 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 2331 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2332 <&rpmhcc RPMH_IPA_CLK>; 2333 }; 2334 2335 mmss_noc: interconnect@1740000 { 2336 compatible = "qcom,sm8450-mmss-noc"; 2337 reg = <0 0x01740000 0 0x1f080>; 2338 #interconnect-cells = <2>; 2339 qcom,bcm-voters = <&apps_bcm_voter>; 2340 }; 2341 2342 tcsr_mutex: hwlock@1f40000 { 2343 compatible = "qcom,tcsr-mutex"; 2344 reg = <0x0 0x01f40000 0x0 0x40000>; 2345 #hwlock-cells = <1>; 2346 }; 2347 2348 tcsr: syscon@1fc0000 { 2349 compatible = "qcom,sm8450-tcsr", "syscon"; 2350 reg = <0x0 0x1fc0000 0x0 0x30000>; 2351 }; 2352 2353 gpu: gpu@3d00000 { 2354 compatible = "qcom,adreno-730.1", "qcom,adreno"; 2355 reg = <0x0 0x03d00000 0x0 0x40000>, 2356 <0x0 0x03d9e000 0x0 0x1000>, 2357 <0x0 0x03d61000 0x0 0x800>; 2358 reg-names = "kgsl_3d0_reg_memory", 2359 "cx_mem", 2360 "cx_dbgc"; 2361 2362 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2363 2364 iommus = <&adreno_smmu 0 0x400>, 2365 <&adreno_smmu 1 0x400>; 2366 2367 operating-points-v2 = <&gpu_opp_table>; 2368 2369 qcom,gmu = <&gmu>; 2370 #cooling-cells = <2>; 2371 2372 status = "disabled"; 2373 2374 zap-shader { 2375 memory-region = <&gpu_micro_code_mem>; 2376 }; 2377 2378 gpu_opp_table: opp-table { 2379 compatible = "operating-points-v2"; 2380 2381 opp-818000000 { 2382 opp-hz = /bits/ 64 <818000000>; 2383 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2384 }; 2385 2386 opp-791000000 { 2387 opp-hz = /bits/ 64 <791000000>; 2388 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2389 }; 2390 2391 opp-734000000 { 2392 opp-hz = /bits/ 64 <734000000>; 2393 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2394 }; 2395 2396 opp-640000000 { 2397 opp-hz = /bits/ 64 <640000000>; 2398 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2399 }; 2400 2401 opp-599000000 { 2402 opp-hz = /bits/ 64 <599000000>; 2403 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2404 }; 2405 2406 opp-545000000 { 2407 opp-hz = /bits/ 64 <545000000>; 2408 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2409 }; 2410 2411 opp-492000000 { 2412 opp-hz = /bits/ 64 <492000000>; 2413 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2414 }; 2415 2416 opp-421000000 { 2417 opp-hz = /bits/ 64 <421000000>; 2418 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 2419 }; 2420 2421 opp-350000000 { 2422 opp-hz = /bits/ 64 <350000000>; 2423 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2424 }; 2425 2426 opp-317000000 { 2427 opp-hz = /bits/ 64 <317000000>; 2428 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2429 }; 2430 2431 opp-285000000 { 2432 opp-hz = /bits/ 64 <285000000>; 2433 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2434 }; 2435 2436 opp-220000000 { 2437 opp-hz = /bits/ 64 <220000000>; 2438 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 2439 }; 2440 }; 2441 }; 2442 2443 gmu: gmu@3d6a000 { 2444 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu"; 2445 reg = <0x0 0x03d6a000 0x0 0x35000>, 2446 <0x0 0x03d50000 0x0 0x10000>, 2447 <0x0 0x0b290000 0x0 0x10000>; 2448 reg-names = "gmu", "rscc", "gmu_pdc"; 2449 2450 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2451 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2452 interrupt-names = "hfi", "gmu"; 2453 2454 clocks = <&gpucc GPU_CC_AHB_CLK>, 2455 <&gpucc GPU_CC_CX_GMU_CLK>, 2456 <&gpucc GPU_CC_CXO_CLK>, 2457 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2458 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2459 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2460 <&gpucc GPU_CC_DEMET_CLK>; 2461 clock-names = "ahb", 2462 "gmu", 2463 "cxo", 2464 "axi", 2465 "memnoc", 2466 "hub", 2467 "demet"; 2468 2469 power-domains = <&gpucc GPU_CX_GDSC>, 2470 <&gpucc GPU_GX_GDSC>; 2471 power-domain-names = "cx", 2472 "gx"; 2473 2474 iommus = <&adreno_smmu 5 0x400>; 2475 2476 qcom,qmp = <&aoss_qmp>; 2477 2478 operating-points-v2 = <&gmu_opp_table>; 2479 2480 gmu_opp_table: opp-table { 2481 compatible = "operating-points-v2"; 2482 2483 opp-500000000 { 2484 opp-hz = /bits/ 64 <500000000>; 2485 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2486 }; 2487 2488 opp-200000000 { 2489 opp-hz = /bits/ 64 <200000000>; 2490 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2491 }; 2492 }; 2493 }; 2494 2495 gpucc: clock-controller@3d90000 { 2496 compatible = "qcom,sm8450-gpucc"; 2497 reg = <0x0 0x03d90000 0x0 0xa000>; 2498 clocks = <&rpmhcc RPMH_CXO_CLK>, 2499 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2500 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2501 #clock-cells = <1>; 2502 #reset-cells = <1>; 2503 #power-domain-cells = <1>; 2504 }; 2505 2506 adreno_smmu: iommu@3da0000 { 2507 compatible = "qcom,sm8450-smmu-500", "qcom,adreno-smmu", 2508 "qcom,smmu-500", "arm,mmu-500"; 2509 reg = <0x0 0x03da0000 0x0 0x40000>; 2510 #iommu-cells = <2>; 2511 #global-interrupts = <1>; 2512 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2513 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2514 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2515 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2516 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2517 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2518 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2519 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2520 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2521 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2522 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2523 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2524 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 2525 <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>, 2526 <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>, 2527 <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 2528 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>, 2529 <GIC_SPI 659 IRQ_TYPE_LEVEL_HIGH>, 2530 <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH>, 2531 <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>, 2532 <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>, 2533 <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>, 2534 <GIC_SPI 668 IRQ_TYPE_LEVEL_HIGH>, 2535 <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>, 2536 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>; 2538 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2539 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2540 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2541 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2542 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2543 <&gpucc GPU_CC_AHB_CLK>; 2544 clock-names = "gmu", 2545 "hub", 2546 "hlos", 2547 "bus", 2548 "iface", 2549 "ahb"; 2550 power-domains = <&gpucc GPU_CX_GDSC>; 2551 dma-coherent; 2552 }; 2553 2554 usb_1_hsphy: phy@88e3000 { 2555 compatible = "qcom,sm8450-usb-hs-phy", 2556 "qcom,usb-snps-hs-7nm-phy"; 2557 reg = <0 0x088e3000 0 0x400>; 2558 status = "disabled"; 2559 #phy-cells = <0>; 2560 2561 clocks = <&rpmhcc RPMH_CXO_CLK>; 2562 clock-names = "ref"; 2563 2564 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2565 }; 2566 2567 usb_1_qmpphy: phy@88e8000 { 2568 compatible = "qcom,sm8450-qmp-usb3-dp-phy"; 2569 reg = <0 0x088e8000 0 0x3000>; 2570 2571 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2572 <&rpmhcc RPMH_CXO_CLK>, 2573 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2574 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2575 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2576 2577 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2578 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2579 reset-names = "phy", "common"; 2580 2581 #clock-cells = <1>; 2582 #phy-cells = <1>; 2583 2584 orientation-switch; 2585 2586 status = "disabled"; 2587 2588 ports { 2589 #address-cells = <1>; 2590 #size-cells = <0>; 2591 2592 port@0 { 2593 reg = <0>; 2594 2595 usb_1_qmpphy_out: endpoint { 2596 }; 2597 }; 2598 2599 port@1 { 2600 reg = <1>; 2601 2602 usb_1_qmpphy_usb_ss_in: endpoint { 2603 remote-endpoint = <&usb_1_dwc3_ss>; 2604 }; 2605 }; 2606 2607 port@2 { 2608 reg = <2>; 2609 2610 usb_1_qmpphy_dp_in: endpoint { 2611 remote-endpoint = <&mdss_dp0_out>; 2612 }; 2613 }; 2614 }; 2615 }; 2616 2617 remoteproc_slpi: remoteproc@2400000 { 2618 compatible = "qcom,sm8450-slpi-pas"; 2619 reg = <0 0x02400000 0 0x4000>; 2620 2621 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2622 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2623 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2624 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2625 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2626 interrupt-names = "wdog", "fatal", "ready", 2627 "handover", "stop-ack"; 2628 2629 clocks = <&rpmhcc RPMH_CXO_CLK>; 2630 clock-names = "xo"; 2631 2632 power-domains = <&rpmhpd RPMHPD_LCX>, 2633 <&rpmhpd RPMHPD_LMX>; 2634 power-domain-names = "lcx", "lmx"; 2635 2636 memory-region = <&slpi_mem>; 2637 2638 qcom,qmp = <&aoss_qmp>; 2639 2640 qcom,smem-states = <&smp2p_slpi_out 0>; 2641 qcom,smem-state-names = "stop"; 2642 2643 status = "disabled"; 2644 2645 glink-edge { 2646 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2647 IPCC_MPROC_SIGNAL_GLINK_QMP 2648 IRQ_TYPE_EDGE_RISING>; 2649 mboxes = <&ipcc IPCC_CLIENT_SLPI 2650 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2651 2652 label = "slpi"; 2653 qcom,remote-pid = <3>; 2654 2655 fastrpc { 2656 compatible = "qcom,fastrpc"; 2657 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2658 label = "sdsp"; 2659 qcom,non-secure-domain; 2660 #address-cells = <1>; 2661 #size-cells = <0>; 2662 2663 compute-cb@1 { 2664 compatible = "qcom,fastrpc-compute-cb"; 2665 reg = <1>; 2666 iommus = <&apps_smmu 0x0541 0x0>; 2667 }; 2668 2669 compute-cb@2 { 2670 compatible = "qcom,fastrpc-compute-cb"; 2671 reg = <2>; 2672 iommus = <&apps_smmu 0x0542 0x0>; 2673 }; 2674 2675 compute-cb@3 { 2676 compatible = "qcom,fastrpc-compute-cb"; 2677 reg = <3>; 2678 iommus = <&apps_smmu 0x0543 0x0>; 2679 /* note: shared-cb = <4> in downstream */ 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 remoteproc_adsp: remoteproc@3000000 { 2686 compatible = "qcom,sm8450-adsp-pas"; 2687 reg = <0x0 0x03000000 0x0 0x10000>; 2688 2689 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2690 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2691 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2692 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2693 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2694 interrupt-names = "wdog", "fatal", "ready", 2695 "handover", "stop-ack"; 2696 2697 clocks = <&rpmhcc RPMH_CXO_CLK>; 2698 clock-names = "xo"; 2699 2700 power-domains = <&rpmhpd RPMHPD_LCX>, 2701 <&rpmhpd RPMHPD_LMX>; 2702 power-domain-names = "lcx", "lmx"; 2703 2704 memory-region = <&adsp_mem>; 2705 2706 qcom,qmp = <&aoss_qmp>; 2707 2708 qcom,smem-states = <&smp2p_adsp_out 0>; 2709 qcom,smem-state-names = "stop"; 2710 2711 status = "disabled"; 2712 2713 remoteproc_adsp_glink: glink-edge { 2714 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2715 IPCC_MPROC_SIGNAL_GLINK_QMP 2716 IRQ_TYPE_EDGE_RISING>; 2717 mboxes = <&ipcc IPCC_CLIENT_LPASS 2718 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2719 2720 label = "lpass"; 2721 qcom,remote-pid = <2>; 2722 2723 gpr { 2724 compatible = "qcom,gpr"; 2725 qcom,glink-channels = "adsp_apps"; 2726 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2727 qcom,intents = <512 20>; 2728 #address-cells = <1>; 2729 #size-cells = <0>; 2730 2731 q6apm: service@1 { 2732 compatible = "qcom,q6apm"; 2733 reg = <GPR_APM_MODULE_IID>; 2734 #sound-dai-cells = <0>; 2735 qcom,protection-domain = "avs/audio", 2736 "msm/adsp/audio_pd"; 2737 2738 q6apmdai: dais { 2739 compatible = "qcom,q6apm-dais"; 2740 iommus = <&apps_smmu 0x1801 0x0>; 2741 }; 2742 2743 q6apmbedai: bedais { 2744 compatible = "qcom,q6apm-lpass-dais"; 2745 #sound-dai-cells = <1>; 2746 }; 2747 }; 2748 2749 q6prm: service@2 { 2750 compatible = "qcom,q6prm"; 2751 reg = <GPR_PRM_MODULE_IID>; 2752 qcom,protection-domain = "avs/audio", 2753 "msm/adsp/audio_pd"; 2754 2755 q6prmcc: clock-controller { 2756 compatible = "qcom,q6prm-lpass-clocks"; 2757 #clock-cells = <2>; 2758 }; 2759 }; 2760 }; 2761 2762 fastrpc { 2763 compatible = "qcom,fastrpc"; 2764 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2765 label = "adsp"; 2766 qcom,non-secure-domain; 2767 #address-cells = <1>; 2768 #size-cells = <0>; 2769 2770 compute-cb@3 { 2771 compatible = "qcom,fastrpc-compute-cb"; 2772 reg = <3>; 2773 iommus = <&apps_smmu 0x1803 0x0>; 2774 }; 2775 2776 compute-cb@4 { 2777 compatible = "qcom,fastrpc-compute-cb"; 2778 reg = <4>; 2779 iommus = <&apps_smmu 0x1804 0x0>; 2780 }; 2781 2782 compute-cb@5 { 2783 compatible = "qcom,fastrpc-compute-cb"; 2784 reg = <5>; 2785 iommus = <&apps_smmu 0x1805 0x0>; 2786 }; 2787 }; 2788 }; 2789 }; 2790 2791 wsa2macro: codec@31e0000 { 2792 compatible = "qcom,sm8450-lpass-wsa-macro"; 2793 reg = <0 0x031e0000 0 0x1000>; 2794 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2795 <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2796 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2797 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2798 <&vamacro>; 2799 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2800 2801 #clock-cells = <0>; 2802 clock-output-names = "wsa2-mclk"; 2803 #sound-dai-cells = <1>; 2804 }; 2805 2806 swr4: soundwire@31f0000 { 2807 compatible = "qcom,soundwire-v1.7.0"; 2808 reg = <0 0x031f0000 0 0x2000>; 2809 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2810 clocks = <&wsa2macro>; 2811 clock-names = "iface"; 2812 label = "WSA2"; 2813 2814 pinctrl-0 = <&wsa2_swr_active>; 2815 pinctrl-names = "default"; 2816 2817 qcom,din-ports = <2>; 2818 qcom,dout-ports = <6>; 2819 2820 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2821 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2822 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2823 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2824 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2825 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2826 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2827 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2828 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2829 2830 #address-cells = <2>; 2831 #size-cells = <0>; 2832 #sound-dai-cells = <1>; 2833 status = "disabled"; 2834 }; 2835 2836 rxmacro: codec@3200000 { 2837 compatible = "qcom,sm8450-lpass-rx-macro"; 2838 reg = <0 0x03200000 0 0x1000>; 2839 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2840 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2841 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2842 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2843 <&vamacro>; 2844 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2845 2846 #clock-cells = <0>; 2847 clock-output-names = "mclk"; 2848 #sound-dai-cells = <1>; 2849 }; 2850 2851 swr1: soundwire@3210000 { 2852 compatible = "qcom,soundwire-v1.7.0"; 2853 reg = <0 0x03210000 0 0x2000>; 2854 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2855 clocks = <&rxmacro>; 2856 clock-names = "iface"; 2857 label = "RX"; 2858 qcom,din-ports = <0>; 2859 qcom,dout-ports = <5>; 2860 2861 pinctrl-0 = <&rx_swr_active>; 2862 pinctrl-names = "default"; 2863 2864 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2865 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2866 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2867 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2868 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2869 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2870 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2871 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2872 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2873 2874 #address-cells = <2>; 2875 #size-cells = <0>; 2876 #sound-dai-cells = <1>; 2877 status = "disabled"; 2878 }; 2879 2880 txmacro: codec@3220000 { 2881 compatible = "qcom,sm8450-lpass-tx-macro"; 2882 reg = <0 0x03220000 0 0x1000>; 2883 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2884 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2885 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2886 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2887 <&vamacro>; 2888 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2889 2890 #clock-cells = <0>; 2891 clock-output-names = "mclk"; 2892 #sound-dai-cells = <1>; 2893 }; 2894 2895 wsamacro: codec@3240000 { 2896 compatible = "qcom,sm8450-lpass-wsa-macro"; 2897 reg = <0 0x03240000 0 0x1000>; 2898 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2899 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2900 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2901 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2902 <&vamacro>; 2903 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2904 2905 #clock-cells = <0>; 2906 clock-output-names = "mclk"; 2907 #sound-dai-cells = <1>; 2908 }; 2909 2910 swr0: soundwire@3250000 { 2911 compatible = "qcom,soundwire-v1.7.0"; 2912 reg = <0 0x03250000 0 0x2000>; 2913 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2914 clocks = <&wsamacro>; 2915 clock-names = "iface"; 2916 label = "WSA"; 2917 2918 pinctrl-0 = <&wsa_swr_active>; 2919 pinctrl-names = "default"; 2920 2921 qcom,din-ports = <2>; 2922 qcom,dout-ports = <6>; 2923 2924 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2925 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2926 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2927 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2928 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2929 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2930 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2931 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2932 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2933 2934 #address-cells = <2>; 2935 #size-cells = <0>; 2936 #sound-dai-cells = <1>; 2937 status = "disabled"; 2938 }; 2939 2940 swr2: soundwire@33b0000 { 2941 compatible = "qcom,soundwire-v1.7.0"; 2942 reg = <0 0x033b0000 0 0x2000>; 2943 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2944 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2945 interrupt-names = "core", "wakeup"; 2946 2947 clocks = <&txmacro>; 2948 clock-names = "iface"; 2949 label = "TX"; 2950 2951 pinctrl-0 = <&tx_swr_active>; 2952 pinctrl-names = "default"; 2953 2954 qcom,din-ports = <4>; 2955 qcom,dout-ports = <0>; 2956 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2957 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2958 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2959 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2960 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2961 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2962 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2963 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2964 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2965 2966 #address-cells = <2>; 2967 #size-cells = <0>; 2968 #sound-dai-cells = <1>; 2969 status = "disabled"; 2970 }; 2971 2972 vamacro: codec@33f0000 { 2973 compatible = "qcom,sm8450-lpass-va-macro"; 2974 reg = <0 0x033f0000 0 0x1000>; 2975 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2976 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2977 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2978 <&q6prmcc LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2979 clock-names = "mclk", "macro", "dcodec", "npl"; 2980 2981 #clock-cells = <0>; 2982 clock-output-names = "fsgen"; 2983 #sound-dai-cells = <1>; 2984 status = "disabled"; 2985 }; 2986 2987 remoteproc_cdsp: remoteproc@32300000 { 2988 compatible = "qcom,sm8450-cdsp-pas"; 2989 reg = <0 0x32300000 0 0x10000>; 2990 2991 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2992 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2993 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2994 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2995 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2996 interrupt-names = "wdog", "fatal", "ready", 2997 "handover", "stop-ack"; 2998 2999 clocks = <&rpmhcc RPMH_CXO_CLK>; 3000 clock-names = "xo"; 3001 3002 power-domains = <&rpmhpd RPMHPD_CX>, 3003 <&rpmhpd RPMHPD_MXC>; 3004 power-domain-names = "cx", "mxc"; 3005 3006 memory-region = <&cdsp_mem>; 3007 3008 qcom,qmp = <&aoss_qmp>; 3009 3010 qcom,smem-states = <&smp2p_cdsp_out 0>; 3011 qcom,smem-state-names = "stop"; 3012 3013 status = "disabled"; 3014 3015 glink-edge { 3016 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3017 IPCC_MPROC_SIGNAL_GLINK_QMP 3018 IRQ_TYPE_EDGE_RISING>; 3019 mboxes = <&ipcc IPCC_CLIENT_CDSP 3020 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3021 3022 label = "cdsp"; 3023 qcom,remote-pid = <5>; 3024 3025 fastrpc { 3026 compatible = "qcom,fastrpc"; 3027 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3028 label = "cdsp"; 3029 qcom,non-secure-domain; 3030 #address-cells = <1>; 3031 #size-cells = <0>; 3032 3033 compute-cb@1 { 3034 compatible = "qcom,fastrpc-compute-cb"; 3035 reg = <1>; 3036 iommus = <&apps_smmu 0x2161 0x0400>, 3037 <&apps_smmu 0x1021 0x1420>; 3038 }; 3039 3040 compute-cb@2 { 3041 compatible = "qcom,fastrpc-compute-cb"; 3042 reg = <2>; 3043 iommus = <&apps_smmu 0x2162 0x0400>, 3044 <&apps_smmu 0x1022 0x1420>; 3045 }; 3046 3047 compute-cb@3 { 3048 compatible = "qcom,fastrpc-compute-cb"; 3049 reg = <3>; 3050 iommus = <&apps_smmu 0x2163 0x0400>, 3051 <&apps_smmu 0x1023 0x1420>; 3052 }; 3053 3054 compute-cb@4 { 3055 compatible = "qcom,fastrpc-compute-cb"; 3056 reg = <4>; 3057 iommus = <&apps_smmu 0x2164 0x0400>, 3058 <&apps_smmu 0x1024 0x1420>; 3059 }; 3060 3061 compute-cb@5 { 3062 compatible = "qcom,fastrpc-compute-cb"; 3063 reg = <5>; 3064 iommus = <&apps_smmu 0x2165 0x0400>, 3065 <&apps_smmu 0x1025 0x1420>; 3066 }; 3067 3068 compute-cb@6 { 3069 compatible = "qcom,fastrpc-compute-cb"; 3070 reg = <6>; 3071 iommus = <&apps_smmu 0x2166 0x0400>, 3072 <&apps_smmu 0x1026 0x1420>; 3073 }; 3074 3075 compute-cb@7 { 3076 compatible = "qcom,fastrpc-compute-cb"; 3077 reg = <7>; 3078 iommus = <&apps_smmu 0x2167 0x0400>, 3079 <&apps_smmu 0x1027 0x1420>; 3080 }; 3081 3082 compute-cb@8 { 3083 compatible = "qcom,fastrpc-compute-cb"; 3084 reg = <8>; 3085 iommus = <&apps_smmu 0x2168 0x0400>, 3086 <&apps_smmu 0x1028 0x1420>; 3087 }; 3088 3089 /* note: secure cb9 in downstream */ 3090 }; 3091 }; 3092 }; 3093 3094 remoteproc_mpss: remoteproc@4080000 { 3095 compatible = "qcom,sm8450-mpss-pas"; 3096 reg = <0x0 0x04080000 0x0 0x10000>; 3097 3098 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3099 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 3100 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 3101 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 3102 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 3103 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 3104 interrupt-names = "wdog", "fatal", "ready", "handover", 3105 "stop-ack", "shutdown-ack"; 3106 3107 clocks = <&rpmhcc RPMH_CXO_CLK>; 3108 clock-names = "xo"; 3109 3110 power-domains = <&rpmhpd RPMHPD_CX>, 3111 <&rpmhpd RPMHPD_MSS>; 3112 power-domain-names = "cx", "mss"; 3113 3114 memory-region = <&mpss_mem>; 3115 3116 qcom,qmp = <&aoss_qmp>; 3117 3118 qcom,smem-states = <&smp2p_modem_out 0>; 3119 qcom,smem-state-names = "stop"; 3120 3121 status = "disabled"; 3122 3123 glink-edge { 3124 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3125 IPCC_MPROC_SIGNAL_GLINK_QMP 3126 IRQ_TYPE_EDGE_RISING>; 3127 mboxes = <&ipcc IPCC_CLIENT_MPSS 3128 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3129 label = "modem"; 3130 qcom,remote-pid = <1>; 3131 }; 3132 }; 3133 3134 videocc: clock-controller@aaf0000 { 3135 compatible = "qcom,sm8450-videocc"; 3136 reg = <0 0x0aaf0000 0 0x10000>; 3137 clocks = <&rpmhcc RPMH_CXO_CLK>, 3138 <&gcc GCC_VIDEO_AHB_CLK>; 3139 power-domains = <&rpmhpd RPMHPD_MMCX>; 3140 required-opps = <&rpmhpd_opp_low_svs>; 3141 #clock-cells = <1>; 3142 #reset-cells = <1>; 3143 #power-domain-cells = <1>; 3144 }; 3145 3146 cci0: cci@ac15000 { 3147 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 3148 reg = <0 0x0ac15000 0 0x1000>; 3149 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3150 power-domains = <&camcc TITAN_TOP_GDSC>; 3151 3152 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3153 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3154 <&camcc CAM_CC_CPAS_AHB_CLK>, 3155 <&camcc CAM_CC_CCI_0_CLK>, 3156 <&camcc CAM_CC_CCI_0_CLK_SRC>; 3157 clock-names = "camnoc_axi", 3158 "slow_ahb_src", 3159 "cpas_ahb", 3160 "cci", 3161 "cci_src"; 3162 pinctrl-0 = <&cci0_default &cci1_default>; 3163 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 3164 pinctrl-names = "default", "sleep"; 3165 3166 status = "disabled"; 3167 #address-cells = <1>; 3168 #size-cells = <0>; 3169 3170 cci0_i2c0: i2c-bus@0 { 3171 reg = <0>; 3172 clock-frequency = <1000000>; 3173 #address-cells = <1>; 3174 #size-cells = <0>; 3175 }; 3176 3177 cci0_i2c1: i2c-bus@1 { 3178 reg = <1>; 3179 clock-frequency = <1000000>; 3180 #address-cells = <1>; 3181 #size-cells = <0>; 3182 }; 3183 }; 3184 3185 cci1: cci@ac16000 { 3186 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; 3187 reg = <0 0x0ac16000 0 0x1000>; 3188 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3189 power-domains = <&camcc TITAN_TOP_GDSC>; 3190 3191 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 3192 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 3193 <&camcc CAM_CC_CPAS_AHB_CLK>, 3194 <&camcc CAM_CC_CCI_1_CLK>, 3195 <&camcc CAM_CC_CCI_1_CLK_SRC>; 3196 clock-names = "camnoc_axi", 3197 "slow_ahb_src", 3198 "cpas_ahb", 3199 "cci", 3200 "cci_src"; 3201 pinctrl-0 = <&cci2_default &cci3_default>; 3202 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 3203 pinctrl-names = "default", "sleep"; 3204 3205 status = "disabled"; 3206 #address-cells = <1>; 3207 #size-cells = <0>; 3208 3209 cci1_i2c0: i2c-bus@0 { 3210 reg = <0>; 3211 clock-frequency = <1000000>; 3212 #address-cells = <1>; 3213 #size-cells = <0>; 3214 }; 3215 3216 cci1_i2c1: i2c-bus@1 { 3217 reg = <1>; 3218 clock-frequency = <1000000>; 3219 #address-cells = <1>; 3220 #size-cells = <0>; 3221 }; 3222 }; 3223 3224 camcc: clock-controller@ade0000 { 3225 compatible = "qcom,sm8450-camcc"; 3226 reg = <0 0x0ade0000 0 0x20000>; 3227 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3228 <&rpmhcc RPMH_CXO_CLK>, 3229 <&rpmhcc RPMH_CXO_CLK_A>, 3230 <&sleep_clk>; 3231 power-domains = <&rpmhpd RPMHPD_MMCX>; 3232 required-opps = <&rpmhpd_opp_low_svs>; 3233 #clock-cells = <1>; 3234 #reset-cells = <1>; 3235 #power-domain-cells = <1>; 3236 status = "disabled"; 3237 }; 3238 3239 mdss: display-subsystem@ae00000 { 3240 compatible = "qcom,sm8450-mdss"; 3241 reg = <0 0x0ae00000 0 0x1000>; 3242 reg-names = "mdss"; 3243 3244 /* same path used twice */ 3245 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3246 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>, 3247 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3248 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3249 interconnect-names = "mdp0-mem", 3250 "mdp1-mem", 3251 "cpu-cfg"; 3252 3253 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3254 3255 power-domains = <&dispcc MDSS_GDSC>; 3256 3257 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3258 <&gcc GCC_DISP_HF_AXI_CLK>, 3259 <&gcc GCC_DISP_SF_AXI_CLK>, 3260 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3261 3262 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3263 interrupt-controller; 3264 #interrupt-cells = <1>; 3265 3266 iommus = <&apps_smmu 0x2800 0x402>; 3267 3268 #address-cells = <2>; 3269 #size-cells = <2>; 3270 ranges; 3271 3272 status = "disabled"; 3273 3274 mdss_mdp: display-controller@ae01000 { 3275 compatible = "qcom,sm8450-dpu"; 3276 reg = <0 0x0ae01000 0 0x8f000>, 3277 <0 0x0aeb0000 0 0x2008>; 3278 reg-names = "mdp", "vbif"; 3279 3280 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3281 <&gcc GCC_DISP_SF_AXI_CLK>, 3282 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3283 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3284 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3285 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3286 clock-names = "bus", 3287 "nrt_bus", 3288 "iface", 3289 "lut", 3290 "core", 3291 "vsync"; 3292 3293 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3294 assigned-clock-rates = <19200000>; 3295 3296 operating-points-v2 = <&mdp_opp_table>; 3297 power-domains = <&rpmhpd RPMHPD_MMCX>; 3298 3299 interrupt-parent = <&mdss>; 3300 interrupts = <0>; 3301 3302 ports { 3303 #address-cells = <1>; 3304 #size-cells = <0>; 3305 3306 port@0 { 3307 reg = <0>; 3308 dpu_intf1_out: endpoint { 3309 remote-endpoint = <&mdss_dsi0_in>; 3310 }; 3311 }; 3312 3313 port@1 { 3314 reg = <1>; 3315 dpu_intf2_out: endpoint { 3316 remote-endpoint = <&mdss_dsi1_in>; 3317 }; 3318 }; 3319 3320 port@2 { 3321 reg = <2>; 3322 dpu_intf0_out: endpoint { 3323 remote-endpoint = <&mdss_dp0_in>; 3324 }; 3325 }; 3326 }; 3327 3328 mdp_opp_table: opp-table { 3329 compatible = "operating-points-v2"; 3330 3331 opp-172000000 { 3332 opp-hz = /bits/ 64 <172000000>; 3333 required-opps = <&rpmhpd_opp_low_svs_d1>; 3334 }; 3335 3336 opp-200000000 { 3337 opp-hz = /bits/ 64 <200000000>; 3338 required-opps = <&rpmhpd_opp_low_svs>; 3339 }; 3340 3341 opp-325000000 { 3342 opp-hz = /bits/ 64 <325000000>; 3343 required-opps = <&rpmhpd_opp_svs>; 3344 }; 3345 3346 opp-375000000 { 3347 opp-hz = /bits/ 64 <375000000>; 3348 required-opps = <&rpmhpd_opp_svs_l1>; 3349 }; 3350 3351 opp-500000000 { 3352 opp-hz = /bits/ 64 <500000000>; 3353 required-opps = <&rpmhpd_opp_nom>; 3354 }; 3355 }; 3356 }; 3357 3358 mdss_dp0: displayport-controller@ae90000 { 3359 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp"; 3360 reg = <0 0xae90000 0 0x200>, 3361 <0 0xae90200 0 0x200>, 3362 <0 0xae90400 0 0xc00>, 3363 <0 0xae91000 0 0x400>, 3364 <0 0xae91400 0 0x400>; 3365 interrupt-parent = <&mdss>; 3366 interrupts = <12>; 3367 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3368 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>, 3369 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>, 3370 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 3371 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 3372 clock-names = "core_iface", 3373 "core_aux", 3374 "ctrl_link", 3375 "ctrl_link_iface", 3376 "stream_pixel"; 3377 3378 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 3379 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 3380 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3381 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3382 3383 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 3384 phy-names = "dp"; 3385 3386 #sound-dai-cells = <0>; 3387 3388 operating-points-v2 = <&dp_opp_table>; 3389 power-domains = <&rpmhpd RPMHPD_MMCX>; 3390 3391 status = "disabled"; 3392 3393 ports { 3394 #address-cells = <1>; 3395 #size-cells = <0>; 3396 3397 port@0 { 3398 reg = <0>; 3399 mdss_dp0_in: endpoint { 3400 remote-endpoint = <&dpu_intf0_out>; 3401 }; 3402 }; 3403 3404 port@1 { 3405 reg = <1>; 3406 3407 mdss_dp0_out: endpoint { 3408 remote-endpoint = <&usb_1_qmpphy_dp_in>; 3409 }; 3410 }; 3411 }; 3412 3413 dp_opp_table: opp-table { 3414 compatible = "operating-points-v2"; 3415 3416 opp-160000000 { 3417 opp-hz = /bits/ 64 <160000000>; 3418 required-opps = <&rpmhpd_opp_low_svs>; 3419 }; 3420 3421 opp-270000000 { 3422 opp-hz = /bits/ 64 <270000000>; 3423 required-opps = <&rpmhpd_opp_svs>; 3424 }; 3425 3426 opp-540000000 { 3427 opp-hz = /bits/ 64 <540000000>; 3428 required-opps = <&rpmhpd_opp_svs_l1>; 3429 }; 3430 3431 opp-810000000 { 3432 opp-hz = /bits/ 64 <810000000>; 3433 required-opps = <&rpmhpd_opp_nom>; 3434 }; 3435 }; 3436 }; 3437 3438 mdss_dsi0: dsi@ae94000 { 3439 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3440 reg = <0 0x0ae94000 0 0x400>; 3441 reg-names = "dsi_ctrl"; 3442 3443 interrupt-parent = <&mdss>; 3444 interrupts = <4>; 3445 3446 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3447 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3448 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3449 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3450 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3451 <&gcc GCC_DISP_HF_AXI_CLK>; 3452 clock-names = "byte", 3453 "byte_intf", 3454 "pixel", 3455 "core", 3456 "iface", 3457 "bus"; 3458 3459 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3460 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 3461 3462 operating-points-v2 = <&mdss_dsi_opp_table>; 3463 power-domains = <&rpmhpd RPMHPD_MMCX>; 3464 3465 phys = <&mdss_dsi0_phy>; 3466 phy-names = "dsi"; 3467 3468 #address-cells = <1>; 3469 #size-cells = <0>; 3470 3471 status = "disabled"; 3472 3473 ports { 3474 #address-cells = <1>; 3475 #size-cells = <0>; 3476 3477 port@0 { 3478 reg = <0>; 3479 mdss_dsi0_in: endpoint { 3480 remote-endpoint = <&dpu_intf1_out>; 3481 }; 3482 }; 3483 3484 port@1 { 3485 reg = <1>; 3486 mdss_dsi0_out: endpoint { 3487 }; 3488 }; 3489 }; 3490 3491 mdss_dsi_opp_table: opp-table { 3492 compatible = "operating-points-v2"; 3493 3494 opp-187500000 { 3495 opp-hz = /bits/ 64 <187500000>; 3496 required-opps = <&rpmhpd_opp_low_svs>; 3497 }; 3498 3499 opp-300000000 { 3500 opp-hz = /bits/ 64 <300000000>; 3501 required-opps = <&rpmhpd_opp_svs>; 3502 }; 3503 3504 opp-358000000 { 3505 opp-hz = /bits/ 64 <358000000>; 3506 required-opps = <&rpmhpd_opp_svs_l1>; 3507 }; 3508 }; 3509 }; 3510 3511 mdss_dsi0_phy: phy@ae94400 { 3512 compatible = "qcom,sm8450-dsi-phy-5nm"; 3513 reg = <0 0x0ae94400 0 0x200>, 3514 <0 0x0ae94600 0 0x280>, 3515 <0 0x0ae94900 0 0x260>; 3516 reg-names = "dsi_phy", 3517 "dsi_phy_lane", 3518 "dsi_pll"; 3519 3520 #clock-cells = <1>; 3521 #phy-cells = <0>; 3522 3523 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3524 <&rpmhcc RPMH_CXO_CLK>; 3525 clock-names = "iface", "ref"; 3526 3527 status = "disabled"; 3528 }; 3529 3530 mdss_dsi1: dsi@ae96000 { 3531 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3532 reg = <0 0x0ae96000 0 0x400>; 3533 reg-names = "dsi_ctrl"; 3534 3535 interrupt-parent = <&mdss>; 3536 interrupts = <5>; 3537 3538 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3539 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3540 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3541 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3542 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3543 <&gcc GCC_DISP_HF_AXI_CLK>; 3544 clock-names = "byte", 3545 "byte_intf", 3546 "pixel", 3547 "core", 3548 "iface", 3549 "bus"; 3550 3551 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3552 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 3553 3554 operating-points-v2 = <&mdss_dsi_opp_table>; 3555 power-domains = <&rpmhpd RPMHPD_MMCX>; 3556 3557 phys = <&mdss_dsi1_phy>; 3558 phy-names = "dsi"; 3559 3560 #address-cells = <1>; 3561 #size-cells = <0>; 3562 3563 status = "disabled"; 3564 3565 ports { 3566 #address-cells = <1>; 3567 #size-cells = <0>; 3568 3569 port@0 { 3570 reg = <0>; 3571 mdss_dsi1_in: endpoint { 3572 remote-endpoint = <&dpu_intf2_out>; 3573 }; 3574 }; 3575 3576 port@1 { 3577 reg = <1>; 3578 mdss_dsi1_out: endpoint { 3579 }; 3580 }; 3581 }; 3582 }; 3583 3584 mdss_dsi1_phy: phy@ae96400 { 3585 compatible = "qcom,sm8450-dsi-phy-5nm"; 3586 reg = <0 0x0ae96400 0 0x200>, 3587 <0 0x0ae96600 0 0x280>, 3588 <0 0x0ae96900 0 0x260>; 3589 reg-names = "dsi_phy", 3590 "dsi_phy_lane", 3591 "dsi_pll"; 3592 3593 #clock-cells = <1>; 3594 #phy-cells = <0>; 3595 3596 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3597 <&rpmhcc RPMH_CXO_CLK>; 3598 clock-names = "iface", "ref"; 3599 3600 status = "disabled"; 3601 }; 3602 }; 3603 3604 dispcc: clock-controller@af00000 { 3605 compatible = "qcom,sm8450-dispcc"; 3606 reg = <0 0x0af00000 0 0x20000>; 3607 clocks = <&rpmhcc RPMH_CXO_CLK>, 3608 <&rpmhcc RPMH_CXO_CLK_A>, 3609 <&gcc GCC_DISP_AHB_CLK>, 3610 <&sleep_clk>, 3611 <&mdss_dsi0_phy 0>, 3612 <&mdss_dsi0_phy 1>, 3613 <&mdss_dsi1_phy 0>, 3614 <&mdss_dsi1_phy 1>, 3615 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3616 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 3617 <0>, /* dp1 */ 3618 <0>, 3619 <0>, /* dp2 */ 3620 <0>, 3621 <0>, /* dp3 */ 3622 <0>; 3623 power-domains = <&rpmhpd RPMHPD_MMCX>; 3624 required-opps = <&rpmhpd_opp_low_svs>; 3625 #clock-cells = <1>; 3626 #reset-cells = <1>; 3627 #power-domain-cells = <1>; 3628 }; 3629 3630 pdc: interrupt-controller@b220000 { 3631 compatible = "qcom,sm8450-pdc", "qcom,pdc"; 3632 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; 3633 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 3634 <94 609 31>, <125 63 1>, <126 716 12>; 3635 #interrupt-cells = <2>; 3636 interrupt-parent = <&intc>; 3637 interrupt-controller; 3638 }; 3639 3640 tsens0: thermal-sensor@c263000 { 3641 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3642 reg = <0 0x0c263000 0 0x1000>, /* TM */ 3643 <0 0x0c222000 0 0x1000>; /* SROT */ 3644 #qcom,sensors = <16>; 3645 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 3646 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 3647 interrupt-names = "uplow", "critical"; 3648 #thermal-sensor-cells = <1>; 3649 }; 3650 3651 tsens1: thermal-sensor@c265000 { 3652 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2"; 3653 reg = <0 0x0c265000 0 0x1000>, /* TM */ 3654 <0 0x0c223000 0 0x1000>; /* SROT */ 3655 #qcom,sensors = <16>; 3656 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 3657 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 3658 interrupt-names = "uplow", "critical"; 3659 #thermal-sensor-cells = <1>; 3660 }; 3661 3662 aoss_qmp: power-management@c300000 { 3663 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp"; 3664 reg = <0 0x0c300000 0 0x400>; 3665 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3666 IRQ_TYPE_EDGE_RISING>; 3667 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3668 3669 #clock-cells = <0>; 3670 }; 3671 3672 sram@c3f0000 { 3673 compatible = "qcom,rpmh-stats"; 3674 reg = <0 0x0c3f0000 0 0x400>; 3675 }; 3676 3677 spmi_bus: spmi@c400000 { 3678 compatible = "qcom,spmi-pmic-arb"; 3679 reg = <0 0x0c400000 0 0x00003000>, 3680 <0 0x0c500000 0 0x00400000>, 3681 <0 0x0c440000 0 0x00080000>, 3682 <0 0x0c4c0000 0 0x00010000>, 3683 <0 0x0c42d000 0 0x00010000>; 3684 reg-names = "core", 3685 "chnls", 3686 "obsrvr", 3687 "intr", 3688 "cnfg"; 3689 interrupt-names = "periph_irq"; 3690 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3691 qcom,ee = <0>; 3692 qcom,channel = <0>; 3693 interrupt-controller; 3694 #interrupt-cells = <4>; 3695 #address-cells = <2>; 3696 #size-cells = <0>; 3697 }; 3698 3699 ipcc: mailbox@ed18000 { 3700 compatible = "qcom,sm8450-ipcc", "qcom,ipcc"; 3701 reg = <0 0x0ed18000 0 0x1000>; 3702 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 3703 interrupt-controller; 3704 #interrupt-cells = <3>; 3705 #mbox-cells = <2>; 3706 }; 3707 3708 tlmm: pinctrl@f100000 { 3709 compatible = "qcom,sm8450-tlmm"; 3710 reg = <0 0x0f100000 0 0x300000>; 3711 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3712 gpio-controller; 3713 #gpio-cells = <2>; 3714 interrupt-controller; 3715 #interrupt-cells = <2>; 3716 gpio-ranges = <&tlmm 0 0 211>; 3717 wakeup-parent = <&pdc>; 3718 3719 sdc2_default_state: sdc2-default-state { 3720 clk-pins { 3721 pins = "sdc2_clk"; 3722 drive-strength = <16>; 3723 bias-disable; 3724 }; 3725 3726 cmd-pins { 3727 pins = "sdc2_cmd"; 3728 drive-strength = <16>; 3729 bias-pull-up; 3730 }; 3731 3732 data-pins { 3733 pins = "sdc2_data"; 3734 drive-strength = <16>; 3735 bias-pull-up; 3736 }; 3737 }; 3738 3739 sdc2_sleep_state: sdc2-sleep-state { 3740 clk-pins { 3741 pins = "sdc2_clk"; 3742 drive-strength = <2>; 3743 bias-disable; 3744 }; 3745 3746 cmd-pins { 3747 pins = "sdc2_cmd"; 3748 drive-strength = <2>; 3749 bias-pull-up; 3750 }; 3751 3752 data-pins { 3753 pins = "sdc2_data"; 3754 drive-strength = <2>; 3755 bias-pull-up; 3756 }; 3757 }; 3758 3759 cci0_default: cci0-default-state { 3760 /* SDA, SCL */ 3761 pins = "gpio110", "gpio111"; 3762 function = "cci_i2c"; 3763 drive-strength = <2>; 3764 bias-pull-up; 3765 }; 3766 3767 cci0_sleep: cci0-sleep-state { 3768 /* SDA, SCL */ 3769 pins = "gpio110", "gpio111"; 3770 function = "cci_i2c"; 3771 drive-strength = <2>; 3772 bias-pull-down; 3773 }; 3774 3775 cci1_default: cci1-default-state { 3776 /* SDA, SCL */ 3777 pins = "gpio112", "gpio113"; 3778 function = "cci_i2c"; 3779 drive-strength = <2>; 3780 bias-pull-up; 3781 }; 3782 3783 cci1_sleep: cci1-sleep-state { 3784 /* SDA, SCL */ 3785 pins = "gpio112", "gpio113"; 3786 function = "cci_i2c"; 3787 drive-strength = <2>; 3788 bias-pull-down; 3789 }; 3790 3791 cci2_default: cci2-default-state { 3792 /* SDA, SCL */ 3793 pins = "gpio114", "gpio115"; 3794 function = "cci_i2c"; 3795 drive-strength = <2>; 3796 bias-pull-up; 3797 }; 3798 3799 cci2_sleep: cci2-sleep-state { 3800 /* SDA, SCL */ 3801 pins = "gpio114", "gpio115"; 3802 function = "cci_i2c"; 3803 drive-strength = <2>; 3804 bias-pull-down; 3805 }; 3806 3807 cci3_default: cci3-default-state { 3808 /* SDA, SCL */ 3809 pins = "gpio208", "gpio209"; 3810 function = "cci_i2c"; 3811 drive-strength = <2>; 3812 bias-pull-up; 3813 }; 3814 3815 cci3_sleep: cci3-sleep-state { 3816 /* SDA, SCL */ 3817 pins = "gpio208", "gpio209"; 3818 function = "cci_i2c"; 3819 drive-strength = <2>; 3820 bias-pull-down; 3821 }; 3822 3823 pcie0_default_state: pcie0-default-state { 3824 perst-pins { 3825 pins = "gpio94"; 3826 function = "gpio"; 3827 drive-strength = <2>; 3828 bias-pull-down; 3829 }; 3830 3831 clkreq-pins { 3832 pins = "gpio95"; 3833 function = "pcie0_clkreqn"; 3834 drive-strength = <2>; 3835 bias-pull-up; 3836 }; 3837 3838 wake-pins { 3839 pins = "gpio96"; 3840 function = "gpio"; 3841 drive-strength = <2>; 3842 bias-pull-up; 3843 }; 3844 }; 3845 3846 pcie1_default_state: pcie1-default-state { 3847 perst-pins { 3848 pins = "gpio97"; 3849 function = "gpio"; 3850 drive-strength = <2>; 3851 bias-pull-down; 3852 }; 3853 3854 clkreq-pins { 3855 pins = "gpio98"; 3856 function = "pcie1_clkreqn"; 3857 drive-strength = <2>; 3858 bias-pull-up; 3859 }; 3860 3861 wake-pins { 3862 pins = "gpio99"; 3863 function = "gpio"; 3864 drive-strength = <2>; 3865 bias-pull-up; 3866 }; 3867 }; 3868 3869 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3870 pins = "gpio0", "gpio1"; 3871 function = "qup0"; 3872 }; 3873 3874 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3875 pins = "gpio4", "gpio5"; 3876 function = "qup1"; 3877 }; 3878 3879 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3880 pins = "gpio8", "gpio9"; 3881 function = "qup2"; 3882 }; 3883 3884 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3885 pins = "gpio12", "gpio13"; 3886 function = "qup3"; 3887 }; 3888 3889 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3890 pins = "gpio16", "gpio17"; 3891 function = "qup4"; 3892 }; 3893 3894 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3895 pins = "gpio206", "gpio207"; 3896 function = "qup5"; 3897 }; 3898 3899 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3900 pins = "gpio20", "gpio21"; 3901 function = "qup6"; 3902 }; 3903 3904 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3905 pins = "gpio28", "gpio29"; 3906 function = "qup8"; 3907 }; 3908 3909 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3910 pins = "gpio32", "gpio33"; 3911 function = "qup9"; 3912 }; 3913 3914 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3915 pins = "gpio36", "gpio37"; 3916 function = "qup10"; 3917 }; 3918 3919 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3920 pins = "gpio40", "gpio41"; 3921 function = "qup11"; 3922 }; 3923 3924 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3925 pins = "gpio44", "gpio45"; 3926 function = "qup12"; 3927 }; 3928 3929 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3930 pins = "gpio48", "gpio49"; 3931 function = "qup13"; 3932 drive-strength = <2>; 3933 bias-pull-up; 3934 }; 3935 3936 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3937 pins = "gpio52", "gpio53"; 3938 function = "qup14"; 3939 drive-strength = <2>; 3940 bias-pull-up; 3941 }; 3942 3943 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3944 pins = "gpio56", "gpio57"; 3945 function = "qup15"; 3946 }; 3947 3948 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3949 pins = "gpio60", "gpio61"; 3950 function = "qup16"; 3951 }; 3952 3953 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3954 pins = "gpio64", "gpio65"; 3955 function = "qup17"; 3956 }; 3957 3958 qup_i2c18_data_clk: qup-i2c18-data-clk-state { 3959 pins = "gpio68", "gpio69"; 3960 function = "qup18"; 3961 }; 3962 3963 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3964 pins = "gpio72", "gpio73"; 3965 function = "qup19"; 3966 }; 3967 3968 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3969 pins = "gpio76", "gpio77"; 3970 function = "qup20"; 3971 }; 3972 3973 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3974 pins = "gpio80", "gpio81"; 3975 function = "qup21"; 3976 }; 3977 3978 qup_spi0_cs: qup-spi0-cs-state { 3979 pins = "gpio3"; 3980 function = "qup0"; 3981 }; 3982 3983 qup_spi0_data_clk: qup-spi0-data-clk-state { 3984 pins = "gpio0", "gpio1", "gpio2"; 3985 function = "qup0"; 3986 }; 3987 3988 qup_spi1_cs: qup-spi1-cs-state { 3989 pins = "gpio7"; 3990 function = "qup1"; 3991 }; 3992 3993 qup_spi1_data_clk: qup-spi1-data-clk-state { 3994 pins = "gpio4", "gpio5", "gpio6"; 3995 function = "qup1"; 3996 }; 3997 3998 qup_spi2_cs: qup-spi2-cs-state { 3999 pins = "gpio11"; 4000 function = "qup2"; 4001 }; 4002 4003 qup_spi2_data_clk: qup-spi2-data-clk-state { 4004 pins = "gpio8", "gpio9", "gpio10"; 4005 function = "qup2"; 4006 }; 4007 4008 qup_spi3_cs: qup-spi3-cs-state { 4009 pins = "gpio15"; 4010 function = "qup3"; 4011 }; 4012 4013 qup_spi3_data_clk: qup-spi3-data-clk-state { 4014 pins = "gpio12", "gpio13", "gpio14"; 4015 function = "qup3"; 4016 }; 4017 4018 qup_spi4_cs: qup-spi4-cs-state { 4019 pins = "gpio19"; 4020 function = "qup4"; 4021 drive-strength = <6>; 4022 bias-disable; 4023 }; 4024 4025 qup_spi4_data_clk: qup-spi4-data-clk-state { 4026 pins = "gpio16", "gpio17", "gpio18"; 4027 function = "qup4"; 4028 }; 4029 4030 qup_spi5_cs: qup-spi5-cs-state { 4031 pins = "gpio85"; 4032 function = "qup5"; 4033 }; 4034 4035 qup_spi5_data_clk: qup-spi5-data-clk-state { 4036 pins = "gpio206", "gpio207", "gpio84"; 4037 function = "qup5"; 4038 }; 4039 4040 qup_spi6_cs: qup-spi6-cs-state { 4041 pins = "gpio23"; 4042 function = "qup6"; 4043 }; 4044 4045 qup_spi6_data_clk: qup-spi6-data-clk-state { 4046 pins = "gpio20", "gpio21", "gpio22"; 4047 function = "qup6"; 4048 }; 4049 4050 qup_spi8_cs: qup-spi8-cs-state { 4051 pins = "gpio31"; 4052 function = "qup8"; 4053 }; 4054 4055 qup_spi8_data_clk: qup-spi8-data-clk-state { 4056 pins = "gpio28", "gpio29", "gpio30"; 4057 function = "qup8"; 4058 }; 4059 4060 qup_spi9_cs: qup-spi9-cs-state { 4061 pins = "gpio35"; 4062 function = "qup9"; 4063 }; 4064 4065 qup_spi9_data_clk: qup-spi9-data-clk-state { 4066 pins = "gpio32", "gpio33", "gpio34"; 4067 function = "qup9"; 4068 }; 4069 4070 qup_spi10_cs: qup-spi10-cs-state { 4071 pins = "gpio39"; 4072 function = "qup10"; 4073 }; 4074 4075 qup_spi10_data_clk: qup-spi10-data-clk-state { 4076 pins = "gpio36", "gpio37", "gpio38"; 4077 function = "qup10"; 4078 }; 4079 4080 qup_spi11_cs: qup-spi11-cs-state { 4081 pins = "gpio43"; 4082 function = "qup11"; 4083 }; 4084 4085 qup_spi11_data_clk: qup-spi11-data-clk-state { 4086 pins = "gpio40", "gpio41", "gpio42"; 4087 function = "qup11"; 4088 }; 4089 4090 qup_spi12_cs: qup-spi12-cs-state { 4091 pins = "gpio47"; 4092 function = "qup12"; 4093 }; 4094 4095 qup_spi12_data_clk: qup-spi12-data-clk-state { 4096 pins = "gpio44", "gpio45", "gpio46"; 4097 function = "qup12"; 4098 }; 4099 4100 qup_spi13_cs: qup-spi13-cs-state { 4101 pins = "gpio51"; 4102 function = "qup13"; 4103 }; 4104 4105 qup_spi13_data_clk: qup-spi13-data-clk-state { 4106 pins = "gpio48", "gpio49", "gpio50"; 4107 function = "qup13"; 4108 }; 4109 4110 qup_spi14_cs: qup-spi14-cs-state { 4111 pins = "gpio55"; 4112 function = "qup14"; 4113 }; 4114 4115 qup_spi14_data_clk: qup-spi14-data-clk-state { 4116 pins = "gpio52", "gpio53", "gpio54"; 4117 function = "qup14"; 4118 }; 4119 4120 qup_spi15_cs: qup-spi15-cs-state { 4121 pins = "gpio59"; 4122 function = "qup15"; 4123 }; 4124 4125 qup_spi15_data_clk: qup-spi15-data-clk-state { 4126 pins = "gpio56", "gpio57", "gpio58"; 4127 function = "qup15"; 4128 }; 4129 4130 qup_spi16_cs: qup-spi16-cs-state { 4131 pins = "gpio63"; 4132 function = "qup16"; 4133 }; 4134 4135 qup_spi16_data_clk: qup-spi16-data-clk-state { 4136 pins = "gpio60", "gpio61", "gpio62"; 4137 function = "qup16"; 4138 }; 4139 4140 qup_spi17_cs: qup-spi17-cs-state { 4141 pins = "gpio67"; 4142 function = "qup17"; 4143 }; 4144 4145 qup_spi17_data_clk: qup-spi17-data-clk-state { 4146 pins = "gpio64", "gpio65", "gpio66"; 4147 function = "qup17"; 4148 }; 4149 4150 qup_spi18_cs: qup-spi18-cs-state { 4151 pins = "gpio71"; 4152 function = "qup18"; 4153 drive-strength = <6>; 4154 bias-disable; 4155 }; 4156 4157 qup_spi18_data_clk: qup-spi18-data-clk-state { 4158 pins = "gpio68", "gpio69", "gpio70"; 4159 function = "qup18"; 4160 drive-strength = <6>; 4161 bias-disable; 4162 }; 4163 4164 qup_spi19_cs: qup-spi19-cs-state { 4165 pins = "gpio75"; 4166 function = "qup19"; 4167 drive-strength = <6>; 4168 bias-disable; 4169 }; 4170 4171 qup_spi19_data_clk: qup-spi19-data-clk-state { 4172 pins = "gpio72", "gpio73", "gpio74"; 4173 function = "qup19"; 4174 drive-strength = <6>; 4175 bias-disable; 4176 }; 4177 4178 qup_spi20_cs: qup-spi20-cs-state { 4179 pins = "gpio79"; 4180 function = "qup20"; 4181 }; 4182 4183 qup_spi20_data_clk: qup-spi20-data-clk-state { 4184 pins = "gpio76", "gpio77", "gpio78"; 4185 function = "qup20"; 4186 }; 4187 4188 qup_spi21_cs: qup-spi21-cs-state { 4189 pins = "gpio83"; 4190 function = "qup21"; 4191 }; 4192 4193 qup_spi21_data_clk: qup-spi21-data-clk-state { 4194 pins = "gpio80", "gpio81", "gpio82"; 4195 function = "qup21"; 4196 }; 4197 4198 qup_uart7_rx: qup-uart7-rx-state { 4199 pins = "gpio26"; 4200 function = "qup7"; 4201 drive-strength = <2>; 4202 bias-disable; 4203 }; 4204 4205 qup_uart7_tx: qup-uart7-tx-state { 4206 pins = "gpio27"; 4207 function = "qup7"; 4208 drive-strength = <2>; 4209 bias-disable; 4210 }; 4211 4212 qup_uart20_default: qup-uart20-default-state { 4213 pins = "gpio76", "gpio77", "gpio78", "gpio79"; 4214 function = "qup20"; 4215 }; 4216 }; 4217 4218 lpass_tlmm: pinctrl@3440000 { 4219 compatible = "qcom,sm8450-lpass-lpi-pinctrl"; 4220 reg = <0 0x03440000 0x0 0x20000>, 4221 <0 0x034d0000 0x0 0x10000>; 4222 gpio-controller; 4223 #gpio-cells = <2>; 4224 gpio-ranges = <&lpass_tlmm 0 0 23>; 4225 4226 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 4227 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 4228 clock-names = "core", "audio"; 4229 4230 tx_swr_active: tx-swr-active-state { 4231 clk-pins { 4232 pins = "gpio0"; 4233 function = "swr_tx_clk"; 4234 drive-strength = <2>; 4235 slew-rate = <1>; 4236 bias-disable; 4237 }; 4238 4239 data-pins { 4240 pins = "gpio1", "gpio2", "gpio14"; 4241 function = "swr_tx_data"; 4242 drive-strength = <2>; 4243 slew-rate = <1>; 4244 bias-bus-hold; 4245 }; 4246 }; 4247 4248 rx_swr_active: rx-swr-active-state { 4249 clk-pins { 4250 pins = "gpio3"; 4251 function = "swr_rx_clk"; 4252 drive-strength = <2>; 4253 slew-rate = <1>; 4254 bias-disable; 4255 }; 4256 4257 data-pins { 4258 pins = "gpio4", "gpio5"; 4259 function = "swr_rx_data"; 4260 drive-strength = <2>; 4261 slew-rate = <1>; 4262 bias-bus-hold; 4263 }; 4264 }; 4265 4266 dmic01_default: dmic01-default-state { 4267 clk-pins { 4268 pins = "gpio6"; 4269 function = "dmic1_clk"; 4270 drive-strength = <8>; 4271 output-high; 4272 }; 4273 4274 data-pins { 4275 pins = "gpio7"; 4276 function = "dmic1_data"; 4277 drive-strength = <8>; 4278 }; 4279 }; 4280 4281 dmic23_default: dmic23-default-state { 4282 clk-pins { 4283 pins = "gpio8"; 4284 function = "dmic2_clk"; 4285 drive-strength = <8>; 4286 output-high; 4287 }; 4288 4289 data-pins { 4290 pins = "gpio9"; 4291 function = "dmic2_data"; 4292 drive-strength = <8>; 4293 }; 4294 }; 4295 4296 wsa_swr_active: wsa-swr-active-state { 4297 clk-pins { 4298 pins = "gpio10"; 4299 function = "wsa_swr_clk"; 4300 drive-strength = <2>; 4301 slew-rate = <1>; 4302 bias-disable; 4303 }; 4304 4305 data-pins { 4306 pins = "gpio11"; 4307 function = "wsa_swr_data"; 4308 drive-strength = <2>; 4309 slew-rate = <1>; 4310 bias-bus-hold; 4311 }; 4312 }; 4313 4314 wsa2_swr_active: wsa2-swr-active-state { 4315 clk-pins { 4316 pins = "gpio15"; 4317 function = "wsa2_swr_clk"; 4318 drive-strength = <2>; 4319 slew-rate = <1>; 4320 bias-disable; 4321 }; 4322 4323 data-pins { 4324 pins = "gpio16"; 4325 function = "wsa2_swr_data"; 4326 drive-strength = <2>; 4327 slew-rate = <1>; 4328 bias-bus-hold; 4329 }; 4330 }; 4331 }; 4332 4333 stm@10002000 { 4334 compatible = "arm,coresight-stm", "arm,primecell"; 4335 reg = <0x0 0x10002000 0x0 0x1000>, 4336 <0x0 0x16280000 0x0 0x180000>; 4337 reg-names = "stm-base", "stm-stimulus-base"; 4338 4339 clocks = <&aoss_qmp>; 4340 clock-names = "apb_pclk"; 4341 4342 out-ports { 4343 port { 4344 stm_out_funnel_in0: endpoint { 4345 remote-endpoint = 4346 <&funnel_in0_in_stm>; 4347 }; 4348 }; 4349 }; 4350 }; 4351 4352 funnel@10041000 { 4353 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4354 reg = <0x0 0x10041000 0x0 0x1000>; 4355 4356 clocks = <&aoss_qmp>; 4357 clock-names = "apb_pclk"; 4358 4359 in-ports { 4360 #address-cells = <1>; 4361 #size-cells = <0>; 4362 4363 port@7 { 4364 reg = <7>; 4365 funnel_in0_in_stm: endpoint { 4366 remote-endpoint = 4367 <&stm_out_funnel_in0>; 4368 }; 4369 }; 4370 }; 4371 4372 out-ports { 4373 port { 4374 funnel_in0_out_funnel_qdss: endpoint { 4375 remote-endpoint = 4376 <&funnel_qdss_in_funnel_in0>; 4377 }; 4378 }; 4379 }; 4380 }; 4381 4382 funnel@10042000 { 4383 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4384 4385 reg = <0x0 0x10042000 0x0 0x1000>; 4386 4387 clocks = <&aoss_qmp>; 4388 clock-names = "apb_pclk"; 4389 4390 in-ports { 4391 #address-cells = <1>; 4392 #size-cells = <0>; 4393 4394 port@4 { 4395 reg = <4>; 4396 funnel_in1_in_funnel_apss: endpoint { 4397 remote-endpoint = 4398 <&funnel_apss_out_funnel_in1>; 4399 }; 4400 }; 4401 4402 port@6 { 4403 reg = <6>; 4404 funnel_in1_in_funnel_dl_center: endpoint { 4405 remote-endpoint = 4406 <&funnel_dl_center_out_funnel_in1>; 4407 }; 4408 }; 4409 }; 4410 4411 out-ports { 4412 port { 4413 funnel_in1_out_funnel_qdss: endpoint { 4414 remote-endpoint = 4415 <&funnel_qdss_in_funnel_in1>; 4416 }; 4417 }; 4418 }; 4419 }; 4420 4421 funnel@10045000 { 4422 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4423 reg = <0x0 0x10045000 0x0 0x1000>; 4424 4425 clocks = <&aoss_qmp>; 4426 clock-names = "apb_pclk"; 4427 4428 in-ports { 4429 #address-cells = <1>; 4430 #size-cells = <0>; 4431 4432 port@0 { 4433 reg = <0>; 4434 funnel_qdss_in_funnel_in0: endpoint { 4435 remote-endpoint = 4436 <&funnel_in0_out_funnel_qdss>; 4437 }; 4438 }; 4439 4440 port@1 { 4441 reg = <1>; 4442 funnel_qdss_in_funnel_in1: endpoint { 4443 remote-endpoint = 4444 <&funnel_in1_out_funnel_qdss>; 4445 }; 4446 }; 4447 }; 4448 4449 out-ports { 4450 port { 4451 funnel_qdss_out_funnel_aoss: endpoint { 4452 remote-endpoint = 4453 <&funnel_aoss_in_funnel_qdss>; 4454 }; 4455 }; 4456 }; 4457 }; 4458 4459 replicator@10046000 { 4460 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4461 reg = <0x0 0x10046000 0x0 0x1000>; 4462 4463 clocks = <&aoss_qmp>; 4464 clock-names = "apb_pclk"; 4465 4466 in-ports { 4467 port { 4468 replicator_qdss_in_replicator_swao: endpoint { 4469 remote-endpoint = 4470 <&replicator_swao_out_replicator_qdss>; 4471 }; 4472 }; 4473 }; 4474 4475 out-ports { 4476 4477 port { 4478 replicator_qdss_out_replicator_etr: endpoint { 4479 remote-endpoint = 4480 <&replicator_etr_in_replicator_qdss>; 4481 }; 4482 }; 4483 }; 4484 }; 4485 4486 tmc_etr: tmc@10048000 { 4487 compatible = "arm,coresight-tmc", "arm,primecell"; 4488 reg = <0x0 0x10048000 0x0 0x1000>; 4489 4490 iommus = <&apps_smmu 0x0600 0>; 4491 arm,buffer-size = <0x10000>; 4492 4493 arm,scatter-gather; 4494 clocks = <&aoss_qmp>; 4495 clock-names = "apb_pclk"; 4496 4497 in-ports { 4498 port { 4499 tmc_etr_in_replicator_etr: endpoint { 4500 remote-endpoint = 4501 <&replicator_etr_out_tmc_etr>; 4502 }; 4503 }; 4504 }; 4505 }; 4506 4507 replicator@1004e000 { 4508 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4509 reg = <0x0 0x1004e000 0x0 0x1000>; 4510 4511 clocks = <&aoss_qmp>; 4512 clock-names = "apb_pclk"; 4513 4514 in-ports { 4515 port { 4516 replicator_etr_in_replicator_qdss: endpoint { 4517 remote-endpoint = 4518 <&replicator_qdss_out_replicator_etr>; 4519 }; 4520 }; 4521 }; 4522 4523 out-ports { 4524 4525 port { 4526 4527 replicator_etr_out_tmc_etr: endpoint { 4528 remote-endpoint = 4529 <&tmc_etr_in_replicator_etr>; 4530 }; 4531 }; 4532 }; 4533 }; 4534 4535 funnel@10b04000 { 4536 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4537 4538 reg = <0x0 0x10b04000 0x0 0x1000>; 4539 4540 clocks = <&aoss_qmp>; 4541 clock-names = "apb_pclk"; 4542 4543 in-ports { 4544 #address-cells = <1>; 4545 #size-cells = <0>; 4546 4547 port@6 { 4548 reg = <6>; 4549 funnel_aoss_in_tpda_aoss: endpoint { 4550 remote-endpoint = 4551 <&tpda_aoss_out_funnel_aoss>; 4552 }; 4553 }; 4554 4555 port@7 { 4556 reg = <7>; 4557 funnel_aoss_in_funnel_qdss: endpoint { 4558 remote-endpoint = 4559 <&funnel_qdss_out_funnel_aoss>; 4560 }; 4561 }; 4562 }; 4563 4564 out-ports { 4565 port { 4566 funnel_aoss_out_tmc_etf: endpoint { 4567 remote-endpoint = 4568 <&tmc_etf_in_funnel_aoss>; 4569 }; 4570 }; 4571 }; 4572 }; 4573 4574 tmc@10b05000 { 4575 compatible = "arm,coresight-tmc", "arm,primecell"; 4576 reg = <0x0 0x10b05000 0x0 0x1000>; 4577 4578 clocks = <&aoss_qmp>; 4579 clock-names = "apb_pclk"; 4580 4581 in-ports { 4582 port { 4583 tmc_etf_in_funnel_aoss: endpoint { 4584 remote-endpoint = 4585 <&funnel_aoss_out_tmc_etf>; 4586 }; 4587 }; 4588 }; 4589 4590 out-ports { 4591 port { 4592 tmc_etf_out_replicator_swao: endpoint { 4593 remote-endpoint = 4594 <&replicator_swao_in_tmc_etf>; 4595 }; 4596 }; 4597 }; 4598 }; 4599 4600 replicator@10b06000 { 4601 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 4602 reg = <0x0 0x10b06000 0x0 0x1000>; 4603 4604 qcom,replicator-loses-context; 4605 clocks = <&aoss_qmp>; 4606 clock-names = "apb_pclk"; 4607 4608 in-ports { 4609 port { 4610 replicator_swao_in_tmc_etf: endpoint { 4611 remote-endpoint = 4612 <&tmc_etf_out_replicator_swao>; 4613 }; 4614 }; 4615 }; 4616 4617 out-ports { 4618 4619 port { 4620 replicator_swao_out_replicator_qdss: endpoint { 4621 remote-endpoint = 4622 <&replicator_qdss_in_replicator_swao>; 4623 }; 4624 }; 4625 }; 4626 }; 4627 4628 tpda@10b08000 { 4629 compatible = "qcom,coresight-tpda", "arm,primecell"; 4630 4631 reg = <0x0 0x10b08000 0x0 0x1000>; 4632 4633 clocks = <&aoss_qmp>; 4634 clock-names = "apb_pclk"; 4635 4636 in-ports { 4637 4638 #address-cells = <1>; 4639 #size-cells = <0>; 4640 4641 port@0 { 4642 reg = <0>; 4643 tpda_aoss_in_tpdm_swao_prio_0: endpoint { 4644 remote-endpoint = 4645 <&tpdm_swao_prio_0_out_tpda_aoss>; 4646 }; 4647 }; 4648 4649 port@4 { 4650 reg = <4>; 4651 tpda_aoss_in_tpdm_swao: endpoint { 4652 remote-endpoint = 4653 <&tpdm_swao_out_tpda_aoss>; 4654 }; 4655 }; 4656 }; 4657 4658 out-ports { 4659 4660 port { 4661 tpda_aoss_out_funnel_aoss: endpoint { 4662 remote-endpoint = 4663 <&funnel_aoss_in_tpda_aoss>; 4664 }; 4665 }; 4666 }; 4667 }; 4668 4669 tpdm@10b09000 { 4670 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4671 reg = <0x0 0x10b09000 0x0 0x1000>; 4672 4673 4674 clocks = <&aoss_qmp>; 4675 clock-names = "apb_pclk"; 4676 4677 out-ports { 4678 port { 4679 tpdm_swao_prio_0_out_tpda_aoss: endpoint { 4680 remote-endpoint = 4681 <&tpda_aoss_in_tpdm_swao_prio_0>; 4682 }; 4683 }; 4684 }; 4685 }; 4686 4687 tpdm@10b0d000 { 4688 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4689 reg = <0x0 0x10b0d000 0x0 0x1000>; 4690 4691 clocks = <&aoss_qmp>; 4692 clock-names = "apb_pclk"; 4693 4694 out-ports { 4695 port { 4696 tpdm_swao_out_tpda_aoss: endpoint { 4697 remote-endpoint = 4698 <&tpda_aoss_in_tpdm_swao>; 4699 }; 4700 }; 4701 }; 4702 }; 4703 4704 tpdm@10c28000 { 4705 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4706 reg = <0x0 0x10c28000 0x0 0x1000>; 4707 4708 clocks = <&aoss_qmp>; 4709 clock-names = "apb_pclk"; 4710 4711 out-ports { 4712 port { 4713 tpdm_dlct_out_tpda_dl_center_26: endpoint { 4714 remote-endpoint = 4715 <&tpda_dl_center_26_in_tpdm_dlct>; 4716 }; 4717 }; 4718 }; 4719 }; 4720 4721 tpdm@10c29000 { 4722 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4723 reg = <0x0 0x10c29000 0x0 0x1000>; 4724 4725 clocks = <&aoss_qmp>; 4726 clock-names = "apb_pclk"; 4727 4728 out-ports { 4729 port { 4730 tpdm_ipcc_out_tpda_dl_center_27: endpoint { 4731 remote-endpoint = 4732 <&tpda_dl_center_27_in_tpdm_ipcc>; 4733 }; 4734 }; 4735 }; 4736 }; 4737 4738 cti@10c2a000 { 4739 compatible = "arm,coresight-cti", "arm,primecell"; 4740 reg = <0x0 0x10c2a000 0x0 0x1000>; 4741 4742 clocks = <&aoss_qmp>; 4743 clock-names = "apb_pclk"; 4744 }; 4745 4746 cti@10c2b000 { 4747 compatible = "arm,coresight-cti", "arm,primecell"; 4748 reg = <0x0 0x10c2b000 0x0 0x1000>; 4749 4750 clocks = <&aoss_qmp>; 4751 clock-names = "apb_pclk"; 4752 }; 4753 4754 tpda@10c2e000 { 4755 compatible = "qcom,coresight-tpda", "arm,primecell"; 4756 reg = <0x0 0x10c2e000 0x0 0x1000>; 4757 4758 clocks = <&aoss_qmp>; 4759 clock-names = "apb_pclk"; 4760 4761 in-ports { 4762 4763 #address-cells = <1>; 4764 #size-cells = <0>; 4765 4766 port@1a { 4767 reg = <26>; 4768 tpda_dl_center_26_in_tpdm_dlct: endpoint { 4769 remote-endpoint = 4770 <&tpdm_dlct_out_tpda_dl_center_26>; 4771 }; 4772 }; 4773 4774 port@1b { 4775 reg = <27>; 4776 tpda_dl_center_27_in_tpdm_ipcc: endpoint { 4777 remote-endpoint = 4778 <&tpdm_ipcc_out_tpda_dl_center_27>; 4779 }; 4780 }; 4781 }; 4782 4783 out-ports { 4784 4785 port { 4786 tpda_dl_center_out_funnel_dl_center: endpoint { 4787 remote-endpoint = 4788 <&funnel_dl_center_in_tpda_dl_center>; 4789 }; 4790 }; 4791 }; 4792 }; 4793 4794 funnel@10c2f000 { 4795 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4796 reg = <0x0 0x10c2f000 0x0 0x1000>; 4797 4798 clocks = <&aoss_qmp>; 4799 clock-names = "apb_pclk"; 4800 4801 in-ports { 4802 4803 port { 4804 funnel_dl_center_in_tpda_dl_center: endpoint { 4805 remote-endpoint = 4806 <&tpda_dl_center_out_funnel_dl_center>; 4807 }; 4808 }; 4809 }; 4810 4811 out-ports { 4812 port { 4813 funnel_dl_center_out_funnel_in1: endpoint { 4814 remote-endpoint = 4815 <&funnel_in1_in_funnel_dl_center>; 4816 }; 4817 }; 4818 }; 4819 }; 4820 4821 funnel@13810000 { 4822 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4823 4824 reg = <0x0 0x13810000 0x0 0x1000>; 4825 4826 clocks = <&aoss_qmp>; 4827 clock-names = "apb_pclk"; 4828 4829 in-ports { 4830 4831 port { 4832 funnel_apss_in_funnel_ete: endpoint { 4833 remote-endpoint = 4834 <&funnel_ete_out_funnel_apss>; 4835 }; 4836 }; 4837 }; 4838 4839 out-ports { 4840 port { 4841 funnel_apss_out_funnel_in1: endpoint { 4842 remote-endpoint = 4843 <&funnel_in1_in_funnel_apss>; 4844 }; 4845 }; 4846 }; 4847 }; 4848 4849 cti@138e0000 { 4850 compatible = "arm,coresight-cti", "arm,primecell"; 4851 reg = <0x0 0x138e0000 0x0 0x1000>; 4852 4853 clocks = <&aoss_qmp>; 4854 clock-names = "apb_pclk"; 4855 }; 4856 4857 cti@138f0000 { 4858 compatible = "arm,coresight-cti", "arm,primecell"; 4859 reg = <0x0 0x138f0000 0x0 0x1000>; 4860 4861 clocks = <&aoss_qmp>; 4862 clock-names = "apb_pclk"; 4863 }; 4864 4865 cti@13900000 { 4866 compatible = "arm,coresight-cti", "arm,primecell"; 4867 reg = <0x0 0x13900000 0x0 0x1000>; 4868 4869 clocks = <&aoss_qmp>; 4870 clock-names = "apb_pclk"; 4871 }; 4872 4873 sram@146aa000 { 4874 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd"; 4875 reg = <0 0x146aa000 0 0x1000>; 4876 ranges = <0 0 0x146aa000 0x1000>; 4877 4878 #address-cells = <1>; 4879 #size-cells = <1>; 4880 4881 pil-reloc@94c { 4882 compatible = "qcom,pil-reloc-info"; 4883 reg = <0x94c 0xc8>; 4884 }; 4885 }; 4886 4887 apps_smmu: iommu@15000000 { 4888 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500"; 4889 reg = <0 0x15000000 0 0x100000>; 4890 #iommu-cells = <2>; 4891 #global-interrupts = <1>; 4892 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4893 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4894 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4895 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4896 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4897 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4898 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4899 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4900 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4901 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4902 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4903 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4904 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4905 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4906 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4907 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4908 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4909 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4910 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4911 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4912 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4913 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4914 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4915 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4916 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4917 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4918 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4919 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4920 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4921 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4922 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4923 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4924 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4925 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4926 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4927 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4928 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4929 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4930 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4931 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4932 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4933 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4934 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4935 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4936 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4937 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4938 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4940 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4944 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4945 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4946 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4947 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4948 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4949 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4951 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4952 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4953 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4954 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4955 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4956 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4957 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4958 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4959 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4960 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 4962 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 4963 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 4964 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 4965 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 4966 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 4967 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 4968 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 4970 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 4971 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 4972 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 4976 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 4977 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 4978 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 4979 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 4980 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 4981 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 4982 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 4983 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 4984 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 4985 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 4986 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 4987 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 4988 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>; 4989 dma-coherent; 4990 }; 4991 4992 intc: interrupt-controller@17100000 { 4993 compatible = "arm,gic-v3"; 4994 #interrupt-cells = <3>; 4995 interrupt-controller; 4996 #redistributor-regions = <1>; 4997 redistributor-stride = <0x0 0x40000>; 4998 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ 4999 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ 5000 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5001 #address-cells = <2>; 5002 #size-cells = <2>; 5003 ranges; 5004 5005 gic_its: msi-controller@17140000 { 5006 compatible = "arm,gic-v3-its"; 5007 reg = <0x0 0x17140000 0x0 0x20000>; 5008 msi-controller; 5009 #msi-cells = <1>; 5010 }; 5011 }; 5012 5013 timer@17420000 { 5014 compatible = "arm,armv7-timer-mem"; 5015 #address-cells = <1>; 5016 #size-cells = <1>; 5017 ranges = <0 0 0 0x20000000>; 5018 reg = <0x0 0x17420000 0x0 0x1000>; 5019 clock-frequency = <19200000>; 5020 5021 frame@17421000 { 5022 frame-number = <0>; 5023 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5025 reg = <0x17421000 0x1000>, 5026 <0x17422000 0x1000>; 5027 }; 5028 5029 frame@17423000 { 5030 frame-number = <1>; 5031 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5032 reg = <0x17423000 0x1000>; 5033 status = "disabled"; 5034 }; 5035 5036 frame@17425000 { 5037 frame-number = <2>; 5038 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5039 reg = <0x17425000 0x1000>; 5040 status = "disabled"; 5041 }; 5042 5043 frame@17427000 { 5044 frame-number = <3>; 5045 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5046 reg = <0x17427000 0x1000>; 5047 status = "disabled"; 5048 }; 5049 5050 frame@17429000 { 5051 frame-number = <4>; 5052 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5053 reg = <0x17429000 0x1000>; 5054 status = "disabled"; 5055 }; 5056 5057 frame@1742b000 { 5058 frame-number = <5>; 5059 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5060 reg = <0x1742b000 0x1000>; 5061 status = "disabled"; 5062 }; 5063 5064 frame@1742d000 { 5065 frame-number = <6>; 5066 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5067 reg = <0x1742d000 0x1000>; 5068 status = "disabled"; 5069 }; 5070 }; 5071 5072 apps_rsc: rsc@17a00000 { 5073 label = "apps_rsc"; 5074 compatible = "qcom,rpmh-rsc"; 5075 reg = <0x0 0x17a00000 0x0 0x10000>, 5076 <0x0 0x17a10000 0x0 0x10000>, 5077 <0x0 0x17a20000 0x0 0x10000>, 5078 <0x0 0x17a30000 0x0 0x10000>; 5079 reg-names = "drv-0", "drv-1", "drv-2", "drv-3"; 5080 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5081 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5082 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5083 qcom,tcs-offset = <0xd00>; 5084 qcom,drv-id = <2>; 5085 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 5086 <WAKE_TCS 2>, <CONTROL_TCS 0>; 5087 power-domains = <&cluster_pd>; 5088 5089 apps_bcm_voter: bcm-voter { 5090 compatible = "qcom,bcm-voter"; 5091 }; 5092 5093 rpmhcc: clock-controller { 5094 compatible = "qcom,sm8450-rpmh-clk"; 5095 #clock-cells = <1>; 5096 clock-names = "xo"; 5097 clocks = <&xo_board>; 5098 }; 5099 5100 rpmhpd: power-controller { 5101 compatible = "qcom,sm8450-rpmhpd"; 5102 #power-domain-cells = <1>; 5103 operating-points-v2 = <&rpmhpd_opp_table>; 5104 5105 rpmhpd_opp_table: opp-table { 5106 compatible = "operating-points-v2"; 5107 5108 rpmhpd_opp_ret: opp1 { 5109 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5110 }; 5111 5112 rpmhpd_opp_min_svs: opp2 { 5113 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5114 }; 5115 5116 rpmhpd_opp_low_svs_d1: opp3 { 5117 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5118 }; 5119 5120 rpmhpd_opp_low_svs: opp4 { 5121 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5122 }; 5123 5124 rpmhpd_opp_low_svs_l1: opp5 { 5125 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5126 }; 5127 5128 rpmhpd_opp_svs: opp6 { 5129 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5130 }; 5131 5132 rpmhpd_opp_svs_l0: opp7 { 5133 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5134 }; 5135 5136 rpmhpd_opp_svs_l1: opp8 { 5137 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5138 }; 5139 5140 rpmhpd_opp_svs_l2: opp9 { 5141 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5142 }; 5143 5144 rpmhpd_opp_nom: opp10 { 5145 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5146 }; 5147 5148 rpmhpd_opp_nom_l1: opp11 { 5149 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5150 }; 5151 5152 rpmhpd_opp_nom_l2: opp12 { 5153 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5154 }; 5155 5156 rpmhpd_opp_turbo: opp13 { 5157 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5158 }; 5159 5160 rpmhpd_opp_turbo_l1: opp14 { 5161 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5162 }; 5163 }; 5164 }; 5165 }; 5166 5167 cpufreq_hw: cpufreq@17d91000 { 5168 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss"; 5169 reg = <0 0x17d91000 0 0x1000>, 5170 <0 0x17d92000 0 0x1000>, 5171 <0 0x17d93000 0 0x1000>; 5172 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 5173 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5174 clock-names = "xo", "alternate"; 5175 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 5176 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5177 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 5178 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 5179 #freq-domain-cells = <1>; 5180 #clock-cells = <1>; 5181 }; 5182 5183 gem_noc: interconnect@19100000 { 5184 compatible = "qcom,sm8450-gem-noc"; 5185 reg = <0 0x19100000 0 0xbb800>; 5186 #interconnect-cells = <2>; 5187 qcom,bcm-voters = <&apps_bcm_voter>; 5188 }; 5189 5190 system-cache-controller@19200000 { 5191 compatible = "qcom,sm8450-llcc"; 5192 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, 5193 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, 5194 <0 0x19a00000 0 0x80000>, <0 0x19c00000 0 0x80000>; 5195 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 5196 "llcc3_base", "llcc_broadcast_base", 5197 "llcc_broadcast_and_base"; 5198 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5199 }; 5200 5201 ufs_mem_hc: ufshc@1d84000 { 5202 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 5203 "jedec,ufs-2.0"; 5204 reg = <0 0x01d84000 0 0x3000>; 5205 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 5206 phys = <&ufs_mem_phy>; 5207 phy-names = "ufsphy"; 5208 lanes-per-direction = <2>; 5209 #reset-cells = <1>; 5210 resets = <&gcc GCC_UFS_PHY_BCR>; 5211 reset-names = "rst"; 5212 5213 power-domains = <&gcc UFS_PHY_GDSC>; 5214 5215 iommus = <&apps_smmu 0xe0 0x0>; 5216 dma-coherent; 5217 5218 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>, 5219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 5220 interconnect-names = "ufs-ddr", "cpu-ufs"; 5221 clock-names = 5222 "core_clk", 5223 "bus_aggr_clk", 5224 "iface_clk", 5225 "core_clk_unipro", 5226 "ref_clk", 5227 "tx_lane0_sync_clk", 5228 "rx_lane0_sync_clk", 5229 "rx_lane1_sync_clk"; 5230 clocks = 5231 <&gcc GCC_UFS_PHY_AXI_CLK>, 5232 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 5233 <&gcc GCC_UFS_PHY_AHB_CLK>, 5234 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 5235 <&rpmhcc RPMH_CXO_CLK>, 5236 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 5237 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 5238 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 5239 freq-table-hz = 5240 <75000000 300000000>, 5241 <0 0>, 5242 <0 0>, 5243 <75000000 300000000>, 5244 <75000000 300000000>, 5245 <0 0>, 5246 <0 0>, 5247 <0 0>; 5248 qcom,ice = <&ice>; 5249 5250 status = "disabled"; 5251 }; 5252 5253 ufs_mem_phy: phy@1d87000 { 5254 compatible = "qcom,sm8450-qmp-ufs-phy"; 5255 reg = <0 0x01d87000 0 0x1000>; 5256 5257 clock-names = "ref", "ref_aux", "qref"; 5258 clocks = <&rpmhcc RPMH_CXO_CLK>, 5259 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 5260 <&gcc GCC_UFS_0_CLKREF_EN>; 5261 5262 power-domains = <&gcc UFS_PHY_GDSC>; 5263 5264 resets = <&ufs_mem_hc 0>; 5265 reset-names = "ufsphy"; 5266 5267 #clock-cells = <1>; 5268 #phy-cells = <0>; 5269 5270 status = "disabled"; 5271 }; 5272 5273 ice: crypto@1d88000 { 5274 compatible = "qcom,sm8450-inline-crypto-engine", 5275 "qcom,inline-crypto-engine"; 5276 reg = <0 0x01d88000 0 0x8000>; 5277 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 5278 }; 5279 5280 cryptobam: dma-controller@1dc4000 { 5281 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 5282 reg = <0 0x01dc4000 0 0x28000>; 5283 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 5284 #dma-cells = <1>; 5285 qcom,ee = <0>; 5286 qcom,controlled-remotely; 5287 iommus = <&apps_smmu 0x584 0x11>, 5288 <&apps_smmu 0x588 0x0>, 5289 <&apps_smmu 0x598 0x5>, 5290 <&apps_smmu 0x59a 0x0>, 5291 <&apps_smmu 0x59f 0x0>; 5292 }; 5293 5294 crypto: crypto@1dfa000 { 5295 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce"; 5296 reg = <0 0x01dfa000 0 0x6000>; 5297 dmas = <&cryptobam 4>, <&cryptobam 5>; 5298 dma-names = "rx", "tx"; 5299 iommus = <&apps_smmu 0x584 0x11>, 5300 <&apps_smmu 0x588 0x0>, 5301 <&apps_smmu 0x598 0x5>, 5302 <&apps_smmu 0x59a 0x0>, 5303 <&apps_smmu 0x59f 0x0>; 5304 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 5305 interconnect-names = "memory"; 5306 }; 5307 5308 sdhc_2: mmc@8804000 { 5309 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5"; 5310 reg = <0 0x08804000 0 0x1000>; 5311 5312 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 5314 interrupt-names = "hc_irq", "pwr_irq"; 5315 5316 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 5317 <&gcc GCC_SDCC2_APPS_CLK>, 5318 <&rpmhcc RPMH_CXO_CLK>; 5319 clock-names = "iface", "core", "xo"; 5320 resets = <&gcc GCC_SDCC2_BCR>; 5321 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 5322 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 5323 interconnect-names = "sdhc-ddr","cpu-sdhc"; 5324 iommus = <&apps_smmu 0x4a0 0x0>; 5325 power-domains = <&rpmhpd RPMHPD_CX>; 5326 operating-points-v2 = <&sdhc2_opp_table>; 5327 bus-width = <4>; 5328 dma-coherent; 5329 5330 /* Forbid SDR104/SDR50 - broken hw! */ 5331 sdhci-caps-mask = <0x3 0x0>; 5332 5333 status = "disabled"; 5334 5335 sdhc2_opp_table: opp-table { 5336 compatible = "operating-points-v2"; 5337 5338 opp-100000000 { 5339 opp-hz = /bits/ 64 <100000000>; 5340 required-opps = <&rpmhpd_opp_low_svs>; 5341 }; 5342 5343 opp-202000000 { 5344 opp-hz = /bits/ 64 <202000000>; 5345 required-opps = <&rpmhpd_opp_svs_l1>; 5346 }; 5347 }; 5348 }; 5349 5350 usb_1: usb@a6f8800 { 5351 compatible = "qcom,sm8450-dwc3", "qcom,dwc3"; 5352 reg = <0 0x0a6f8800 0 0x400>; 5353 status = "disabled"; 5354 #address-cells = <2>; 5355 #size-cells = <2>; 5356 ranges; 5357 5358 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 5359 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 5360 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 5361 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 5362 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5363 <&gcc GCC_USB3_0_CLKREF_EN>; 5364 clock-names = "cfg_noc", 5365 "core", 5366 "iface", 5367 "sleep", 5368 "mock_utmi", 5369 "xo"; 5370 5371 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 5372 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 5373 assigned-clock-rates = <19200000>, <200000000>; 5374 5375 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 5376 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 5377 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 5378 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 5379 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 5380 interrupt-names = "pwr_event", 5381 "hs_phy_irq", 5382 "dp_hs_phy_irq", 5383 "dm_hs_phy_irq", 5384 "ss_phy_irq"; 5385 5386 power-domains = <&gcc USB30_PRIM_GDSC>; 5387 5388 resets = <&gcc GCC_USB30_PRIM_BCR>; 5389 5390 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 5391 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 5392 interconnect-names = "usb-ddr", "apps-usb"; 5393 5394 usb_1_dwc3: usb@a600000 { 5395 compatible = "snps,dwc3"; 5396 reg = <0 0x0a600000 0 0xcd00>; 5397 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 5398 iommus = <&apps_smmu 0x0 0x0>; 5399 snps,dis_u2_susphy_quirk; 5400 snps,dis_enblslpm_quirk; 5401 snps,dis-u1-entry-quirk; 5402 snps,dis-u2-entry-quirk; 5403 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 5404 phy-names = "usb2-phy", "usb3-phy"; 5405 5406 ports { 5407 #address-cells = <1>; 5408 #size-cells = <0>; 5409 5410 port@0 { 5411 reg = <0>; 5412 5413 usb_1_dwc3_hs: endpoint { 5414 }; 5415 }; 5416 5417 port@1 { 5418 reg = <1>; 5419 5420 usb_1_dwc3_ss: endpoint { 5421 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 5422 }; 5423 }; 5424 }; 5425 }; 5426 }; 5427 5428 nsp_noc: interconnect@320c0000 { 5429 compatible = "qcom,sm8450-nsp-noc"; 5430 reg = <0 0x320c0000 0 0x10000>; 5431 #interconnect-cells = <2>; 5432 qcom,bcm-voters = <&apps_bcm_voter>; 5433 }; 5434 5435 lpass_ag_noc: interconnect@3c40000 { 5436 compatible = "qcom,sm8450-lpass-ag-noc"; 5437 reg = <0 0x03c40000 0 0x17200>; 5438 #interconnect-cells = <2>; 5439 qcom,bcm-voters = <&apps_bcm_voter>; 5440 }; 5441 }; 5442 5443 sound: sound { 5444 }; 5445 5446 thermal-zones { 5447 aoss0-thermal { 5448 thermal-sensors = <&tsens0 0>; 5449 5450 trips { 5451 thermal-engine-config { 5452 temperature = <125000>; 5453 hysteresis = <1000>; 5454 type = "passive"; 5455 }; 5456 5457 reset-mon-cfg { 5458 temperature = <115000>; 5459 hysteresis = <5000>; 5460 type = "passive"; 5461 }; 5462 }; 5463 }; 5464 5465 cpuss0-thermal { 5466 thermal-sensors = <&tsens0 1>; 5467 5468 trips { 5469 thermal-engine-config { 5470 temperature = <125000>; 5471 hysteresis = <1000>; 5472 type = "passive"; 5473 }; 5474 5475 reset-mon-cfg { 5476 temperature = <115000>; 5477 hysteresis = <5000>; 5478 type = "passive"; 5479 }; 5480 }; 5481 }; 5482 5483 cpuss1-thermal { 5484 thermal-sensors = <&tsens0 2>; 5485 5486 trips { 5487 thermal-engine-config { 5488 temperature = <125000>; 5489 hysteresis = <1000>; 5490 type = "passive"; 5491 }; 5492 5493 reset-mon-cfg { 5494 temperature = <115000>; 5495 hysteresis = <5000>; 5496 type = "passive"; 5497 }; 5498 }; 5499 }; 5500 5501 cpuss3-thermal { 5502 thermal-sensors = <&tsens0 3>; 5503 5504 trips { 5505 thermal-engine-config { 5506 temperature = <125000>; 5507 hysteresis = <1000>; 5508 type = "passive"; 5509 }; 5510 5511 reset-mon-cfg { 5512 temperature = <115000>; 5513 hysteresis = <5000>; 5514 type = "passive"; 5515 }; 5516 }; 5517 }; 5518 5519 cpuss4-thermal { 5520 thermal-sensors = <&tsens0 4>; 5521 5522 trips { 5523 thermal-engine-config { 5524 temperature = <125000>; 5525 hysteresis = <1000>; 5526 type = "passive"; 5527 }; 5528 5529 reset-mon-cfg { 5530 temperature = <115000>; 5531 hysteresis = <5000>; 5532 type = "passive"; 5533 }; 5534 }; 5535 }; 5536 5537 cpu4-top-thermal { 5538 thermal-sensors = <&tsens0 5>; 5539 5540 trips { 5541 cpu4_top_alert0: trip-point0 { 5542 temperature = <90000>; 5543 hysteresis = <2000>; 5544 type = "passive"; 5545 }; 5546 5547 cpu4_top_alert1: trip-point1 { 5548 temperature = <95000>; 5549 hysteresis = <2000>; 5550 type = "passive"; 5551 }; 5552 5553 cpu4_top_crit: cpu-crit { 5554 temperature = <110000>; 5555 hysteresis = <1000>; 5556 type = "critical"; 5557 }; 5558 }; 5559 }; 5560 5561 cpu4-bottom-thermal { 5562 thermal-sensors = <&tsens0 6>; 5563 5564 trips { 5565 cpu4_bottom_alert0: trip-point0 { 5566 temperature = <90000>; 5567 hysteresis = <2000>; 5568 type = "passive"; 5569 }; 5570 5571 cpu4_bottom_alert1: trip-point1 { 5572 temperature = <95000>; 5573 hysteresis = <2000>; 5574 type = "passive"; 5575 }; 5576 5577 cpu4_bottom_crit: cpu-crit { 5578 temperature = <110000>; 5579 hysteresis = <1000>; 5580 type = "critical"; 5581 }; 5582 }; 5583 }; 5584 5585 cpu5-top-thermal { 5586 thermal-sensors = <&tsens0 7>; 5587 5588 trips { 5589 cpu5_top_alert0: trip-point0 { 5590 temperature = <90000>; 5591 hysteresis = <2000>; 5592 type = "passive"; 5593 }; 5594 5595 cpu5_top_alert1: trip-point1 { 5596 temperature = <95000>; 5597 hysteresis = <2000>; 5598 type = "passive"; 5599 }; 5600 5601 cpu5_top_crit: cpu-crit { 5602 temperature = <110000>; 5603 hysteresis = <1000>; 5604 type = "critical"; 5605 }; 5606 }; 5607 }; 5608 5609 cpu5-bottom-thermal { 5610 thermal-sensors = <&tsens0 8>; 5611 5612 trips { 5613 cpu5_bottom_alert0: trip-point0 { 5614 temperature = <90000>; 5615 hysteresis = <2000>; 5616 type = "passive"; 5617 }; 5618 5619 cpu5_bottom_alert1: trip-point1 { 5620 temperature = <95000>; 5621 hysteresis = <2000>; 5622 type = "passive"; 5623 }; 5624 5625 cpu5_bottom_crit: cpu-crit { 5626 temperature = <110000>; 5627 hysteresis = <1000>; 5628 type = "critical"; 5629 }; 5630 }; 5631 }; 5632 5633 cpu6-top-thermal { 5634 thermal-sensors = <&tsens0 9>; 5635 5636 trips { 5637 cpu6_top_alert0: trip-point0 { 5638 temperature = <90000>; 5639 hysteresis = <2000>; 5640 type = "passive"; 5641 }; 5642 5643 cpu6_top_alert1: trip-point1 { 5644 temperature = <95000>; 5645 hysteresis = <2000>; 5646 type = "passive"; 5647 }; 5648 5649 cpu6_top_crit: cpu-crit { 5650 temperature = <110000>; 5651 hysteresis = <1000>; 5652 type = "critical"; 5653 }; 5654 }; 5655 }; 5656 5657 cpu6-bottom-thermal { 5658 thermal-sensors = <&tsens0 10>; 5659 5660 trips { 5661 cpu6_bottom_alert0: trip-point0 { 5662 temperature = <90000>; 5663 hysteresis = <2000>; 5664 type = "passive"; 5665 }; 5666 5667 cpu6_bottom_alert1: trip-point1 { 5668 temperature = <95000>; 5669 hysteresis = <2000>; 5670 type = "passive"; 5671 }; 5672 5673 cpu6_bottom_crit: cpu-crit { 5674 temperature = <110000>; 5675 hysteresis = <1000>; 5676 type = "critical"; 5677 }; 5678 }; 5679 }; 5680 5681 cpu7-top-thermal { 5682 thermal-sensors = <&tsens0 11>; 5683 5684 trips { 5685 cpu7_top_alert0: trip-point0 { 5686 temperature = <90000>; 5687 hysteresis = <2000>; 5688 type = "passive"; 5689 }; 5690 5691 cpu7_top_alert1: trip-point1 { 5692 temperature = <95000>; 5693 hysteresis = <2000>; 5694 type = "passive"; 5695 }; 5696 5697 cpu7_top_crit: cpu-crit { 5698 temperature = <110000>; 5699 hysteresis = <1000>; 5700 type = "critical"; 5701 }; 5702 }; 5703 }; 5704 5705 cpu7-middle-thermal { 5706 thermal-sensors = <&tsens0 12>; 5707 5708 trips { 5709 cpu7_middle_alert0: trip-point0 { 5710 temperature = <90000>; 5711 hysteresis = <2000>; 5712 type = "passive"; 5713 }; 5714 5715 cpu7_middle_alert1: trip-point1 { 5716 temperature = <95000>; 5717 hysteresis = <2000>; 5718 type = "passive"; 5719 }; 5720 5721 cpu7_middle_crit: cpu-crit { 5722 temperature = <110000>; 5723 hysteresis = <1000>; 5724 type = "critical"; 5725 }; 5726 }; 5727 }; 5728 5729 cpu7-bottom-thermal { 5730 thermal-sensors = <&tsens0 13>; 5731 5732 trips { 5733 cpu7_bottom_alert0: trip-point0 { 5734 temperature = <90000>; 5735 hysteresis = <2000>; 5736 type = "passive"; 5737 }; 5738 5739 cpu7_bottom_alert1: trip-point1 { 5740 temperature = <95000>; 5741 hysteresis = <2000>; 5742 type = "passive"; 5743 }; 5744 5745 cpu7_bottom_crit: cpu-crit { 5746 temperature = <110000>; 5747 hysteresis = <1000>; 5748 type = "critical"; 5749 }; 5750 }; 5751 }; 5752 5753 gpu-top-thermal { 5754 polling-delay-passive = <10>; 5755 5756 thermal-sensors = <&tsens0 14>; 5757 5758 cooling-maps { 5759 map0 { 5760 trip = <&gpu_top_alert0>; 5761 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5762 }; 5763 }; 5764 5765 trips { 5766 gpu_top_alert0: trip-point0 { 5767 temperature = <85000>; 5768 hysteresis = <1000>; 5769 type = "passive"; 5770 }; 5771 5772 trip-point1 { 5773 temperature = <90000>; 5774 hysteresis = <1000>; 5775 type = "hot"; 5776 }; 5777 5778 trip-point2 { 5779 temperature = <110000>; 5780 hysteresis = <1000>; 5781 type = "critical"; 5782 }; 5783 }; 5784 }; 5785 5786 gpu-bottom-thermal { 5787 polling-delay-passive = <10>; 5788 5789 thermal-sensors = <&tsens0 15>; 5790 5791 cooling-maps { 5792 map0 { 5793 trip = <&gpu_bottom_alert0>; 5794 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 5795 }; 5796 }; 5797 5798 trips { 5799 gpu_bottom_alert0: trip-point0 { 5800 temperature = <85000>; 5801 hysteresis = <1000>; 5802 type = "passive"; 5803 }; 5804 5805 trip-point1 { 5806 temperature = <90000>; 5807 hysteresis = <1000>; 5808 type = "hot"; 5809 }; 5810 5811 trip-point2 { 5812 temperature = <110000>; 5813 hysteresis = <1000>; 5814 type = "critical"; 5815 }; 5816 }; 5817 }; 5818 5819 aoss1-thermal { 5820 thermal-sensors = <&tsens1 0>; 5821 5822 trips { 5823 thermal-engine-config { 5824 temperature = <125000>; 5825 hysteresis = <1000>; 5826 type = "passive"; 5827 }; 5828 5829 reset-mon-cfg { 5830 temperature = <115000>; 5831 hysteresis = <5000>; 5832 type = "passive"; 5833 }; 5834 }; 5835 }; 5836 5837 cpu0-thermal { 5838 thermal-sensors = <&tsens1 1>; 5839 5840 trips { 5841 cpu0_alert0: trip-point0 { 5842 temperature = <90000>; 5843 hysteresis = <2000>; 5844 type = "passive"; 5845 }; 5846 5847 cpu0_alert1: trip-point1 { 5848 temperature = <95000>; 5849 hysteresis = <2000>; 5850 type = "passive"; 5851 }; 5852 5853 cpu0_crit: cpu-crit { 5854 temperature = <110000>; 5855 hysteresis = <1000>; 5856 type = "critical"; 5857 }; 5858 }; 5859 }; 5860 5861 cpu1-thermal { 5862 thermal-sensors = <&tsens1 2>; 5863 5864 trips { 5865 cpu1_alert0: trip-point0 { 5866 temperature = <90000>; 5867 hysteresis = <2000>; 5868 type = "passive"; 5869 }; 5870 5871 cpu1_alert1: trip-point1 { 5872 temperature = <95000>; 5873 hysteresis = <2000>; 5874 type = "passive"; 5875 }; 5876 5877 cpu1_crit: cpu-crit { 5878 temperature = <110000>; 5879 hysteresis = <1000>; 5880 type = "critical"; 5881 }; 5882 }; 5883 }; 5884 5885 cpu2-thermal { 5886 thermal-sensors = <&tsens1 3>; 5887 5888 trips { 5889 cpu2_alert0: trip-point0 { 5890 temperature = <90000>; 5891 hysteresis = <2000>; 5892 type = "passive"; 5893 }; 5894 5895 cpu2_alert1: trip-point1 { 5896 temperature = <95000>; 5897 hysteresis = <2000>; 5898 type = "passive"; 5899 }; 5900 5901 cpu2_crit: cpu-crit { 5902 temperature = <110000>; 5903 hysteresis = <1000>; 5904 type = "critical"; 5905 }; 5906 }; 5907 }; 5908 5909 cpu3-thermal { 5910 thermal-sensors = <&tsens1 4>; 5911 5912 trips { 5913 cpu3_alert0: trip-point0 { 5914 temperature = <90000>; 5915 hysteresis = <2000>; 5916 type = "passive"; 5917 }; 5918 5919 cpu3_alert1: trip-point1 { 5920 temperature = <95000>; 5921 hysteresis = <2000>; 5922 type = "passive"; 5923 }; 5924 5925 cpu3_crit: cpu-crit { 5926 temperature = <110000>; 5927 hysteresis = <1000>; 5928 type = "critical"; 5929 }; 5930 }; 5931 }; 5932 5933 cdsp0-thermal { 5934 polling-delay-passive = <10>; 5935 5936 thermal-sensors = <&tsens1 5>; 5937 5938 trips { 5939 thermal-engine-config { 5940 temperature = <125000>; 5941 hysteresis = <1000>; 5942 type = "passive"; 5943 }; 5944 5945 thermal-hal-config { 5946 temperature = <125000>; 5947 hysteresis = <1000>; 5948 type = "passive"; 5949 }; 5950 5951 reset-mon-cfg { 5952 temperature = <115000>; 5953 hysteresis = <5000>; 5954 type = "passive"; 5955 }; 5956 5957 cdsp_0_config: junction-config { 5958 temperature = <95000>; 5959 hysteresis = <5000>; 5960 type = "passive"; 5961 }; 5962 }; 5963 }; 5964 5965 cdsp1-thermal { 5966 polling-delay-passive = <10>; 5967 5968 thermal-sensors = <&tsens1 6>; 5969 5970 trips { 5971 thermal-engine-config { 5972 temperature = <125000>; 5973 hysteresis = <1000>; 5974 type = "passive"; 5975 }; 5976 5977 thermal-hal-config { 5978 temperature = <125000>; 5979 hysteresis = <1000>; 5980 type = "passive"; 5981 }; 5982 5983 reset-mon-cfg { 5984 temperature = <115000>; 5985 hysteresis = <5000>; 5986 type = "passive"; 5987 }; 5988 5989 cdsp_1_config: junction-config { 5990 temperature = <95000>; 5991 hysteresis = <5000>; 5992 type = "passive"; 5993 }; 5994 }; 5995 }; 5996 5997 cdsp2-thermal { 5998 polling-delay-passive = <10>; 5999 6000 thermal-sensors = <&tsens1 7>; 6001 6002 trips { 6003 thermal-engine-config { 6004 temperature = <125000>; 6005 hysteresis = <1000>; 6006 type = "passive"; 6007 }; 6008 6009 thermal-hal-config { 6010 temperature = <125000>; 6011 hysteresis = <1000>; 6012 type = "passive"; 6013 }; 6014 6015 reset-mon-cfg { 6016 temperature = <115000>; 6017 hysteresis = <5000>; 6018 type = "passive"; 6019 }; 6020 6021 cdsp_2_config: junction-config { 6022 temperature = <95000>; 6023 hysteresis = <5000>; 6024 type = "passive"; 6025 }; 6026 }; 6027 }; 6028 6029 video-thermal { 6030 thermal-sensors = <&tsens1 8>; 6031 6032 trips { 6033 thermal-engine-config { 6034 temperature = <125000>; 6035 hysteresis = <1000>; 6036 type = "passive"; 6037 }; 6038 6039 reset-mon-cfg { 6040 temperature = <115000>; 6041 hysteresis = <5000>; 6042 type = "passive"; 6043 }; 6044 }; 6045 }; 6046 6047 mem-thermal { 6048 polling-delay-passive = <10>; 6049 6050 thermal-sensors = <&tsens1 9>; 6051 6052 trips { 6053 thermal-engine-config { 6054 temperature = <125000>; 6055 hysteresis = <1000>; 6056 type = "passive"; 6057 }; 6058 6059 ddr_config0: ddr0-config { 6060 temperature = <90000>; 6061 hysteresis = <5000>; 6062 type = "passive"; 6063 }; 6064 6065 reset-mon-cfg { 6066 temperature = <115000>; 6067 hysteresis = <5000>; 6068 type = "passive"; 6069 }; 6070 }; 6071 }; 6072 6073 modem0-thermal { 6074 thermal-sensors = <&tsens1 10>; 6075 6076 trips { 6077 thermal-engine-config { 6078 temperature = <125000>; 6079 hysteresis = <1000>; 6080 type = "passive"; 6081 }; 6082 6083 mdmss0_config0: mdmss0-config0 { 6084 temperature = <102000>; 6085 hysteresis = <3000>; 6086 type = "passive"; 6087 }; 6088 6089 mdmss0_config1: mdmss0-config1 { 6090 temperature = <105000>; 6091 hysteresis = <3000>; 6092 type = "passive"; 6093 }; 6094 6095 reset-mon-cfg { 6096 temperature = <115000>; 6097 hysteresis = <5000>; 6098 type = "passive"; 6099 }; 6100 }; 6101 }; 6102 6103 modem1-thermal { 6104 thermal-sensors = <&tsens1 11>; 6105 6106 trips { 6107 thermal-engine-config { 6108 temperature = <125000>; 6109 hysteresis = <1000>; 6110 type = "passive"; 6111 }; 6112 6113 mdmss1_config0: mdmss1-config0 { 6114 temperature = <102000>; 6115 hysteresis = <3000>; 6116 type = "passive"; 6117 }; 6118 6119 mdmss1_config1: mdmss1-config1 { 6120 temperature = <105000>; 6121 hysteresis = <3000>; 6122 type = "passive"; 6123 }; 6124 6125 reset-mon-cfg { 6126 temperature = <115000>; 6127 hysteresis = <5000>; 6128 type = "passive"; 6129 }; 6130 }; 6131 }; 6132 6133 modem2-thermal { 6134 thermal-sensors = <&tsens1 12>; 6135 6136 trips { 6137 thermal-engine-config { 6138 temperature = <125000>; 6139 hysteresis = <1000>; 6140 type = "passive"; 6141 }; 6142 6143 mdmss2_config0: mdmss2-config0 { 6144 temperature = <102000>; 6145 hysteresis = <3000>; 6146 type = "passive"; 6147 }; 6148 6149 mdmss2_config1: mdmss2-config1 { 6150 temperature = <105000>; 6151 hysteresis = <3000>; 6152 type = "passive"; 6153 }; 6154 6155 reset-mon-cfg { 6156 temperature = <115000>; 6157 hysteresis = <5000>; 6158 type = "passive"; 6159 }; 6160 }; 6161 }; 6162 6163 modem3-thermal { 6164 thermal-sensors = <&tsens1 13>; 6165 6166 trips { 6167 thermal-engine-config { 6168 temperature = <125000>; 6169 hysteresis = <1000>; 6170 type = "passive"; 6171 }; 6172 6173 mdmss3_config0: mdmss3-config0 { 6174 temperature = <102000>; 6175 hysteresis = <3000>; 6176 type = "passive"; 6177 }; 6178 6179 mdmss3_config1: mdmss3-config1 { 6180 temperature = <105000>; 6181 hysteresis = <3000>; 6182 type = "passive"; 6183 }; 6184 6185 reset-mon-cfg { 6186 temperature = <115000>; 6187 hysteresis = <5000>; 6188 type = "passive"; 6189 }; 6190 }; 6191 }; 6192 6193 camera0-thermal { 6194 thermal-sensors = <&tsens1 14>; 6195 6196 trips { 6197 thermal-engine-config { 6198 temperature = <125000>; 6199 hysteresis = <1000>; 6200 type = "passive"; 6201 }; 6202 6203 reset-mon-cfg { 6204 temperature = <115000>; 6205 hysteresis = <5000>; 6206 type = "passive"; 6207 }; 6208 }; 6209 }; 6210 6211 camera1-thermal { 6212 thermal-sensors = <&tsens1 15>; 6213 6214 trips { 6215 thermal-engine-config { 6216 temperature = <125000>; 6217 hysteresis = <1000>; 6218 type = "passive"; 6219 }; 6220 6221 reset-mon-cfg { 6222 temperature = <115000>; 6223 hysteresis = <5000>; 6224 type = "passive"; 6225 }; 6226 }; 6227 }; 6228 }; 6229 6230 timer { 6231 compatible = "arm,armv8-timer"; 6232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6236 clock-frequency = <19200000>; 6237 }; 6238}; 6239