1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Linaro Limited 4 */ 5 6#include <dt-bindings/interconnect/qcom,sm8350.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/clock/qcom,dispcc-sm8350.h> 9#include <dt-bindings/clock/qcom,gcc-sm8350.h> 10#include <dt-bindings/clock/qcom,gpucc-sm8350.h> 11#include <dt-bindings/clock/qcom,rpmh.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,icc.h> 16#include <dt-bindings/interconnect/qcom,sm8350.h> 17#include <dt-bindings/mailbox/qcom-ipcc.h> 18#include <dt-bindings/phy/phy-qcom-qmp.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/power/qcom,rpmhpd.h> 21#include <dt-bindings/soc/qcom,apr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/sound/qcom,q6afe.h> 24#include <dt-bindings/thermal/thermal.h> 25#include <dt-bindings/interconnect/qcom,sm8350.h> 26 27/ { 28 interrupt-parent = <&intc>; 29 30 #address-cells = <2>; 31 #size-cells = <2>; 32 33 chosen { }; 34 35 clocks { 36 xo_board: xo-board { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <38400000>; 40 clock-output-names = "xo_board"; 41 }; 42 43 sleep_clk: sleep-clk { 44 compatible = "fixed-clock"; 45 clock-frequency = <32764>; 46 #clock-cells = <0>; 47 }; 48 }; 49 50 cpus { 51 #address-cells = <2>; 52 #size-cells = <0>; 53 54 cpu0: cpu@0 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a55"; 57 reg = <0x0 0x0>; 58 clocks = <&cpufreq_hw 0>; 59 enable-method = "psci"; 60 next-level-cache = <&l2_0>; 61 qcom,freq-domain = <&cpufreq_hw 0>; 62 power-domains = <&cpu_pd0>; 63 power-domain-names = "psci"; 64 #cooling-cells = <2>; 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 l3_0: l3-cache { 71 compatible = "cache"; 72 cache-level = <3>; 73 cache-unified; 74 }; 75 }; 76 }; 77 78 cpu1: cpu@100 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a55"; 81 reg = <0x0 0x100>; 82 clocks = <&cpufreq_hw 0>; 83 enable-method = "psci"; 84 next-level-cache = <&l2_100>; 85 qcom,freq-domain = <&cpufreq_hw 0>; 86 power-domains = <&cpu_pd1>; 87 power-domain-names = "psci"; 88 #cooling-cells = <2>; 89 l2_100: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 next-level-cache = <&l3_0>; 94 }; 95 }; 96 97 cpu2: cpu@200 { 98 device_type = "cpu"; 99 compatible = "arm,cortex-a55"; 100 reg = <0x0 0x200>; 101 clocks = <&cpufreq_hw 0>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_200>; 104 qcom,freq-domain = <&cpufreq_hw 0>; 105 power-domains = <&cpu_pd2>; 106 power-domain-names = "psci"; 107 #cooling-cells = <2>; 108 l2_200: l2-cache { 109 compatible = "cache"; 110 cache-level = <2>; 111 cache-unified; 112 next-level-cache = <&l3_0>; 113 }; 114 }; 115 116 cpu3: cpu@300 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a55"; 119 reg = <0x0 0x300>; 120 clocks = <&cpufreq_hw 0>; 121 enable-method = "psci"; 122 next-level-cache = <&l2_300>; 123 qcom,freq-domain = <&cpufreq_hw 0>; 124 power-domains = <&cpu_pd3>; 125 power-domain-names = "psci"; 126 #cooling-cells = <2>; 127 l2_300: l2-cache { 128 compatible = "cache"; 129 cache-level = <2>; 130 cache-unified; 131 next-level-cache = <&l3_0>; 132 }; 133 }; 134 135 cpu4: cpu@400 { 136 device_type = "cpu"; 137 compatible = "arm,cortex-a78"; 138 reg = <0x0 0x400>; 139 clocks = <&cpufreq_hw 1>; 140 enable-method = "psci"; 141 next-level-cache = <&l2_400>; 142 qcom,freq-domain = <&cpufreq_hw 1>; 143 power-domains = <&cpu_pd4>; 144 power-domain-names = "psci"; 145 #cooling-cells = <2>; 146 l2_400: l2-cache { 147 compatible = "cache"; 148 cache-level = <2>; 149 cache-unified; 150 next-level-cache = <&l3_0>; 151 }; 152 }; 153 154 cpu5: cpu@500 { 155 device_type = "cpu"; 156 compatible = "arm,cortex-a78"; 157 reg = <0x0 0x500>; 158 clocks = <&cpufreq_hw 1>; 159 enable-method = "psci"; 160 next-level-cache = <&l2_500>; 161 qcom,freq-domain = <&cpufreq_hw 1>; 162 power-domains = <&cpu_pd5>; 163 power-domain-names = "psci"; 164 #cooling-cells = <2>; 165 l2_500: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&l3_0>; 170 }; 171 }; 172 173 cpu6: cpu@600 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a78"; 176 reg = <0x0 0x600>; 177 clocks = <&cpufreq_hw 1>; 178 enable-method = "psci"; 179 next-level-cache = <&l2_600>; 180 qcom,freq-domain = <&cpufreq_hw 1>; 181 power-domains = <&cpu_pd6>; 182 power-domain-names = "psci"; 183 #cooling-cells = <2>; 184 l2_600: l2-cache { 185 compatible = "cache"; 186 cache-level = <2>; 187 cache-unified; 188 next-level-cache = <&l3_0>; 189 }; 190 }; 191 192 cpu7: cpu@700 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-x1"; 195 reg = <0x0 0x700>; 196 clocks = <&cpufreq_hw 2>; 197 enable-method = "psci"; 198 next-level-cache = <&l2_700>; 199 qcom,freq-domain = <&cpufreq_hw 2>; 200 power-domains = <&cpu_pd7>; 201 power-domain-names = "psci"; 202 #cooling-cells = <2>; 203 l2_700: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&l3_0>; 208 }; 209 }; 210 211 cpu-map { 212 cluster0 { 213 core0 { 214 cpu = <&cpu0>; 215 }; 216 217 core1 { 218 cpu = <&cpu1>; 219 }; 220 221 core2 { 222 cpu = <&cpu2>; 223 }; 224 225 core3 { 226 cpu = <&cpu3>; 227 }; 228 229 core4 { 230 cpu = <&cpu4>; 231 }; 232 233 core5 { 234 cpu = <&cpu5>; 235 }; 236 237 core6 { 238 cpu = <&cpu6>; 239 }; 240 241 core7 { 242 cpu = <&cpu7>; 243 }; 244 }; 245 }; 246 247 idle-states { 248 entry-method = "psci"; 249 250 little_cpu_sleep_0: cpu-sleep-0-0 { 251 compatible = "arm,idle-state"; 252 idle-state-name = "silver-rail-power-collapse"; 253 arm,psci-suspend-param = <0x40000004>; 254 entry-latency-us = <360>; 255 exit-latency-us = <531>; 256 min-residency-us = <3934>; 257 local-timer-stop; 258 }; 259 260 big_cpu_sleep_0: cpu-sleep-1-0 { 261 compatible = "arm,idle-state"; 262 idle-state-name = "gold-rail-power-collapse"; 263 arm,psci-suspend-param = <0x40000004>; 264 entry-latency-us = <702>; 265 exit-latency-us = <1061>; 266 min-residency-us = <4488>; 267 local-timer-stop; 268 }; 269 }; 270 271 domain-idle-states { 272 cluster_sleep_apss_off: cluster-sleep-0 { 273 compatible = "domain-idle-state"; 274 arm,psci-suspend-param = <0x41000044>; 275 entry-latency-us = <2752>; 276 exit-latency-us = <3048>; 277 min-residency-us = <6118>; 278 }; 279 280 cluster_sleep_aoss_sleep: cluster-sleep-1 { 281 compatible = "domain-idle-state"; 282 arm,psci-suspend-param = <0x4100c344>; 283 entry-latency-us = <3263>; 284 exit-latency-us = <6562>; 285 min-residency-us = <9987>; 286 }; 287 }; 288 }; 289 290 firmware { 291 scm: scm { 292 compatible = "qcom,scm-sm8350", "qcom,scm"; 293 qcom,dload-mode = <&tcsr 0x13000>; 294 #reset-cells = <1>; 295 }; 296 }; 297 298 memory@80000000 { 299 device_type = "memory"; 300 /* We expect the bootloader to fill in the size */ 301 reg = <0x0 0x80000000 0x0 0x0>; 302 }; 303 304 pmu-a55 { 305 compatible = "arm,cortex-a55-pmu"; 306 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 307 }; 308 309 pmu-a78 { 310 compatible = "arm,cortex-a78-pmu"; 311 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 312 }; 313 314 pmu-x1 { 315 compatible = "arm,cortex-x1-pmu"; 316 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 317 }; 318 319 psci { 320 compatible = "arm,psci-1.0"; 321 method = "smc"; 322 323 cpu_pd0: power-domain-cpu0 { 324 #power-domain-cells = <0>; 325 power-domains = <&cluster_pd>; 326 domain-idle-states = <&little_cpu_sleep_0>; 327 }; 328 329 cpu_pd1: power-domain-cpu1 { 330 #power-domain-cells = <0>; 331 power-domains = <&cluster_pd>; 332 domain-idle-states = <&little_cpu_sleep_0>; 333 }; 334 335 cpu_pd2: power-domain-cpu2 { 336 #power-domain-cells = <0>; 337 power-domains = <&cluster_pd>; 338 domain-idle-states = <&little_cpu_sleep_0>; 339 }; 340 341 cpu_pd3: power-domain-cpu3 { 342 #power-domain-cells = <0>; 343 power-domains = <&cluster_pd>; 344 domain-idle-states = <&little_cpu_sleep_0>; 345 }; 346 347 cpu_pd4: power-domain-cpu4 { 348 #power-domain-cells = <0>; 349 power-domains = <&cluster_pd>; 350 domain-idle-states = <&big_cpu_sleep_0>; 351 }; 352 353 cpu_pd5: power-domain-cpu5 { 354 #power-domain-cells = <0>; 355 power-domains = <&cluster_pd>; 356 domain-idle-states = <&big_cpu_sleep_0>; 357 }; 358 359 cpu_pd6: power-domain-cpu6 { 360 #power-domain-cells = <0>; 361 power-domains = <&cluster_pd>; 362 domain-idle-states = <&big_cpu_sleep_0>; 363 }; 364 365 cpu_pd7: power-domain-cpu7 { 366 #power-domain-cells = <0>; 367 power-domains = <&cluster_pd>; 368 domain-idle-states = <&big_cpu_sleep_0>; 369 }; 370 371 cluster_pd: power-domain-cpu-cluster0 { 372 #power-domain-cells = <0>; 373 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_aoss_sleep>; 374 }; 375 }; 376 377 qup_opp_table_100mhz: opp-table-qup100mhz { 378 compatible = "operating-points-v2"; 379 380 opp-50000000 { 381 opp-hz = /bits/ 64 <50000000>; 382 required-opps = <&rpmhpd_opp_min_svs>; 383 }; 384 385 opp-75000000 { 386 opp-hz = /bits/ 64 <75000000>; 387 required-opps = <&rpmhpd_opp_low_svs>; 388 }; 389 390 opp-100000000 { 391 opp-hz = /bits/ 64 <100000000>; 392 required-opps = <&rpmhpd_opp_svs>; 393 }; 394 }; 395 396 qup_opp_table_120mhz: opp-table-qup120mhz { 397 compatible = "operating-points-v2"; 398 399 opp-50000000 { 400 opp-hz = /bits/ 64 <50000000>; 401 required-opps = <&rpmhpd_opp_min_svs>; 402 }; 403 404 opp-75000000 { 405 opp-hz = /bits/ 64 <75000000>; 406 required-opps = <&rpmhpd_opp_low_svs>; 407 }; 408 409 opp-120000000 { 410 opp-hz = /bits/ 64 <120000000>; 411 required-opps = <&rpmhpd_opp_svs>; 412 }; 413 }; 414 415 reserved_memory: reserved-memory { 416 #address-cells = <2>; 417 #size-cells = <2>; 418 ranges; 419 420 hyp_mem: memory@80000000 { 421 reg = <0x0 0x80000000 0x0 0x600000>; 422 no-map; 423 }; 424 425 xbl_aop_mem: memory@80700000 { 426 no-map; 427 reg = <0x0 0x80700000 0x0 0x160000>; 428 }; 429 430 cmd_db: memory@80860000 { 431 compatible = "qcom,cmd-db"; 432 reg = <0x0 0x80860000 0x0 0x20000>; 433 no-map; 434 }; 435 436 reserved_xbl_uefi_log: memory@80880000 { 437 reg = <0x0 0x80880000 0x0 0x14000>; 438 no-map; 439 }; 440 441 smem@80900000 { 442 compatible = "qcom,smem"; 443 reg = <0x0 0x80900000 0x0 0x200000>; 444 hwlocks = <&tcsr_mutex 3>; 445 no-map; 446 }; 447 448 cpucp_fw_mem: memory@80b00000 { 449 reg = <0x0 0x80b00000 0x0 0x100000>; 450 no-map; 451 }; 452 453 cdsp_secure_heap: memory@80c00000 { 454 reg = <0x0 0x80c00000 0x0 0x4600000>; 455 no-map; 456 }; 457 458 pil_camera_mem: mmeory@85200000 { 459 reg = <0x0 0x85200000 0x0 0x500000>; 460 no-map; 461 }; 462 463 pil_video_mem: memory@85700000 { 464 reg = <0x0 0x85700000 0x0 0x500000>; 465 no-map; 466 }; 467 468 pil_cvp_mem: memory@85c00000 { 469 reg = <0x0 0x85c00000 0x0 0x500000>; 470 no-map; 471 }; 472 473 pil_adsp_mem: memory@86100000 { 474 reg = <0x0 0x86100000 0x0 0x2100000>; 475 no-map; 476 }; 477 478 pil_slpi_mem: memory@88200000 { 479 reg = <0x0 0x88200000 0x0 0x1500000>; 480 no-map; 481 }; 482 483 pil_cdsp_mem: memory@89700000 { 484 reg = <0x0 0x89700000 0x0 0x1e00000>; 485 no-map; 486 }; 487 488 pil_ipa_fw_mem: memory@8b500000 { 489 reg = <0x0 0x8b500000 0x0 0x10000>; 490 no-map; 491 }; 492 493 pil_ipa_gsi_mem: memory@8b510000 { 494 reg = <0x0 0x8b510000 0x0 0xa000>; 495 no-map; 496 }; 497 498 pil_gpu_mem: memory@8b51a000 { 499 reg = <0x0 0x8b51a000 0x0 0x2000>; 500 no-map; 501 }; 502 503 pil_spss_mem: memory@8b600000 { 504 reg = <0x0 0x8b600000 0x0 0x100000>; 505 no-map; 506 }; 507 508 pil_modem_mem: memory@8b800000 { 509 reg = <0x0 0x8b800000 0x0 0x10000000>; 510 no-map; 511 }; 512 513 rmtfs_mem: memory@9b800000 { 514 compatible = "qcom,rmtfs-mem"; 515 reg = <0x0 0x9b800000 0x0 0x280000>; 516 no-map; 517 518 qcom,client-id = <1>; 519 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 520 }; 521 522 hyp_reserved_mem: memory@d0000000 { 523 reg = <0x0 0xd0000000 0x0 0x800000>; 524 no-map; 525 }; 526 527 pil_trustedvm_mem: memory@d0800000 { 528 reg = <0x0 0xd0800000 0x0 0x76f7000>; 529 no-map; 530 }; 531 532 qrtr_shbuf: memory@d7ef7000 { 533 reg = <0x0 0xd7ef7000 0x0 0x9000>; 534 no-map; 535 }; 536 537 chan0_shbuf: memory@d7f00000 { 538 reg = <0x0 0xd7f00000 0x0 0x80000>; 539 no-map; 540 }; 541 542 chan1_shbuf: memory@d7f80000 { 543 reg = <0x0 0xd7f80000 0x0 0x80000>; 544 no-map; 545 }; 546 547 removed_mem: memory@d8800000 { 548 reg = <0x0 0xd8800000 0x0 0x6800000>; 549 no-map; 550 }; 551 }; 552 553 smp2p-adsp { 554 compatible = "qcom,smp2p"; 555 qcom,smem = <443>, <429>; 556 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 557 IPCC_MPROC_SIGNAL_SMP2P 558 IRQ_TYPE_EDGE_RISING>; 559 mboxes = <&ipcc IPCC_CLIENT_LPASS 560 IPCC_MPROC_SIGNAL_SMP2P>; 561 562 qcom,local-pid = <0>; 563 qcom,remote-pid = <2>; 564 565 smp2p_adsp_out: master-kernel { 566 qcom,entry-name = "master-kernel"; 567 #qcom,smem-state-cells = <1>; 568 }; 569 570 smp2p_adsp_in: slave-kernel { 571 qcom,entry-name = "slave-kernel"; 572 interrupt-controller; 573 #interrupt-cells = <2>; 574 }; 575 }; 576 577 smp2p-cdsp { 578 compatible = "qcom,smp2p"; 579 qcom,smem = <94>, <432>; 580 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 581 IPCC_MPROC_SIGNAL_SMP2P 582 IRQ_TYPE_EDGE_RISING>; 583 mboxes = <&ipcc IPCC_CLIENT_CDSP 584 IPCC_MPROC_SIGNAL_SMP2P>; 585 586 qcom,local-pid = <0>; 587 qcom,remote-pid = <5>; 588 589 smp2p_cdsp_out: master-kernel { 590 qcom,entry-name = "master-kernel"; 591 #qcom,smem-state-cells = <1>; 592 }; 593 594 smp2p_cdsp_in: slave-kernel { 595 qcom,entry-name = "slave-kernel"; 596 interrupt-controller; 597 #interrupt-cells = <2>; 598 }; 599 }; 600 601 smp2p-modem { 602 compatible = "qcom,smp2p"; 603 qcom,smem = <435>, <428>; 604 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 605 IPCC_MPROC_SIGNAL_SMP2P 606 IRQ_TYPE_EDGE_RISING>; 607 mboxes = <&ipcc IPCC_CLIENT_MPSS 608 IPCC_MPROC_SIGNAL_SMP2P>; 609 610 qcom,local-pid = <0>; 611 qcom,remote-pid = <1>; 612 613 smp2p_modem_out: master-kernel { 614 qcom,entry-name = "master-kernel"; 615 #qcom,smem-state-cells = <1>; 616 }; 617 618 smp2p_modem_in: slave-kernel { 619 qcom,entry-name = "slave-kernel"; 620 interrupt-controller; 621 #interrupt-cells = <2>; 622 }; 623 624 ipa_smp2p_out: ipa-ap-to-modem { 625 qcom,entry-name = "ipa"; 626 #qcom,smem-state-cells = <1>; 627 }; 628 629 ipa_smp2p_in: ipa-modem-to-ap { 630 qcom,entry-name = "ipa"; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-slpi { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <481>, <430>; 639 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 640 IPCC_MPROC_SIGNAL_SMP2P 641 IRQ_TYPE_EDGE_RISING>; 642 mboxes = <&ipcc IPCC_CLIENT_SLPI 643 IPCC_MPROC_SIGNAL_SMP2P>; 644 645 qcom,local-pid = <0>; 646 qcom,remote-pid = <3>; 647 648 smp2p_slpi_out: master-kernel { 649 qcom,entry-name = "master-kernel"; 650 #qcom,smem-state-cells = <1>; 651 }; 652 653 smp2p_slpi_in: slave-kernel { 654 qcom,entry-name = "slave-kernel"; 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 soc: soc@0 { 661 #address-cells = <2>; 662 #size-cells = <2>; 663 ranges = <0 0 0 0 0x10 0>; 664 dma-ranges = <0 0 0 0 0x10 0>; 665 compatible = "simple-bus"; 666 667 gcc: clock-controller@100000 { 668 compatible = "qcom,gcc-sm8350"; 669 reg = <0x0 0x00100000 0x0 0x1f0000>; 670 #clock-cells = <1>; 671 #reset-cells = <1>; 672 #power-domain-cells = <1>; 673 clock-names = "bi_tcxo", 674 "sleep_clk", 675 "pcie_0_pipe_clk", 676 "pcie_1_pipe_clk", 677 "ufs_card_rx_symbol_0_clk", 678 "ufs_card_rx_symbol_1_clk", 679 "ufs_card_tx_symbol_0_clk", 680 "ufs_phy_rx_symbol_0_clk", 681 "ufs_phy_rx_symbol_1_clk", 682 "ufs_phy_tx_symbol_0_clk", 683 "usb3_phy_wrapper_gcc_usb30_pipe_clk", 684 "usb3_uni_phy_sec_gcc_usb30_pipe_clk"; 685 clocks = <&rpmhcc RPMH_CXO_CLK>, 686 <&sleep_clk>, 687 <&pcie0_phy>, 688 <&pcie1_phy>, 689 <0>, 690 <0>, 691 <0>, 692 <&ufs_mem_phy 0>, 693 <&ufs_mem_phy 1>, 694 <&ufs_mem_phy 2>, 695 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 696 <0>; 697 }; 698 699 ipcc: mailbox@408000 { 700 compatible = "qcom,sm8350-ipcc", "qcom,ipcc"; 701 reg = <0 0x00408000 0 0x1000>; 702 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 703 interrupt-controller; 704 #interrupt-cells = <3>; 705 #mbox-cells = <2>; 706 }; 707 708 gpi_dma2: dma-controller@800000 { 709 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 710 reg = <0 0x00800000 0 0x60000>; 711 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 723 dma-channels = <12>; 724 dma-channel-mask = <0xff>; 725 iommus = <&apps_smmu 0x5f6 0x0>; 726 #dma-cells = <3>; 727 status = "disabled"; 728 }; 729 730 qupv3_id_2: geniqup@8c0000 { 731 compatible = "qcom,geni-se-qup"; 732 reg = <0x0 0x008c0000 0x0 0x6000>; 733 clock-names = "m-ahb", "s-ahb"; 734 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 735 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 736 iommus = <&apps_smmu 0x5e3 0x0>; 737 #address-cells = <2>; 738 #size-cells = <2>; 739 ranges; 740 status = "disabled"; 741 742 i2c14: i2c@880000 { 743 compatible = "qcom,geni-i2c"; 744 reg = <0 0x00880000 0 0x4000>; 745 clock-names = "se"; 746 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 747 pinctrl-names = "default"; 748 pinctrl-0 = <&qup_i2c14_default>; 749 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 750 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 751 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 752 dma-names = "tx", "rx"; 753 #address-cells = <1>; 754 #size-cells = <0>; 755 status = "disabled"; 756 }; 757 758 spi14: spi@880000 { 759 compatible = "qcom,geni-spi"; 760 reg = <0 0x00880000 0 0x4000>; 761 clock-names = "se"; 762 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 763 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 764 power-domains = <&rpmhpd RPMHPD_CX>; 765 operating-points-v2 = <&qup_opp_table_120mhz>; 766 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 767 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 768 dma-names = "tx", "rx"; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 status = "disabled"; 772 }; 773 774 i2c15: i2c@884000 { 775 compatible = "qcom,geni-i2c"; 776 reg = <0 0x00884000 0 0x4000>; 777 clock-names = "se"; 778 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 779 pinctrl-names = "default"; 780 pinctrl-0 = <&qup_i2c15_default>; 781 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 782 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 783 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 784 dma-names = "tx", "rx"; 785 #address-cells = <1>; 786 #size-cells = <0>; 787 status = "disabled"; 788 }; 789 790 spi15: spi@884000 { 791 compatible = "qcom,geni-spi"; 792 reg = <0 0x00884000 0 0x4000>; 793 clock-names = "se"; 794 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 795 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 796 power-domains = <&rpmhpd RPMHPD_CX>; 797 operating-points-v2 = <&qup_opp_table_120mhz>; 798 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 799 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 800 dma-names = "tx", "rx"; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 i2c16: i2c@888000 { 807 compatible = "qcom,geni-i2c"; 808 reg = <0 0x00888000 0 0x4000>; 809 clock-names = "se"; 810 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 811 pinctrl-names = "default"; 812 pinctrl-0 = <&qup_i2c16_default>; 813 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 814 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 815 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 816 dma-names = "tx", "rx"; 817 #address-cells = <1>; 818 #size-cells = <0>; 819 status = "disabled"; 820 }; 821 822 spi16: spi@888000 { 823 compatible = "qcom,geni-spi"; 824 reg = <0 0x00888000 0 0x4000>; 825 clock-names = "se"; 826 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 827 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 828 power-domains = <&rpmhpd RPMHPD_CX>; 829 operating-points-v2 = <&qup_opp_table_100mhz>; 830 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 831 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 832 dma-names = "tx", "rx"; 833 #address-cells = <1>; 834 #size-cells = <0>; 835 status = "disabled"; 836 }; 837 838 i2c17: i2c@88c000 { 839 compatible = "qcom,geni-i2c"; 840 reg = <0 0x0088c000 0 0x4000>; 841 clock-names = "se"; 842 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 843 pinctrl-names = "default"; 844 pinctrl-0 = <&qup_i2c17_default>; 845 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 846 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 847 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 848 dma-names = "tx", "rx"; 849 #address-cells = <1>; 850 #size-cells = <0>; 851 status = "disabled"; 852 }; 853 854 spi17: spi@88c000 { 855 compatible = "qcom,geni-spi"; 856 reg = <0 0x0088c000 0 0x4000>; 857 clock-names = "se"; 858 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 859 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 860 power-domains = <&rpmhpd RPMHPD_CX>; 861 operating-points-v2 = <&qup_opp_table_100mhz>; 862 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 863 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 864 dma-names = "tx", "rx"; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 status = "disabled"; 868 }; 869 870 /* QUP no. 18 seems to be strictly SPI/UART-only */ 871 872 spi18: spi@890000 { 873 compatible = "qcom,geni-spi"; 874 reg = <0 0x00890000 0 0x4000>; 875 clock-names = "se"; 876 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 877 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 878 power-domains = <&rpmhpd RPMHPD_CX>; 879 operating-points-v2 = <&qup_opp_table_100mhz>; 880 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 881 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 882 dma-names = "tx", "rx"; 883 #address-cells = <1>; 884 #size-cells = <0>; 885 status = "disabled"; 886 }; 887 888 uart18: serial@890000 { 889 compatible = "qcom,geni-uart"; 890 reg = <0 0x00890000 0 0x4000>; 891 clock-names = "se"; 892 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 893 pinctrl-names = "default"; 894 pinctrl-0 = <&qup_uart18_default>; 895 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 896 power-domains = <&rpmhpd RPMHPD_CX>; 897 operating-points-v2 = <&qup_opp_table_100mhz>; 898 status = "disabled"; 899 }; 900 901 i2c19: i2c@894000 { 902 compatible = "qcom,geni-i2c"; 903 reg = <0 0x00894000 0 0x4000>; 904 clock-names = "se"; 905 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 906 pinctrl-names = "default"; 907 pinctrl-0 = <&qup_i2c19_default>; 908 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 909 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 910 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 911 dma-names = "tx", "rx"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 status = "disabled"; 915 }; 916 917 spi19: spi@894000 { 918 compatible = "qcom,geni-spi"; 919 reg = <0 0x00894000 0 0x4000>; 920 clock-names = "se"; 921 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 922 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 923 power-domains = <&rpmhpd RPMHPD_CX>; 924 operating-points-v2 = <&qup_opp_table_100mhz>; 925 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 926 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 927 dma-names = "tx", "rx"; 928 #address-cells = <1>; 929 #size-cells = <0>; 930 status = "disabled"; 931 }; 932 }; 933 934 gpi_dma0: dma-controller@900000 { 935 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 936 reg = <0 0x00900000 0 0x60000>; 937 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 949 dma-channels = <12>; 950 dma-channel-mask = <0x7e>; 951 iommus = <&apps_smmu 0x5b6 0x0>; 952 #dma-cells = <3>; 953 status = "disabled"; 954 }; 955 956 qupv3_id_0: geniqup@9c0000 { 957 compatible = "qcom,geni-se-qup"; 958 reg = <0x0 0x009c0000 0x0 0x6000>; 959 clock-names = "m-ahb", "s-ahb"; 960 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 961 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 962 iommus = <&apps_smmu 0x5a3 0>; 963 #address-cells = <2>; 964 #size-cells = <2>; 965 ranges; 966 status = "disabled"; 967 968 i2c0: i2c@980000 { 969 compatible = "qcom,geni-i2c"; 970 reg = <0 0x00980000 0 0x4000>; 971 clock-names = "se"; 972 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 973 pinctrl-names = "default"; 974 pinctrl-0 = <&qup_i2c0_default>; 975 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 976 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 977 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 978 dma-names = "tx", "rx"; 979 #address-cells = <1>; 980 #size-cells = <0>; 981 status = "disabled"; 982 }; 983 984 spi0: spi@980000 { 985 compatible = "qcom,geni-spi"; 986 reg = <0 0x00980000 0 0x4000>; 987 clock-names = "se"; 988 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 989 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 990 power-domains = <&rpmhpd RPMHPD_CX>; 991 operating-points-v2 = <&qup_opp_table_100mhz>; 992 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 993 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 994 dma-names = "tx", "rx"; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 i2c1: i2c@984000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0 0x00984000 0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c1_default>; 1007 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1008 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1009 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1010 dma-names = "tx", "rx"; 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 status = "disabled"; 1014 }; 1015 1016 spi1: spi@984000 { 1017 compatible = "qcom,geni-spi"; 1018 reg = <0 0x00984000 0 0x4000>; 1019 clock-names = "se"; 1020 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1021 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1022 power-domains = <&rpmhpd RPMHPD_CX>; 1023 operating-points-v2 = <&qup_opp_table_100mhz>; 1024 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1025 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1026 dma-names = "tx", "rx"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 status = "disabled"; 1030 }; 1031 1032 i2c2: i2c@988000 { 1033 compatible = "qcom,geni-i2c"; 1034 reg = <0 0x00988000 0 0x4000>; 1035 clock-names = "se"; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1037 pinctrl-names = "default"; 1038 pinctrl-0 = <&qup_i2c2_default>; 1039 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1040 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1041 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1042 dma-names = "tx", "rx"; 1043 #address-cells = <1>; 1044 #size-cells = <0>; 1045 status = "disabled"; 1046 }; 1047 1048 spi2: spi@988000 { 1049 compatible = "qcom,geni-spi"; 1050 reg = <0 0x00988000 0 0x4000>; 1051 clock-names = "se"; 1052 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1053 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1054 power-domains = <&rpmhpd RPMHPD_CX>; 1055 operating-points-v2 = <&qup_opp_table_100mhz>; 1056 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1057 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1058 dma-names = "tx", "rx"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 uart2: serial@98c000 { 1065 compatible = "qcom,geni-debug-uart"; 1066 reg = <0 0x0098c000 0 0x4000>; 1067 clock-names = "se"; 1068 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1069 pinctrl-names = "default"; 1070 pinctrl-0 = <&qup_uart3_default_state>; 1071 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 operating-points-v2 = <&qup_opp_table_100mhz>; 1074 status = "disabled"; 1075 }; 1076 1077 /* QUP no. 3 seems to be strictly SPI-only */ 1078 1079 spi3: spi@98c000 { 1080 compatible = "qcom,geni-spi"; 1081 reg = <0 0x0098c000 0 0x4000>; 1082 clock-names = "se"; 1083 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1084 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1085 power-domains = <&rpmhpd RPMHPD_CX>; 1086 operating-points-v2 = <&qup_opp_table_100mhz>; 1087 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1088 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1089 dma-names = "tx", "rx"; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 status = "disabled"; 1093 }; 1094 1095 i2c4: i2c@990000 { 1096 compatible = "qcom,geni-i2c"; 1097 reg = <0 0x00990000 0 0x4000>; 1098 clock-names = "se"; 1099 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&qup_i2c4_default>; 1102 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1103 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1104 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1105 dma-names = "tx", "rx"; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 spi4: spi@990000 { 1112 compatible = "qcom,geni-spi"; 1113 reg = <0 0x00990000 0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1116 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1117 power-domains = <&rpmhpd RPMHPD_CX>; 1118 operating-points-v2 = <&qup_opp_table_100mhz>; 1119 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1120 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1121 dma-names = "tx", "rx"; 1122 #address-cells = <1>; 1123 #size-cells = <0>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c5: i2c@994000 { 1128 compatible = "qcom,geni-i2c"; 1129 reg = <0 0x00994000 0 0x4000>; 1130 clock-names = "se"; 1131 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1132 pinctrl-names = "default"; 1133 pinctrl-0 = <&qup_i2c5_default>; 1134 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1135 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1136 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1137 dma-names = "tx", "rx"; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 status = "disabled"; 1141 }; 1142 1143 spi5: spi@994000 { 1144 compatible = "qcom,geni-spi"; 1145 reg = <0 0x00994000 0 0x4000>; 1146 clock-names = "se"; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1148 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1149 power-domains = <&rpmhpd RPMHPD_CX>; 1150 operating-points-v2 = <&qup_opp_table_100mhz>; 1151 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1152 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 #address-cells = <1>; 1155 #size-cells = <0>; 1156 status = "disabled"; 1157 }; 1158 1159 i2c6: i2c@998000 { 1160 compatible = "qcom,geni-i2c"; 1161 reg = <0 0x00998000 0 0x4000>; 1162 clock-names = "se"; 1163 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1164 pinctrl-names = "default"; 1165 pinctrl-0 = <&qup_i2c6_default>; 1166 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1167 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1168 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1169 dma-names = "tx", "rx"; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 spi6: spi@998000 { 1176 compatible = "qcom,geni-spi"; 1177 reg = <0 0x00998000 0 0x4000>; 1178 clock-names = "se"; 1179 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1180 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1181 power-domains = <&rpmhpd RPMHPD_CX>; 1182 operating-points-v2 = <&qup_opp_table_100mhz>; 1183 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1184 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1185 dma-names = "tx", "rx"; 1186 #address-cells = <1>; 1187 #size-cells = <0>; 1188 status = "disabled"; 1189 }; 1190 1191 uart6: serial@998000 { 1192 compatible = "qcom,geni-uart"; 1193 reg = <0 0x00998000 0 0x4000>; 1194 clock-names = "se"; 1195 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&qup_uart6_default>; 1198 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1199 power-domains = <&rpmhpd RPMHPD_CX>; 1200 operating-points-v2 = <&qup_opp_table_100mhz>; 1201 status = "disabled"; 1202 }; 1203 1204 i2c7: i2c@99c000 { 1205 compatible = "qcom,geni-i2c"; 1206 reg = <0 0x0099c000 0 0x4000>; 1207 clock-names = "se"; 1208 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1209 pinctrl-names = "default"; 1210 pinctrl-0 = <&qup_i2c7_default>; 1211 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1212 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1213 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1214 dma-names = "tx", "rx"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 status = "disabled"; 1218 }; 1219 1220 spi7: spi@99c000 { 1221 compatible = "qcom,geni-spi"; 1222 reg = <0 0x0099c000 0 0x4000>; 1223 clock-names = "se"; 1224 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1225 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1226 power-domains = <&rpmhpd RPMHPD_CX>; 1227 operating-points-v2 = <&qup_opp_table_100mhz>; 1228 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1229 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1230 dma-names = "tx", "rx"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 status = "disabled"; 1234 }; 1235 }; 1236 1237 gpi_dma1: dma-controller@a00000 { 1238 compatible = "qcom,sm8350-gpi-dma", "qcom,sm6350-gpi-dma"; 1239 reg = <0 0x00a00000 0 0x60000>; 1240 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1247 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1248 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1249 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1250 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1251 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1252 dma-channels = <12>; 1253 dma-channel-mask = <0xff>; 1254 iommus = <&apps_smmu 0x56 0x0>; 1255 #dma-cells = <3>; 1256 status = "disabled"; 1257 }; 1258 1259 qupv3_id_1: geniqup@ac0000 { 1260 compatible = "qcom,geni-se-qup"; 1261 reg = <0x0 0x00ac0000 0x0 0x6000>; 1262 clock-names = "m-ahb", "s-ahb"; 1263 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1264 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1265 iommus = <&apps_smmu 0x43 0>; 1266 #address-cells = <2>; 1267 #size-cells = <2>; 1268 ranges; 1269 status = "disabled"; 1270 1271 i2c8: i2c@a80000 { 1272 compatible = "qcom,geni-i2c"; 1273 reg = <0 0x00a80000 0 0x4000>; 1274 clock-names = "se"; 1275 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&qup_i2c8_default>; 1278 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1279 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1280 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1281 dma-names = "tx", "rx"; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 status = "disabled"; 1285 }; 1286 1287 spi8: spi@a80000 { 1288 compatible = "qcom,geni-spi"; 1289 reg = <0 0x00a80000 0 0x4000>; 1290 clock-names = "se"; 1291 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1292 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1293 power-domains = <&rpmhpd RPMHPD_CX>; 1294 operating-points-v2 = <&qup_opp_table_120mhz>; 1295 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1296 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1297 dma-names = "tx", "rx"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 i2c9: i2c@a84000 { 1304 compatible = "qcom,geni-i2c"; 1305 reg = <0 0x00a84000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1308 pinctrl-names = "default"; 1309 pinctrl-0 = <&qup_i2c9_default>; 1310 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1311 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1312 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1313 dma-names = "tx", "rx"; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 spi9: spi@a84000 { 1320 compatible = "qcom,geni-spi"; 1321 reg = <0 0x00a84000 0 0x4000>; 1322 clock-names = "se"; 1323 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1324 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1325 power-domains = <&rpmhpd RPMHPD_CX>; 1326 operating-points-v2 = <&qup_opp_table_100mhz>; 1327 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1328 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1329 dma-names = "tx", "rx"; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 i2c10: i2c@a88000 { 1336 compatible = "qcom,geni-i2c"; 1337 reg = <0 0x00a88000 0 0x4000>; 1338 clock-names = "se"; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_i2c10_default>; 1342 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1343 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1344 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1345 dma-names = "tx", "rx"; 1346 #address-cells = <1>; 1347 #size-cells = <0>; 1348 status = "disabled"; 1349 }; 1350 1351 spi10: spi@a88000 { 1352 compatible = "qcom,geni-spi"; 1353 reg = <0 0x00a88000 0 0x4000>; 1354 clock-names = "se"; 1355 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1356 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1357 power-domains = <&rpmhpd RPMHPD_CX>; 1358 operating-points-v2 = <&qup_opp_table_100mhz>; 1359 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1360 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1361 dma-names = "tx", "rx"; 1362 #address-cells = <1>; 1363 #size-cells = <0>; 1364 status = "disabled"; 1365 }; 1366 1367 i2c11: i2c@a8c000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0 0x00a8c000 0 0x4000>; 1370 clock-names = "se"; 1371 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1372 pinctrl-names = "default"; 1373 pinctrl-0 = <&qup_i2c11_default>; 1374 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1375 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1376 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1377 dma-names = "tx", "rx"; 1378 #address-cells = <1>; 1379 #size-cells = <0>; 1380 status = "disabled"; 1381 }; 1382 1383 spi11: spi@a8c000 { 1384 compatible = "qcom,geni-spi"; 1385 reg = <0 0x00a8c000 0 0x4000>; 1386 clock-names = "se"; 1387 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1388 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1389 power-domains = <&rpmhpd RPMHPD_CX>; 1390 operating-points-v2 = <&qup_opp_table_100mhz>; 1391 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1392 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 status = "disabled"; 1397 }; 1398 1399 i2c12: i2c@a90000 { 1400 compatible = "qcom,geni-i2c"; 1401 reg = <0 0x00a90000 0 0x4000>; 1402 clock-names = "se"; 1403 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1404 pinctrl-names = "default"; 1405 pinctrl-0 = <&qup_i2c12_default>; 1406 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1407 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1408 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1409 dma-names = "tx", "rx"; 1410 #address-cells = <1>; 1411 #size-cells = <0>; 1412 status = "disabled"; 1413 }; 1414 1415 spi12: spi@a90000 { 1416 compatible = "qcom,geni-spi"; 1417 reg = <0 0x00a90000 0 0x4000>; 1418 clock-names = "se"; 1419 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1420 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1421 power-domains = <&rpmhpd RPMHPD_CX>; 1422 operating-points-v2 = <&qup_opp_table_100mhz>; 1423 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1424 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1425 dma-names = "tx", "rx"; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 status = "disabled"; 1429 }; 1430 1431 i2c13: i2c@a94000 { 1432 compatible = "qcom,geni-i2c"; 1433 reg = <0 0x00a94000 0 0x4000>; 1434 clock-names = "se"; 1435 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1436 pinctrl-names = "default"; 1437 pinctrl-0 = <&qup_i2c13_default>; 1438 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1439 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1440 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1441 dma-names = "tx", "rx"; 1442 #address-cells = <1>; 1443 #size-cells = <0>; 1444 status = "disabled"; 1445 }; 1446 1447 spi13: spi@a94000 { 1448 compatible = "qcom,geni-spi"; 1449 reg = <0 0x00a94000 0 0x4000>; 1450 clock-names = "se"; 1451 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1452 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1453 power-domains = <&rpmhpd RPMHPD_CX>; 1454 operating-points-v2 = <&qup_opp_table_100mhz>; 1455 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1456 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1457 dma-names = "tx", "rx"; 1458 #address-cells = <1>; 1459 #size-cells = <0>; 1460 status = "disabled"; 1461 }; 1462 }; 1463 1464 rng: rng@10d3000 { 1465 compatible = "qcom,prng-ee"; 1466 reg = <0 0x010d3000 0 0x1000>; 1467 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1468 clock-names = "core"; 1469 }; 1470 1471 config_noc: interconnect@1500000 { 1472 compatible = "qcom,sm8350-config-noc"; 1473 reg = <0 0x01500000 0 0xa580>; 1474 #interconnect-cells = <2>; 1475 qcom,bcm-voters = <&apps_bcm_voter>; 1476 }; 1477 1478 mc_virt: interconnect@1580000 { 1479 compatible = "qcom,sm8350-mc-virt"; 1480 reg = <0 0x01580000 0 0x1000>; 1481 #interconnect-cells = <2>; 1482 qcom,bcm-voters = <&apps_bcm_voter>; 1483 }; 1484 1485 system_noc: interconnect@1680000 { 1486 compatible = "qcom,sm8350-system-noc"; 1487 reg = <0 0x01680000 0 0x1c200>; 1488 #interconnect-cells = <2>; 1489 qcom,bcm-voters = <&apps_bcm_voter>; 1490 }; 1491 1492 aggre1_noc: interconnect@16e0000 { 1493 compatible = "qcom,sm8350-aggre1-noc"; 1494 reg = <0 0x016e0000 0 0x1f180>; 1495 #interconnect-cells = <2>; 1496 qcom,bcm-voters = <&apps_bcm_voter>; 1497 }; 1498 1499 aggre2_noc: interconnect@1700000 { 1500 compatible = "qcom,sm8350-aggre2-noc"; 1501 reg = <0 0x01700000 0 0x33000>; 1502 #interconnect-cells = <2>; 1503 qcom,bcm-voters = <&apps_bcm_voter>; 1504 }; 1505 1506 mmss_noc: interconnect@1740000 { 1507 compatible = "qcom,sm8350-mmss-noc"; 1508 reg = <0 0x01740000 0 0x1f080>; 1509 #interconnect-cells = <2>; 1510 qcom,bcm-voters = <&apps_bcm_voter>; 1511 }; 1512 1513 pcie0: pcie@1c00000 { 1514 compatible = "qcom,pcie-sm8350"; 1515 reg = <0 0x01c00000 0 0x3000>, 1516 <0 0x60000000 0 0xf1d>, 1517 <0 0x60000f20 0 0xa8>, 1518 <0 0x60001000 0 0x1000>, 1519 <0 0x60100000 0 0x100000>; 1520 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1521 device_type = "pci"; 1522 linux,pci-domain = <0>; 1523 bus-range = <0x00 0xff>; 1524 num-lanes = <1>; 1525 1526 #address-cells = <3>; 1527 #size-cells = <2>; 1528 1529 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 1530 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 1531 1532 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1533 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1534 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1536 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1537 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1538 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1539 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "msi0", 1541 "msi1", 1542 "msi2", 1543 "msi3", 1544 "msi4", 1545 "msi5", 1546 "msi6", 1547 "msi7"; 1548 #interrupt-cells = <1>; 1549 interrupt-map-mask = <0 0 0 0x7>; 1550 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1551 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1552 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1553 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1554 1555 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1556 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1557 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1558 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1559 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 1560 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1561 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1562 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, 1563 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 1564 clock-names = "aux", 1565 "cfg", 1566 "bus_master", 1567 "bus_slave", 1568 "slave_q2a", 1569 "tbu", 1570 "ddrss_sf_tbu", 1571 "aggre1", 1572 "aggre0"; 1573 1574 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 1575 <0x100 &apps_smmu 0x1c01 0x1>; 1576 1577 resets = <&gcc GCC_PCIE_0_BCR>; 1578 reset-names = "pci"; 1579 1580 power-domains = <&gcc PCIE_0_GDSC>; 1581 1582 phys = <&pcie0_phy>; 1583 phy-names = "pciephy"; 1584 1585 status = "disabled"; 1586 1587 pcie@0 { 1588 device_type = "pci"; 1589 reg = <0x0 0x0 0x0 0x0 0x0>; 1590 bus-range = <0x01 0xff>; 1591 1592 #address-cells = <3>; 1593 #size-cells = <2>; 1594 ranges; 1595 }; 1596 }; 1597 1598 pcie0_phy: phy@1c06000 { 1599 compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy"; 1600 reg = <0 0x01c06000 0 0x2000>; 1601 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 1602 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1603 <&gcc GCC_PCIE_0_CLKREF_EN>, 1604 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 1605 <&gcc GCC_PCIE_0_PIPE_CLK>; 1606 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1607 1608 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1609 reset-names = "phy"; 1610 1611 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 1612 assigned-clock-rates = <100000000>; 1613 1614 #clock-cells = <0>; 1615 clock-output-names = "pcie_0_pipe_clk"; 1616 1617 #phy-cells = <0>; 1618 1619 status = "disabled"; 1620 }; 1621 1622 pcie1: pcie@1c08000 { 1623 compatible = "qcom,pcie-sm8350"; 1624 reg = <0 0x01c08000 0 0x3000>, 1625 <0 0x40000000 0 0xf1d>, 1626 <0 0x40000f20 0 0xa8>, 1627 <0 0x40001000 0 0x1000>, 1628 <0 0x40100000 0 0x100000>; 1629 reg-names = "parf", "dbi", "elbi", "atu", "config"; 1630 device_type = "pci"; 1631 linux,pci-domain = <1>; 1632 bus-range = <0x00 0xff>; 1633 num-lanes = <2>; 1634 1635 #address-cells = <3>; 1636 #size-cells = <2>; 1637 1638 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1639 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1640 1641 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 1649 interrupt-names = "msi0", 1650 "msi1", 1651 "msi2", 1652 "msi3", 1653 "msi4", 1654 "msi5", 1655 "msi6", 1656 "msi7"; 1657 #interrupt-cells = <1>; 1658 interrupt-map-mask = <0 0 0 0x7>; 1659 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1660 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1661 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1662 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1663 1664 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1665 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1666 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 1667 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 1668 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 1669 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 1670 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1671 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 1672 clock-names = "aux", 1673 "cfg", 1674 "bus_master", 1675 "bus_slave", 1676 "slave_q2a", 1677 "tbu", 1678 "ddrss_sf_tbu", 1679 "aggre1"; 1680 1681 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 1682 <0x100 &apps_smmu 0x1c81 0x1>; 1683 1684 resets = <&gcc GCC_PCIE_1_BCR>; 1685 reset-names = "pci"; 1686 1687 power-domains = <&gcc PCIE_1_GDSC>; 1688 1689 phys = <&pcie1_phy>; 1690 phy-names = "pciephy"; 1691 1692 status = "disabled"; 1693 1694 pcie@0 { 1695 device_type = "pci"; 1696 reg = <0x0 0x0 0x0 0x0 0x0>; 1697 bus-range = <0x01 0xff>; 1698 1699 #address-cells = <3>; 1700 #size-cells = <2>; 1701 ranges; 1702 }; 1703 }; 1704 1705 pcie1_phy: phy@1c0e000 { 1706 compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy"; 1707 reg = <0 0x01c0e000 0 0x2000>; 1708 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 1709 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 1710 <&gcc GCC_PCIE_1_CLKREF_EN>, 1711 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 1712 <&gcc GCC_PCIE_1_PIPE_CLK>; 1713 clock-names = "aux", "cfg_ahb", "ref", "rchng", "pipe"; 1714 1715 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 1716 reset-names = "phy"; 1717 1718 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 1719 assigned-clock-rates = <100000000>; 1720 1721 #clock-cells = <0>; 1722 clock-output-names = "pcie_1_pipe_clk"; 1723 1724 #phy-cells = <0>; 1725 1726 status = "disabled"; 1727 }; 1728 1729 ufs_mem_hc: ufshc@1d84000 { 1730 compatible = "qcom,sm8350-ufshc", "qcom,ufshc", 1731 "jedec,ufs-2.0"; 1732 reg = <0 0x01d84000 0 0x3000>; 1733 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1734 phys = <&ufs_mem_phy>; 1735 phy-names = "ufsphy"; 1736 lanes-per-direction = <2>; 1737 #reset-cells = <1>; 1738 resets = <&gcc GCC_UFS_PHY_BCR>; 1739 reset-names = "rst"; 1740 1741 power-domains = <&gcc UFS_PHY_GDSC>; 1742 1743 iommus = <&apps_smmu 0xe0 0x0>; 1744 dma-coherent; 1745 1746 clock-names = 1747 "core_clk", 1748 "bus_aggr_clk", 1749 "iface_clk", 1750 "core_clk_unipro", 1751 "ref_clk", 1752 "tx_lane0_sync_clk", 1753 "rx_lane0_sync_clk", 1754 "rx_lane1_sync_clk"; 1755 clocks = 1756 <&gcc GCC_UFS_PHY_AXI_CLK>, 1757 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1758 <&gcc GCC_UFS_PHY_AHB_CLK>, 1759 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1760 <&rpmhcc RPMH_CXO_CLK>, 1761 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1762 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1763 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1764 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1765 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1766 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1767 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 1768 interconnect-names = "ufs-ddr", "cpu-ufs"; 1769 freq-table-hz = 1770 <75000000 300000000>, 1771 <0 0>, 1772 <0 0>, 1773 <75000000 300000000>, 1774 <0 0>, 1775 <0 0>, 1776 <0 0>, 1777 <0 0>; 1778 status = "disabled"; 1779 }; 1780 1781 ufs_mem_phy: phy@1d87000 { 1782 compatible = "qcom,sm8350-qmp-ufs-phy"; 1783 reg = <0 0x01d87000 0 0x1000>; 1784 1785 clocks = <&rpmhcc RPMH_CXO_CLK>, 1786 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1787 <&gcc GCC_UFS_1_CLKREF_EN>; 1788 clock-names = "ref", 1789 "ref_aux", 1790 "qref"; 1791 1792 power-domains = <&gcc UFS_PHY_GDSC>; 1793 1794 resets = <&ufs_mem_hc 0>; 1795 reset-names = "ufsphy"; 1796 1797 #clock-cells = <1>; 1798 #phy-cells = <0>; 1799 1800 status = "disabled"; 1801 }; 1802 1803 cryptobam: dma-controller@1dc4000 { 1804 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1805 reg = <0 0x01dc4000 0 0x24000>; 1806 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1807 #dma-cells = <1>; 1808 qcom,ee = <0>; 1809 qcom,controlled-remotely; 1810 iommus = <&apps_smmu 0x594 0x0011>, 1811 <&apps_smmu 0x596 0x0011>; 1812 /* FIXME: Probing BAM DMA causes some abort and system hang */ 1813 status = "fail"; 1814 }; 1815 1816 crypto: crypto@1dfa000 { 1817 compatible = "qcom,sm8350-qce", "qcom,sm8150-qce", "qcom,qce"; 1818 reg = <0 0x01dfa000 0 0x6000>; 1819 dmas = <&cryptobam 4>, <&cryptobam 5>; 1820 dma-names = "rx", "tx"; 1821 iommus = <&apps_smmu 0x594 0x0011>, 1822 <&apps_smmu 0x596 0x0011>; 1823 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 1824 interconnect-names = "memory"; 1825 /* FIXME: dependency BAM DMA is disabled */ 1826 status = "disabled"; 1827 }; 1828 1829 ipa: ipa@1e40000 { 1830 compatible = "qcom,sm8350-ipa"; 1831 1832 iommus = <&apps_smmu 0x5c0 0x0>, 1833 <&apps_smmu 0x5c2 0x0>; 1834 reg = <0 0x01e40000 0 0x8000>, 1835 <0 0x01e50000 0 0x4b20>, 1836 <0 0x01e04000 0 0x23000>; 1837 reg-names = "ipa-reg", 1838 "ipa-shared", 1839 "gsi"; 1840 1841 interrupts-extended = <&intc GIC_SPI 655 IRQ_TYPE_EDGE_RISING>, 1842 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 1843 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1844 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 1845 interrupt-names = "ipa", 1846 "gsi", 1847 "ipa-clock-query", 1848 "ipa-setup-ready"; 1849 1850 clocks = <&rpmhcc RPMH_IPA_CLK>; 1851 clock-names = "core"; 1852 1853 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 1854 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>; 1855 interconnect-names = "memory", 1856 "config"; 1857 1858 qcom,qmp = <&aoss_qmp>; 1859 1860 qcom,smem-states = <&ipa_smp2p_out 0>, 1861 <&ipa_smp2p_out 1>; 1862 qcom,smem-state-names = "ipa-clock-enabled-valid", 1863 "ipa-clock-enabled"; 1864 1865 status = "disabled"; 1866 }; 1867 1868 tcsr_mutex: hwlock@1f40000 { 1869 compatible = "qcom,tcsr-mutex"; 1870 reg = <0x0 0x01f40000 0x0 0x40000>; 1871 #hwlock-cells = <1>; 1872 }; 1873 1874 tcsr: syscon@1fc0000 { 1875 compatible = "qcom,sm8350-tcsr", "syscon"; 1876 reg = <0x0 0x1fc0000 0x0 0x30000>; 1877 }; 1878 1879 adsp: remoteproc@3000000 { 1880 compatible = "qcom,sm8350-adsp-pas"; 1881 reg = <0x0 0x03000000 0x0 0x10000>; 1882 1883 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 1884 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 1885 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 1886 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 1887 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 1888 interrupt-names = "wdog", "fatal", "ready", 1889 "handover", "stop-ack"; 1890 1891 clocks = <&rpmhcc RPMH_CXO_CLK>; 1892 clock-names = "xo"; 1893 1894 power-domains = <&rpmhpd RPMHPD_LCX>, 1895 <&rpmhpd RPMHPD_LMX>; 1896 power-domain-names = "lcx", "lmx"; 1897 1898 memory-region = <&pil_adsp_mem>; 1899 1900 qcom,qmp = <&aoss_qmp>; 1901 1902 qcom,smem-states = <&smp2p_adsp_out 0>; 1903 qcom,smem-state-names = "stop"; 1904 1905 status = "disabled"; 1906 1907 glink-edge { 1908 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 1909 IPCC_MPROC_SIGNAL_GLINK_QMP 1910 IRQ_TYPE_EDGE_RISING>; 1911 mboxes = <&ipcc IPCC_CLIENT_LPASS 1912 IPCC_MPROC_SIGNAL_GLINK_QMP>; 1913 1914 label = "lpass"; 1915 qcom,remote-pid = <2>; 1916 1917 apr { 1918 compatible = "qcom,apr-v2"; 1919 qcom,glink-channels = "apr_audio_svc"; 1920 qcom,domain = <APR_DOMAIN_ADSP>; 1921 #address-cells = <1>; 1922 #size-cells = <0>; 1923 1924 service@3 { 1925 reg = <APR_SVC_ADSP_CORE>; 1926 compatible = "qcom,q6core"; 1927 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1928 }; 1929 1930 q6afe: service@4 { 1931 compatible = "qcom,q6afe"; 1932 reg = <APR_SVC_AFE>; 1933 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1934 1935 q6afedai: dais { 1936 compatible = "qcom,q6afe-dais"; 1937 #address-cells = <1>; 1938 #size-cells = <0>; 1939 #sound-dai-cells = <1>; 1940 }; 1941 1942 q6afecc: clock-controller { 1943 compatible = "qcom,q6afe-clocks"; 1944 #clock-cells = <2>; 1945 }; 1946 }; 1947 1948 q6asm: service@7 { 1949 compatible = "qcom,q6asm"; 1950 reg = <APR_SVC_ASM>; 1951 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1952 1953 q6asmdai: dais { 1954 compatible = "qcom,q6asm-dais"; 1955 #address-cells = <1>; 1956 #size-cells = <0>; 1957 #sound-dai-cells = <1>; 1958 iommus = <&apps_smmu 0x1801 0x0>; 1959 1960 dai@0 { 1961 reg = <0>; 1962 }; 1963 1964 dai@1 { 1965 reg = <1>; 1966 }; 1967 1968 dai@2 { 1969 reg = <2>; 1970 }; 1971 }; 1972 }; 1973 1974 q6adm: service@8 { 1975 compatible = "qcom,q6adm"; 1976 reg = <APR_SVC_ADM>; 1977 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 1978 1979 q6routing: routing { 1980 compatible = "qcom,q6adm-routing"; 1981 #sound-dai-cells = <0>; 1982 }; 1983 }; 1984 }; 1985 1986 fastrpc { 1987 compatible = "qcom,fastrpc"; 1988 qcom,glink-channels = "fastrpcglink-apps-dsp"; 1989 label = "adsp"; 1990 qcom,non-secure-domain; 1991 #address-cells = <1>; 1992 #size-cells = <0>; 1993 1994 compute-cb@3 { 1995 compatible = "qcom,fastrpc-compute-cb"; 1996 reg = <3>; 1997 iommus = <&apps_smmu 0x1803 0x0>; 1998 }; 1999 2000 compute-cb@4 { 2001 compatible = "qcom,fastrpc-compute-cb"; 2002 reg = <4>; 2003 iommus = <&apps_smmu 0x1804 0x0>; 2004 }; 2005 2006 compute-cb@5 { 2007 compatible = "qcom,fastrpc-compute-cb"; 2008 reg = <5>; 2009 iommus = <&apps_smmu 0x1805 0x0>; 2010 }; 2011 }; 2012 }; 2013 }; 2014 2015 lpass_tlmm: pinctrl@33c0000 { 2016 compatible = "qcom,sm8350-lpass-lpi-pinctrl"; 2017 reg = <0 0x033c0000 0 0x20000>, 2018 <0 0x03550000 0 0x10000>; 2019 2020 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2021 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2022 clock-names = "core", "audio"; 2023 2024 gpio-controller; 2025 #gpio-cells = <2>; 2026 gpio-ranges = <&lpass_tlmm 0 0 15>; 2027 }; 2028 2029 gpu: gpu@3d00000 { 2030 compatible = "qcom,adreno-660.1", "qcom,adreno"; 2031 2032 reg = <0 0x03d00000 0 0x40000>, 2033 <0 0x03d9e000 0 0x1000>, 2034 <0 0x03d61000 0 0x800>; 2035 reg-names = "kgsl_3d0_reg_memory", 2036 "cx_mem", 2037 "cx_dbgc"; 2038 2039 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2040 2041 iommus = <&adreno_smmu 0 0x400>, <&adreno_smmu 1 0x400>; 2042 2043 operating-points-v2 = <&gpu_opp_table>; 2044 2045 qcom,gmu = <&gmu>; 2046 #cooling-cells = <2>; 2047 2048 status = "disabled"; 2049 2050 zap-shader { 2051 memory-region = <&pil_gpu_mem>; 2052 }; 2053 2054 /* note: downstream checks gpu binning for 670 Mhz */ 2055 gpu_opp_table: opp-table { 2056 compatible = "operating-points-v2"; 2057 2058 opp-840000000 { 2059 opp-hz = /bits/ 64 <840000000>; 2060 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2061 }; 2062 2063 opp-778000000 { 2064 opp-hz = /bits/ 64 <778000000>; 2065 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2066 }; 2067 2068 opp-738000000 { 2069 opp-hz = /bits/ 64 <738000000>; 2070 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2071 }; 2072 2073 opp-676000000 { 2074 opp-hz = /bits/ 64 <676000000>; 2075 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2076 }; 2077 2078 opp-608000000 { 2079 opp-hz = /bits/ 64 <608000000>; 2080 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2081 }; 2082 2083 opp-540000000 { 2084 opp-hz = /bits/ 64 <540000000>; 2085 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2086 }; 2087 2088 opp-491000000 { 2089 opp-hz = /bits/ 64 <491000000>; 2090 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2091 }; 2092 2093 opp-443000000 { 2094 opp-hz = /bits/ 64 <443000000>; 2095 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2096 }; 2097 2098 opp-379000000 { 2099 opp-hz = /bits/ 64 <379000000>; 2100 opp-level = <80 /* RPMH_REGULATOR_LEVEL_LOW_SVS_L1 */>; 2101 }; 2102 2103 opp-315000000 { 2104 opp-hz = /bits/ 64 <315000000>; 2105 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2106 }; 2107 }; 2108 }; 2109 2110 gmu: gmu@3d6a000 { 2111 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu"; 2112 2113 reg = <0 0x03d6a000 0 0x34000>, 2114 <0 0x03de0000 0 0x10000>, 2115 <0 0x0b290000 0 0x10000>; 2116 reg-names = "gmu", "rscc", "gmu_pdc"; 2117 2118 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2120 interrupt-names = "hfi", "gmu"; 2121 2122 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2123 <&gpucc GPU_CC_CXO_CLK>, 2124 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2125 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2126 <&gpucc GPU_CC_AHB_CLK>, 2127 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2128 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2129 clock-names = "gmu", 2130 "cxo", 2131 "axi", 2132 "memnoc", 2133 "ahb", 2134 "hub", 2135 "smmu_vote"; 2136 2137 power-domains = <&gpucc GPU_CX_GDSC>, 2138 <&gpucc GPU_GX_GDSC>; 2139 power-domain-names = "cx", 2140 "gx"; 2141 2142 iommus = <&adreno_smmu 5 0x400>; 2143 2144 operating-points-v2 = <&gmu_opp_table>; 2145 2146 gmu_opp_table: opp-table { 2147 compatible = "operating-points-v2"; 2148 2149 opp-200000000 { 2150 opp-hz = /bits/ 64 <200000000>; 2151 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2152 }; 2153 }; 2154 }; 2155 2156 gpucc: clock-controller@3d90000 { 2157 compatible = "qcom,sm8350-gpucc"; 2158 reg = <0 0x03d90000 0 0x9000>; 2159 clocks = <&rpmhcc RPMH_CXO_CLK>, 2160 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2161 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2162 clock-names = "bi_tcxo", 2163 "gcc_gpu_gpll0_clk_src", 2164 "gcc_gpu_gpll0_div_clk_src"; 2165 #clock-cells = <1>; 2166 #reset-cells = <1>; 2167 #power-domain-cells = <1>; 2168 }; 2169 2170 adreno_smmu: iommu@3da0000 { 2171 compatible = "qcom,sm8350-smmu-500", "qcom,adreno-smmu", 2172 "qcom,smmu-500", "arm,mmu-500"; 2173 reg = <0 0x03da0000 0 0x20000>; 2174 #iommu-cells = <2>; 2175 #global-interrupts = <2>; 2176 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2177 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2178 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2179 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2180 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2181 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2182 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2183 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2184 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2185 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2186 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2187 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 2188 2189 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2190 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2191 <&gpucc GPU_CC_AHB_CLK>, 2192 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2193 <&gpucc GPU_CC_CX_GMU_CLK>, 2194 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2195 <&gpucc GPU_CC_HUB_AON_CLK>; 2196 clock-names = "bus", 2197 "iface", 2198 "ahb", 2199 "hlos1_vote_gpu_smmu", 2200 "cx_gmu", 2201 "hub_cx_int", 2202 "hub_aon"; 2203 2204 power-domains = <&gpucc GPU_CX_GDSC>; 2205 dma-coherent; 2206 }; 2207 2208 lpass_ag_noc: interconnect@3c40000 { 2209 compatible = "qcom,sm8350-lpass-ag-noc"; 2210 reg = <0 0x03c40000 0 0xf080>; 2211 #interconnect-cells = <2>; 2212 qcom,bcm-voters = <&apps_bcm_voter>; 2213 }; 2214 2215 mpss: remoteproc@4080000 { 2216 compatible = "qcom,sm8350-mpss-pas"; 2217 reg = <0x0 0x04080000 0x0 0x10000>; 2218 2219 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2220 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2221 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2222 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2223 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2224 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2225 interrupt-names = "wdog", "fatal", "ready", "handover", 2226 "stop-ack", "shutdown-ack"; 2227 2228 clocks = <&rpmhcc RPMH_CXO_CLK>; 2229 clock-names = "xo"; 2230 2231 power-domains = <&rpmhpd RPMHPD_CX>, 2232 <&rpmhpd RPMHPD_MSS>; 2233 power-domain-names = "cx", "mss"; 2234 2235 interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; 2236 2237 memory-region = <&pil_modem_mem>; 2238 2239 qcom,qmp = <&aoss_qmp>; 2240 2241 qcom,smem-states = <&smp2p_modem_out 0>; 2242 qcom,smem-state-names = "stop"; 2243 2244 status = "disabled"; 2245 2246 glink-edge { 2247 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2248 IPCC_MPROC_SIGNAL_GLINK_QMP 2249 IRQ_TYPE_EDGE_RISING>; 2250 mboxes = <&ipcc IPCC_CLIENT_MPSS 2251 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2252 label = "modem"; 2253 qcom,remote-pid = <1>; 2254 }; 2255 }; 2256 2257 slpi: remoteproc@5c00000 { 2258 compatible = "qcom,sm8350-slpi-pas"; 2259 reg = <0 0x05c00000 0 0x4000>; 2260 2261 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 2262 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 2263 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 2264 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 2265 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 2266 interrupt-names = "wdog", "fatal", "ready", 2267 "handover", "stop-ack"; 2268 2269 clocks = <&rpmhcc RPMH_CXO_CLK>; 2270 clock-names = "xo"; 2271 2272 power-domains = <&rpmhpd RPMHPD_LCX>, 2273 <&rpmhpd RPMHPD_LMX>; 2274 power-domain-names = "lcx", "lmx"; 2275 2276 memory-region = <&pil_slpi_mem>; 2277 2278 qcom,qmp = <&aoss_qmp>; 2279 2280 qcom,smem-states = <&smp2p_slpi_out 0>; 2281 qcom,smem-state-names = "stop"; 2282 2283 status = "disabled"; 2284 2285 glink-edge { 2286 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 2287 IPCC_MPROC_SIGNAL_GLINK_QMP 2288 IRQ_TYPE_EDGE_RISING>; 2289 mboxes = <&ipcc IPCC_CLIENT_SLPI 2290 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2291 2292 label = "slpi"; 2293 qcom,remote-pid = <3>; 2294 2295 fastrpc { 2296 compatible = "qcom,fastrpc"; 2297 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2298 label = "sdsp"; 2299 qcom,non-secure-domain; 2300 #address-cells = <1>; 2301 #size-cells = <0>; 2302 2303 compute-cb@1 { 2304 compatible = "qcom,fastrpc-compute-cb"; 2305 reg = <1>; 2306 iommus = <&apps_smmu 0x0541 0x0>; 2307 }; 2308 2309 compute-cb@2 { 2310 compatible = "qcom,fastrpc-compute-cb"; 2311 reg = <2>; 2312 iommus = <&apps_smmu 0x0542 0x0>; 2313 }; 2314 2315 compute-cb@3 { 2316 compatible = "qcom,fastrpc-compute-cb"; 2317 reg = <3>; 2318 iommus = <&apps_smmu 0x0543 0x0>; 2319 /* note: shared-cb = <4> in downstream */ 2320 }; 2321 }; 2322 }; 2323 }; 2324 2325 sdhc_2: mmc@8804000 { 2326 compatible = "qcom,sm8350-sdhci", "qcom,sdhci-msm-v5"; 2327 reg = <0 0x08804000 0 0x1000>; 2328 2329 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 2330 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 2331 interrupt-names = "hc_irq", "pwr_irq"; 2332 2333 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2334 <&gcc GCC_SDCC2_APPS_CLK>, 2335 <&rpmhcc RPMH_CXO_CLK>; 2336 clock-names = "iface", "core", "xo"; 2337 resets = <&gcc GCC_SDCC2_BCR>; 2338 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 2339 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 2340 interconnect-names = "sdhc-ddr","cpu-sdhc"; 2341 iommus = <&apps_smmu 0x4a0 0x0>; 2342 power-domains = <&rpmhpd RPMHPD_CX>; 2343 operating-points-v2 = <&sdhc2_opp_table>; 2344 bus-width = <4>; 2345 dma-coherent; 2346 2347 status = "disabled"; 2348 2349 sdhc2_opp_table: opp-table { 2350 compatible = "operating-points-v2"; 2351 2352 opp-100000000 { 2353 opp-hz = /bits/ 64 <100000000>; 2354 required-opps = <&rpmhpd_opp_low_svs>; 2355 }; 2356 2357 opp-202000000 { 2358 opp-hz = /bits/ 64 <202000000>; 2359 required-opps = <&rpmhpd_opp_svs_l1>; 2360 }; 2361 }; 2362 }; 2363 2364 usb_1_hsphy: phy@88e3000 { 2365 compatible = "qcom,sm8350-usb-hs-phy", 2366 "qcom,usb-snps-hs-7nm-phy"; 2367 reg = <0 0x088e3000 0 0x400>; 2368 status = "disabled"; 2369 #phy-cells = <0>; 2370 2371 clocks = <&rpmhcc RPMH_CXO_CLK>; 2372 clock-names = "ref"; 2373 2374 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2375 }; 2376 2377 usb_2_hsphy: phy@88e4000 { 2378 compatible = "qcom,sm8250-usb-hs-phy", 2379 "qcom,usb-snps-hs-7nm-phy"; 2380 reg = <0 0x088e4000 0 0x400>; 2381 status = "disabled"; 2382 #phy-cells = <0>; 2383 2384 clocks = <&rpmhcc RPMH_CXO_CLK>; 2385 clock-names = "ref"; 2386 2387 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2388 }; 2389 2390 refgen: regulator@88e7000 { 2391 compatible = "qcom,sm8350-refgen-regulator", 2392 "qcom,sm8250-refgen-regulator"; 2393 reg = <0x0 0x088e7000 0x0 0x84>; 2394 }; 2395 2396 usb_1_qmpphy: phy@88e8000 { 2397 compatible = "qcom,sm8350-qmp-usb3-dp-phy"; 2398 reg = <0 0x088e8000 0 0x3000>; 2399 2400 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2401 <&rpmhcc RPMH_CXO_CLK>, 2402 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2403 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2404 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 2405 2406 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2407 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2408 reset-names = "phy", "common"; 2409 2410 #clock-cells = <1>; 2411 #phy-cells = <1>; 2412 2413 orientation-switch; 2414 2415 status = "disabled"; 2416 2417 ports { 2418 #address-cells = <1>; 2419 #size-cells = <0>; 2420 2421 port@0 { 2422 reg = <0>; 2423 2424 usb_1_qmpphy_out: endpoint { 2425 }; 2426 }; 2427 2428 port@1 { 2429 reg = <1>; 2430 2431 usb_1_qmpphy_usb_ss_in: endpoint { 2432 remote-endpoint = <&usb_1_dwc3_ss>; 2433 }; 2434 }; 2435 2436 port@2 { 2437 reg = <2>; 2438 2439 usb_1_qmpphy_dp_in: endpoint { 2440 remote-endpoint = <&mdss_dp_out>; 2441 }; 2442 }; 2443 }; 2444 }; 2445 2446 usb_2_qmpphy: phy@88eb000 { 2447 compatible = "qcom,sm8350-qmp-usb3-uni-phy"; 2448 reg = <0 0x088eb000 0 0x2000>; 2449 status = "disabled"; 2450 2451 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2452 <&gcc GCC_USB3_SEC_CLKREF_EN>, 2453 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 2454 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2455 clock-names = "aux", 2456 "ref", 2457 "com_aux", 2458 "pipe"; 2459 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2460 #clock-cells = <0>; 2461 #phy-cells = <0>; 2462 2463 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 2464 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 2465 reset-names = "phy", 2466 "phy_phy"; 2467 }; 2468 2469 dc_noc: interconnect@90c0000 { 2470 compatible = "qcom,sm8350-dc-noc"; 2471 reg = <0 0x090c0000 0 0x4200>; 2472 #interconnect-cells = <2>; 2473 qcom,bcm-voters = <&apps_bcm_voter>; 2474 }; 2475 2476 gem_noc: interconnect@9100000 { 2477 compatible = "qcom,sm8350-gem-noc"; 2478 reg = <0 0x09100000 0 0xb4000>; 2479 #interconnect-cells = <2>; 2480 qcom,bcm-voters = <&apps_bcm_voter>; 2481 }; 2482 2483 system-cache-controller@9200000 { 2484 compatible = "qcom,sm8350-llcc"; 2485 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 2486 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 2487 <0 0x09600000 0 0x58000>; 2488 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 2489 "llcc3_base", "llcc_broadcast_base"; 2490 }; 2491 2492 compute_noc: interconnect@a0c0000 { 2493 compatible = "qcom,sm8350-compute-noc"; 2494 reg = <0 0x0a0c0000 0 0xa180>; 2495 #interconnect-cells = <2>; 2496 qcom,bcm-voters = <&apps_bcm_voter>; 2497 }; 2498 2499 cdsp: remoteproc@a300000 { 2500 compatible = "qcom,sm8350-cdsp-pas"; 2501 reg = <0x0 0x0a300000 0x0 0x10000>; 2502 2503 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 2504 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 2505 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 2506 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 2507 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 2508 interrupt-names = "wdog", "fatal", "ready", 2509 "handover", "stop-ack"; 2510 2511 clocks = <&rpmhcc RPMH_CXO_CLK>; 2512 clock-names = "xo"; 2513 2514 power-domains = <&rpmhpd RPMHPD_CX>, 2515 <&rpmhpd RPMHPD_MXC>; 2516 power-domain-names = "cx", "mxc"; 2517 2518 interconnects = <&compute_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 2519 2520 memory-region = <&pil_cdsp_mem>; 2521 2522 qcom,qmp = <&aoss_qmp>; 2523 2524 qcom,smem-states = <&smp2p_cdsp_out 0>; 2525 qcom,smem-state-names = "stop"; 2526 2527 status = "disabled"; 2528 2529 glink-edge { 2530 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 2531 IPCC_MPROC_SIGNAL_GLINK_QMP 2532 IRQ_TYPE_EDGE_RISING>; 2533 mboxes = <&ipcc IPCC_CLIENT_CDSP 2534 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2535 2536 label = "cdsp"; 2537 qcom,remote-pid = <5>; 2538 2539 fastrpc { 2540 compatible = "qcom,fastrpc"; 2541 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2542 label = "cdsp"; 2543 qcom,non-secure-domain; 2544 #address-cells = <1>; 2545 #size-cells = <0>; 2546 2547 compute-cb@1 { 2548 compatible = "qcom,fastrpc-compute-cb"; 2549 reg = <1>; 2550 iommus = <&apps_smmu 0x2161 0x0400>, 2551 <&apps_smmu 0x1181 0x0420>; 2552 }; 2553 2554 compute-cb@2 { 2555 compatible = "qcom,fastrpc-compute-cb"; 2556 reg = <2>; 2557 iommus = <&apps_smmu 0x2162 0x0400>, 2558 <&apps_smmu 0x1182 0x0420>; 2559 }; 2560 2561 compute-cb@3 { 2562 compatible = "qcom,fastrpc-compute-cb"; 2563 reg = <3>; 2564 iommus = <&apps_smmu 0x2163 0x0400>, 2565 <&apps_smmu 0x1183 0x0420>; 2566 }; 2567 2568 compute-cb@4 { 2569 compatible = "qcom,fastrpc-compute-cb"; 2570 reg = <4>; 2571 iommus = <&apps_smmu 0x2164 0x0400>, 2572 <&apps_smmu 0x1184 0x0420>; 2573 }; 2574 2575 compute-cb@5 { 2576 compatible = "qcom,fastrpc-compute-cb"; 2577 reg = <5>; 2578 iommus = <&apps_smmu 0x2165 0x0400>, 2579 <&apps_smmu 0x1185 0x0420>; 2580 }; 2581 2582 compute-cb@6 { 2583 compatible = "qcom,fastrpc-compute-cb"; 2584 reg = <6>; 2585 iommus = <&apps_smmu 0x2166 0x0400>, 2586 <&apps_smmu 0x1186 0x0420>; 2587 }; 2588 2589 compute-cb@7 { 2590 compatible = "qcom,fastrpc-compute-cb"; 2591 reg = <7>; 2592 iommus = <&apps_smmu 0x2167 0x0400>, 2593 <&apps_smmu 0x1187 0x0420>; 2594 }; 2595 2596 compute-cb@8 { 2597 compatible = "qcom,fastrpc-compute-cb"; 2598 reg = <8>; 2599 iommus = <&apps_smmu 0x2168 0x0400>, 2600 <&apps_smmu 0x1188 0x0420>; 2601 }; 2602 2603 /* note: secure cb9 in downstream */ 2604 }; 2605 }; 2606 }; 2607 2608 usb_1: usb@a6f8800 { 2609 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2610 reg = <0 0x0a6f8800 0 0x400>; 2611 status = "disabled"; 2612 #address-cells = <2>; 2613 #size-cells = <2>; 2614 ranges; 2615 2616 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2617 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2618 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2619 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2620 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2621 clock-names = "cfg_noc", 2622 "core", 2623 "iface", 2624 "sleep", 2625 "mock_utmi"; 2626 2627 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2628 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2629 assigned-clock-rates = <19200000>, <200000000>; 2630 2631 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2632 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2633 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2634 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2635 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2636 interrupt-names = "pwr_event", 2637 "hs_phy_irq", 2638 "dp_hs_phy_irq", 2639 "dm_hs_phy_irq", 2640 "ss_phy_irq"; 2641 2642 power-domains = <&gcc USB30_PRIM_GDSC>; 2643 2644 resets = <&gcc GCC_USB30_PRIM_BCR>; 2645 2646 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 2647 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 2648 interconnect-names = "usb-ddr", "apps-usb"; 2649 2650 usb_1_dwc3: usb@a600000 { 2651 compatible = "snps,dwc3"; 2652 reg = <0 0x0a600000 0 0xcd00>; 2653 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2654 iommus = <&apps_smmu 0x0 0x0>; 2655 snps,dis_u2_susphy_quirk; 2656 snps,dis_enblslpm_quirk; 2657 snps,dis-u1-entry-quirk; 2658 snps,dis-u2-entry-quirk; 2659 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 2660 phy-names = "usb2-phy", "usb3-phy"; 2661 2662 ports { 2663 #address-cells = <1>; 2664 #size-cells = <0>; 2665 2666 port@0 { 2667 reg = <0>; 2668 2669 usb_1_dwc3_hs: endpoint { 2670 }; 2671 }; 2672 2673 port@1 { 2674 reg = <1>; 2675 2676 usb_1_dwc3_ss: endpoint { 2677 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 2678 }; 2679 }; 2680 }; 2681 }; 2682 }; 2683 2684 usb_2: usb@a8f8800 { 2685 compatible = "qcom,sm8350-dwc3", "qcom,dwc3"; 2686 reg = <0 0x0a8f8800 0 0x400>; 2687 status = "disabled"; 2688 #address-cells = <2>; 2689 #size-cells = <2>; 2690 ranges; 2691 2692 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2693 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2694 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2695 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 2696 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2697 <&gcc GCC_USB3_SEC_CLKREF_EN>; 2698 clock-names = "cfg_noc", 2699 "core", 2700 "iface", 2701 "sleep", 2702 "mock_utmi", 2703 "xo"; 2704 2705 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2706 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2707 assigned-clock-rates = <19200000>, <200000000>; 2708 2709 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2710 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2711 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 2712 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 2713 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 2714 interrupt-names = "pwr_event", 2715 "hs_phy_irq", 2716 "dp_hs_phy_irq", 2717 "dm_hs_phy_irq", 2718 "ss_phy_irq"; 2719 2720 power-domains = <&gcc USB30_SEC_GDSC>; 2721 2722 resets = <&gcc GCC_USB30_SEC_BCR>; 2723 2724 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 2725 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 2726 interconnect-names = "usb-ddr", "apps-usb"; 2727 2728 usb_2_dwc3: usb@a800000 { 2729 compatible = "snps,dwc3"; 2730 reg = <0 0x0a800000 0 0xcd00>; 2731 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2732 iommus = <&apps_smmu 0x20 0x0>; 2733 snps,dis_u2_susphy_quirk; 2734 snps,dis_enblslpm_quirk; 2735 snps,dis-u1-entry-quirk; 2736 snps,dis-u2-entry-quirk; 2737 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 2738 phy-names = "usb2-phy", "usb3-phy"; 2739 }; 2740 }; 2741 2742 mdss: display-subsystem@ae00000 { 2743 compatible = "qcom,sm8350-mdss"; 2744 reg = <0 0x0ae00000 0 0x1000>; 2745 reg-names = "mdss"; 2746 2747 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 2748 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>, 2749 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2750 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2751 interconnect-names = "mdp0-mem", 2752 "mdp1-mem", 2753 "cpu-cfg"; 2754 2755 power-domains = <&dispcc MDSS_GDSC>; 2756 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 2757 2758 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2759 <&gcc GCC_DISP_HF_AXI_CLK>, 2760 <&gcc GCC_DISP_SF_AXI_CLK>, 2761 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2762 clock-names = "iface", "bus", "nrt_bus", "core"; 2763 2764 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2765 interrupt-controller; 2766 #interrupt-cells = <1>; 2767 2768 iommus = <&apps_smmu 0x820 0x402>; 2769 2770 status = "disabled"; 2771 2772 #address-cells = <2>; 2773 #size-cells = <2>; 2774 ranges; 2775 2776 mdss_mdp: display-controller@ae01000 { 2777 compatible = "qcom,sm8350-dpu"; 2778 reg = <0 0x0ae01000 0 0x8f000>, 2779 <0 0x0aeb0000 0 0x2008>; 2780 reg-names = "mdp", "vbif"; 2781 2782 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 2783 <&gcc GCC_DISP_SF_AXI_CLK>, 2784 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2785 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 2786 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2787 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2788 clock-names = "bus", 2789 "nrt_bus", 2790 "iface", 2791 "lut", 2792 "core", 2793 "vsync"; 2794 2795 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2796 assigned-clock-rates = <19200000>; 2797 2798 operating-points-v2 = <&dpu_opp_table>; 2799 power-domains = <&rpmhpd RPMHPD_MMCX>; 2800 2801 interrupt-parent = <&mdss>; 2802 interrupts = <0>; 2803 2804 dpu_opp_table: opp-table { 2805 compatible = "operating-points-v2"; 2806 2807 /* TODO: opp-200000000 should work with 2808 * &rpmhpd_opp_low_svs, but one some of 2809 * sm8350_hdk boards reboot using this 2810 * opp. 2811 */ 2812 opp-200000000 { 2813 opp-hz = /bits/ 64 <200000000>; 2814 required-opps = <&rpmhpd_opp_svs>; 2815 }; 2816 2817 opp-300000000 { 2818 opp-hz = /bits/ 64 <300000000>; 2819 required-opps = <&rpmhpd_opp_svs>; 2820 }; 2821 2822 opp-345000000 { 2823 opp-hz = /bits/ 64 <345000000>; 2824 required-opps = <&rpmhpd_opp_svs_l1>; 2825 }; 2826 2827 opp-460000000 { 2828 opp-hz = /bits/ 64 <460000000>; 2829 required-opps = <&rpmhpd_opp_nom>; 2830 }; 2831 }; 2832 2833 ports { 2834 #address-cells = <1>; 2835 #size-cells = <0>; 2836 2837 port@0 { 2838 reg = <0>; 2839 dpu_intf1_out: endpoint { 2840 remote-endpoint = <&mdss_dsi0_in>; 2841 }; 2842 }; 2843 2844 port@1 { 2845 reg = <1>; 2846 dpu_intf2_out: endpoint { 2847 remote-endpoint = <&mdss_dsi1_in>; 2848 }; 2849 }; 2850 2851 port@2 { 2852 reg = <2>; 2853 dpu_intf0_out: endpoint { 2854 remote-endpoint = <&mdss_dp_in>; 2855 }; 2856 }; 2857 }; 2858 }; 2859 2860 mdss_dp: displayport-controller@ae90000 { 2861 compatible = "qcom,sm8350-dp"; 2862 reg = <0 0xae90000 0 0x200>, 2863 <0 0xae90200 0 0x200>, 2864 <0 0xae90400 0 0x600>, 2865 <0 0xae91000 0 0x400>, 2866 <0 0xae91400 0 0x400>; 2867 interrupt-parent = <&mdss>; 2868 interrupts = <12>; 2869 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2870 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 2871 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 2872 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 2873 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 2874 clock-names = "core_iface", 2875 "core_aux", 2876 "ctrl_link", 2877 "ctrl_link_iface", 2878 "stream_pixel"; 2879 2880 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 2881 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 2882 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 2883 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 2884 2885 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 2886 phy-names = "dp"; 2887 2888 #sound-dai-cells = <0>; 2889 2890 operating-points-v2 = <&dp_opp_table>; 2891 power-domains = <&rpmhpd RPMHPD_MMCX>; 2892 2893 status = "disabled"; 2894 2895 ports { 2896 #address-cells = <1>; 2897 #size-cells = <0>; 2898 2899 port@0 { 2900 reg = <0>; 2901 mdss_dp_in: endpoint { 2902 remote-endpoint = <&dpu_intf0_out>; 2903 }; 2904 }; 2905 2906 port@1 { 2907 reg = <1>; 2908 2909 mdss_dp_out: endpoint { 2910 remote-endpoint = <&usb_1_qmpphy_dp_in>; 2911 }; 2912 }; 2913 }; 2914 2915 dp_opp_table: opp-table { 2916 compatible = "operating-points-v2"; 2917 2918 opp-160000000 { 2919 opp-hz = /bits/ 64 <160000000>; 2920 required-opps = <&rpmhpd_opp_low_svs>; 2921 }; 2922 2923 opp-270000000 { 2924 opp-hz = /bits/ 64 <270000000>; 2925 required-opps = <&rpmhpd_opp_svs>; 2926 }; 2927 2928 opp-540000000 { 2929 opp-hz = /bits/ 64 <540000000>; 2930 required-opps = <&rpmhpd_opp_svs_l1>; 2931 }; 2932 2933 opp-810000000 { 2934 opp-hz = /bits/ 64 <810000000>; 2935 required-opps = <&rpmhpd_opp_nom>; 2936 }; 2937 }; 2938 }; 2939 2940 mdss_dsi0: dsi@ae94000 { 2941 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2942 reg = <0 0x0ae94000 0 0x400>; 2943 reg-names = "dsi_ctrl"; 2944 2945 interrupt-parent = <&mdss>; 2946 interrupts = <4>; 2947 2948 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2949 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2950 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2951 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2952 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2953 <&gcc GCC_DISP_HF_AXI_CLK>; 2954 clock-names = "byte", 2955 "byte_intf", 2956 "pixel", 2957 "core", 2958 "iface", 2959 "bus"; 2960 2961 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2962 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2963 assigned-clock-parents = <&mdss_dsi0_phy 0>, 2964 <&mdss_dsi0_phy 1>; 2965 2966 operating-points-v2 = <&dsi0_opp_table>; 2967 power-domains = <&rpmhpd RPMHPD_MMCX>; 2968 refgen-supply = <&refgen>; 2969 2970 phys = <&mdss_dsi0_phy>; 2971 2972 #address-cells = <1>; 2973 #size-cells = <0>; 2974 2975 status = "disabled"; 2976 2977 dsi0_opp_table: opp-table { 2978 compatible = "operating-points-v2"; 2979 2980 /* TODO: opp-187500000 should work with 2981 * &rpmhpd_opp_low_svs, but one some of 2982 * sm8350_hdk boards reboot using this 2983 * opp. 2984 */ 2985 opp-187500000 { 2986 opp-hz = /bits/ 64 <187500000>; 2987 required-opps = <&rpmhpd_opp_svs>; 2988 }; 2989 2990 opp-300000000 { 2991 opp-hz = /bits/ 64 <300000000>; 2992 required-opps = <&rpmhpd_opp_svs>; 2993 }; 2994 2995 opp-358000000 { 2996 opp-hz = /bits/ 64 <358000000>; 2997 required-opps = <&rpmhpd_opp_svs_l1>; 2998 }; 2999 }; 3000 3001 ports { 3002 #address-cells = <1>; 3003 #size-cells = <0>; 3004 3005 port@0 { 3006 reg = <0>; 3007 mdss_dsi0_in: endpoint { 3008 remote-endpoint = <&dpu_intf1_out>; 3009 }; 3010 }; 3011 3012 port@1 { 3013 reg = <1>; 3014 mdss_dsi0_out: endpoint { 3015 }; 3016 }; 3017 }; 3018 }; 3019 3020 mdss_dsi0_phy: phy@ae94400 { 3021 compatible = "qcom,sm8350-dsi-phy-5nm"; 3022 reg = <0 0x0ae94400 0 0x200>, 3023 <0 0x0ae94600 0 0x280>, 3024 <0 0x0ae94900 0 0x27c>; 3025 reg-names = "dsi_phy", 3026 "dsi_phy_lane", 3027 "dsi_pll"; 3028 3029 #clock-cells = <1>; 3030 #phy-cells = <0>; 3031 3032 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3033 <&rpmhcc RPMH_CXO_CLK>; 3034 clock-names = "iface", "ref"; 3035 3036 status = "disabled"; 3037 }; 3038 3039 mdss_dsi1: dsi@ae96000 { 3040 compatible = "qcom,sm8350-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3041 reg = <0 0x0ae96000 0 0x400>; 3042 reg-names = "dsi_ctrl"; 3043 3044 interrupt-parent = <&mdss>; 3045 interrupts = <5>; 3046 3047 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 3048 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 3049 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 3050 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 3051 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3052 <&gcc GCC_DISP_HF_AXI_CLK>; 3053 clock-names = "byte", 3054 "byte_intf", 3055 "pixel", 3056 "core", 3057 "iface", 3058 "bus"; 3059 3060 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 3061 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 3062 assigned-clock-parents = <&mdss_dsi1_phy 0>, 3063 <&mdss_dsi1_phy 1>; 3064 3065 operating-points-v2 = <&dsi1_opp_table>; 3066 power-domains = <&rpmhpd RPMHPD_MMCX>; 3067 refgen-supply = <&refgen>; 3068 3069 phys = <&mdss_dsi1_phy>; 3070 3071 #address-cells = <1>; 3072 #size-cells = <0>; 3073 3074 status = "disabled"; 3075 3076 dsi1_opp_table: opp-table { 3077 compatible = "operating-points-v2"; 3078 3079 /* TODO: opp-187500000 should work with 3080 * &rpmhpd_opp_low_svs, but one some of 3081 * sm8350_hdk boards reboot using this 3082 * opp. 3083 */ 3084 opp-187500000 { 3085 opp-hz = /bits/ 64 <187500000>; 3086 required-opps = <&rpmhpd_opp_svs>; 3087 }; 3088 3089 opp-300000000 { 3090 opp-hz = /bits/ 64 <300000000>; 3091 required-opps = <&rpmhpd_opp_svs>; 3092 }; 3093 3094 opp-358000000 { 3095 opp-hz = /bits/ 64 <358000000>; 3096 required-opps = <&rpmhpd_opp_svs_l1>; 3097 }; 3098 }; 3099 3100 ports { 3101 #address-cells = <1>; 3102 #size-cells = <0>; 3103 3104 port@0 { 3105 reg = <0>; 3106 mdss_dsi1_in: endpoint { 3107 remote-endpoint = <&dpu_intf2_out>; 3108 }; 3109 }; 3110 3111 port@1 { 3112 reg = <1>; 3113 mdss_dsi1_out: endpoint { 3114 }; 3115 }; 3116 }; 3117 }; 3118 3119 mdss_dsi1_phy: phy@ae96400 { 3120 compatible = "qcom,sm8350-dsi-phy-5nm"; 3121 reg = <0 0x0ae96400 0 0x200>, 3122 <0 0x0ae96600 0 0x280>, 3123 <0 0x0ae96900 0 0x27c>; 3124 reg-names = "dsi_phy", 3125 "dsi_phy_lane", 3126 "dsi_pll"; 3127 3128 #clock-cells = <1>; 3129 #phy-cells = <0>; 3130 3131 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3132 <&rpmhcc RPMH_CXO_CLK>; 3133 clock-names = "iface", "ref"; 3134 3135 status = "disabled"; 3136 }; 3137 }; 3138 3139 dispcc: clock-controller@af00000 { 3140 compatible = "qcom,sm8350-dispcc"; 3141 reg = <0 0x0af00000 0 0x10000>; 3142 clocks = <&rpmhcc RPMH_CXO_CLK>, 3143 <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>, 3144 <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>, 3145 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 3146 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 3147 clock-names = "bi_tcxo", 3148 "dsi0_phy_pll_out_byteclk", 3149 "dsi0_phy_pll_out_dsiclk", 3150 "dsi1_phy_pll_out_byteclk", 3151 "dsi1_phy_pll_out_dsiclk", 3152 "dp_phy_pll_link_clk", 3153 "dp_phy_pll_vco_div_clk"; 3154 #clock-cells = <1>; 3155 #reset-cells = <1>; 3156 #power-domain-cells = <1>; 3157 3158 power-domains = <&rpmhpd RPMHPD_MMCX>; 3159 }; 3160 3161 pdc: interrupt-controller@b220000 { 3162 compatible = "qcom,sm8350-pdc", "qcom,pdc"; 3163 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 3164 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, <55 306 4>, 3165 <59 312 3>, <62 374 2>, <64 434 2>, <66 438 3>, 3166 <69 86 1>, <70 520 54>, <124 609 31>, <155 63 1>, 3167 <156 716 12>; 3168 #interrupt-cells = <2>; 3169 interrupt-parent = <&intc>; 3170 interrupt-controller; 3171 }; 3172 3173 tsens0: thermal-sensor@c263000 { 3174 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3175 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 3176 <0 0x0c222000 0 0x8>; /* SROT */ 3177 #qcom,sensors = <15>; 3178 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 3179 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 3180 interrupt-names = "uplow", "critical"; 3181 #thermal-sensor-cells = <1>; 3182 }; 3183 3184 tsens1: thermal-sensor@c265000 { 3185 compatible = "qcom,sm8350-tsens", "qcom,tsens-v2"; 3186 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 3187 <0 0x0c223000 0 0x8>; /* SROT */ 3188 #qcom,sensors = <14>; 3189 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 3190 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 3191 interrupt-names = "uplow", "critical"; 3192 #thermal-sensor-cells = <1>; 3193 }; 3194 3195 aoss_qmp: power-management@c300000 { 3196 compatible = "qcom,sm8350-aoss-qmp", "qcom,aoss-qmp"; 3197 reg = <0 0x0c300000 0 0x400>; 3198 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 3199 IRQ_TYPE_EDGE_RISING>; 3200 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 3201 3202 #clock-cells = <0>; 3203 }; 3204 3205 sram@c3f0000 { 3206 compatible = "qcom,rpmh-stats"; 3207 reg = <0 0x0c3f0000 0 0x400>; 3208 }; 3209 3210 spmi_bus: spmi@c440000 { 3211 compatible = "qcom,spmi-pmic-arb"; 3212 reg = <0x0 0x0c440000 0x0 0x1100>, 3213 <0x0 0x0c600000 0x0 0x2000000>, 3214 <0x0 0x0e600000 0x0 0x100000>, 3215 <0x0 0x0e700000 0x0 0xa0000>, 3216 <0x0 0x0c40a000 0x0 0x26000>; 3217 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3218 interrupt-names = "periph_irq"; 3219 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3220 qcom,ee = <0>; 3221 qcom,channel = <0>; 3222 #address-cells = <2>; 3223 #size-cells = <0>; 3224 interrupt-controller; 3225 #interrupt-cells = <4>; 3226 }; 3227 3228 tlmm: pinctrl@f100000 { 3229 compatible = "qcom,sm8350-tlmm"; 3230 reg = <0 0x0f100000 0 0x300000>; 3231 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3232 gpio-controller; 3233 #gpio-cells = <2>; 3234 interrupt-controller; 3235 #interrupt-cells = <2>; 3236 gpio-ranges = <&tlmm 0 0 204>; 3237 wakeup-parent = <&pdc>; 3238 3239 sdc2_default_state: sdc2-default-state { 3240 clk-pins { 3241 pins = "sdc2_clk"; 3242 drive-strength = <16>; 3243 bias-disable; 3244 }; 3245 3246 cmd-pins { 3247 pins = "sdc2_cmd"; 3248 drive-strength = <16>; 3249 bias-pull-up; 3250 }; 3251 3252 data-pins { 3253 pins = "sdc2_data"; 3254 drive-strength = <16>; 3255 bias-pull-up; 3256 }; 3257 }; 3258 3259 sdc2_sleep_state: sdc2-sleep-state { 3260 clk-pins { 3261 pins = "sdc2_clk"; 3262 drive-strength = <2>; 3263 bias-disable; 3264 }; 3265 3266 cmd-pins { 3267 pins = "sdc2_cmd"; 3268 drive-strength = <2>; 3269 bias-pull-up; 3270 }; 3271 3272 data-pins { 3273 pins = "sdc2_data"; 3274 drive-strength = <2>; 3275 bias-pull-up; 3276 }; 3277 }; 3278 3279 qup_uart3_default_state: qup-uart3-default-state { 3280 rx-pins { 3281 pins = "gpio18"; 3282 function = "qup3"; 3283 }; 3284 tx-pins { 3285 pins = "gpio19"; 3286 function = "qup3"; 3287 }; 3288 }; 3289 3290 qup_uart6_default: qup-uart6-default-state { 3291 pins = "gpio30", "gpio31"; 3292 function = "qup6"; 3293 drive-strength = <2>; 3294 bias-disable; 3295 }; 3296 3297 qup_uart18_default: qup-uart18-default-state { 3298 pins = "gpio68", "gpio69"; 3299 function = "qup18"; 3300 drive-strength = <2>; 3301 bias-disable; 3302 }; 3303 3304 qup_i2c0_default: qup-i2c0-default-state { 3305 pins = "gpio4", "gpio5"; 3306 function = "qup0"; 3307 drive-strength = <2>; 3308 bias-pull-up; 3309 }; 3310 3311 qup_i2c1_default: qup-i2c1-default-state { 3312 pins = "gpio8", "gpio9"; 3313 function = "qup1"; 3314 drive-strength = <2>; 3315 bias-pull-up; 3316 }; 3317 3318 qup_i2c2_default: qup-i2c2-default-state { 3319 pins = "gpio12", "gpio13"; 3320 function = "qup2"; 3321 drive-strength = <2>; 3322 bias-pull-up; 3323 }; 3324 3325 qup_i2c4_default: qup-i2c4-default-state { 3326 pins = "gpio20", "gpio21"; 3327 function = "qup4"; 3328 drive-strength = <2>; 3329 bias-pull-up; 3330 }; 3331 3332 qup_i2c5_default: qup-i2c5-default-state { 3333 pins = "gpio24", "gpio25"; 3334 function = "qup5"; 3335 drive-strength = <2>; 3336 bias-pull-up; 3337 }; 3338 3339 qup_i2c6_default: qup-i2c6-default-state { 3340 pins = "gpio28", "gpio29"; 3341 function = "qup6"; 3342 drive-strength = <2>; 3343 bias-pull-up; 3344 }; 3345 3346 qup_i2c7_default: qup-i2c7-default-state { 3347 pins = "gpio32", "gpio33"; 3348 function = "qup7"; 3349 drive-strength = <2>; 3350 bias-disable; 3351 }; 3352 3353 qup_i2c8_default: qup-i2c8-default-state { 3354 pins = "gpio36", "gpio37"; 3355 function = "qup8"; 3356 drive-strength = <2>; 3357 bias-pull-up; 3358 }; 3359 3360 qup_i2c9_default: qup-i2c9-default-state { 3361 pins = "gpio40", "gpio41"; 3362 function = "qup9"; 3363 drive-strength = <2>; 3364 bias-pull-up; 3365 }; 3366 3367 qup_i2c10_default: qup-i2c10-default-state { 3368 pins = "gpio44", "gpio45"; 3369 function = "qup10"; 3370 drive-strength = <2>; 3371 bias-pull-up; 3372 }; 3373 3374 qup_i2c11_default: qup-i2c11-default-state { 3375 pins = "gpio48", "gpio49"; 3376 function = "qup11"; 3377 drive-strength = <2>; 3378 bias-pull-up; 3379 }; 3380 3381 qup_i2c12_default: qup-i2c12-default-state { 3382 pins = "gpio52", "gpio53"; 3383 function = "qup12"; 3384 drive-strength = <2>; 3385 bias-pull-up; 3386 }; 3387 3388 qup_i2c13_default: qup-i2c13-default-state { 3389 pins = "gpio0", "gpio1"; 3390 function = "qup13"; 3391 drive-strength = <2>; 3392 bias-pull-up; 3393 }; 3394 3395 qup_i2c14_default: qup-i2c14-default-state { 3396 pins = "gpio56", "gpio57"; 3397 function = "qup14"; 3398 drive-strength = <2>; 3399 bias-disable; 3400 }; 3401 3402 qup_i2c15_default: qup-i2c15-default-state { 3403 pins = "gpio60", "gpio61"; 3404 function = "qup15"; 3405 drive-strength = <2>; 3406 bias-disable; 3407 }; 3408 3409 qup_i2c16_default: qup-i2c16-default-state { 3410 pins = "gpio64", "gpio65"; 3411 function = "qup16"; 3412 drive-strength = <2>; 3413 bias-disable; 3414 }; 3415 3416 qup_i2c17_default: qup-i2c17-default-state { 3417 pins = "gpio72", "gpio73"; 3418 function = "qup17"; 3419 drive-strength = <2>; 3420 bias-disable; 3421 }; 3422 3423 qup_i2c19_default: qup-i2c19-default-state { 3424 pins = "gpio76", "gpio77"; 3425 function = "qup19"; 3426 drive-strength = <2>; 3427 bias-disable; 3428 }; 3429 }; 3430 3431 apps_smmu: iommu@15000000 { 3432 compatible = "qcom,sm8350-smmu-500", "arm,mmu-500"; 3433 reg = <0 0x15000000 0 0x100000>; 3434 #iommu-cells = <2>; 3435 #global-interrupts = <2>; 3436 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 3437 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3438 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3439 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3440 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3441 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3442 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3443 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3444 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3445 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3446 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3447 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3448 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3449 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3450 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3451 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3452 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3453 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3454 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3455 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3456 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3457 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3458 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3459 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3460 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3461 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3462 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3463 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3465 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3466 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3467 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3468 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3469 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3470 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3471 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3472 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3473 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3474 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3475 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3477 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3478 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3479 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3480 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3481 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3482 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3483 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3484 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3485 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3486 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3487 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3489 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3490 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3491 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3492 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3493 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3494 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3495 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3496 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3497 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3498 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3499 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3501 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3510 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3511 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3513 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3514 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3515 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3516 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3517 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3518 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3519 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3520 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3521 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3522 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3523 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3525 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3526 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3527 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3528 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3529 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3530 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3531 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3532 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3533 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 3534 dma-coherent; 3535 }; 3536 3537 intc: interrupt-controller@17a00000 { 3538 compatible = "arm,gic-v3"; 3539 #interrupt-cells = <3>; 3540 interrupt-controller; 3541 #redistributor-regions = <1>; 3542 redistributor-stride = <0 0x20000>; 3543 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 3544 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 3545 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3546 }; 3547 3548 timer@17c20000 { 3549 compatible = "arm,armv7-timer-mem"; 3550 #address-cells = <1>; 3551 #size-cells = <1>; 3552 ranges = <0 0 0 0x20000000>; 3553 reg = <0x0 0x17c20000 0x0 0x1000>; 3554 clock-frequency = <19200000>; 3555 3556 frame@17c21000 { 3557 frame-number = <0>; 3558 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3559 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3560 reg = <0x17c21000 0x1000>, 3561 <0x17c22000 0x1000>; 3562 }; 3563 3564 frame@17c23000 { 3565 frame-number = <1>; 3566 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3567 reg = <0x17c23000 0x1000>; 3568 status = "disabled"; 3569 }; 3570 3571 frame@17c25000 { 3572 frame-number = <2>; 3573 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3574 reg = <0x17c25000 0x1000>; 3575 status = "disabled"; 3576 }; 3577 3578 frame@17c27000 { 3579 frame-number = <3>; 3580 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3581 reg = <0x17c27000 0x1000>; 3582 status = "disabled"; 3583 }; 3584 3585 frame@17c29000 { 3586 frame-number = <4>; 3587 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3588 reg = <0x17c29000 0x1000>; 3589 status = "disabled"; 3590 }; 3591 3592 frame@17c2b000 { 3593 frame-number = <5>; 3594 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3595 reg = <0x17c2b000 0x1000>; 3596 status = "disabled"; 3597 }; 3598 3599 frame@17c2d000 { 3600 frame-number = <6>; 3601 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3602 reg = <0x17c2d000 0x1000>; 3603 status = "disabled"; 3604 }; 3605 }; 3606 3607 apps_rsc: rsc@18200000 { 3608 label = "apps_rsc"; 3609 compatible = "qcom,rpmh-rsc"; 3610 reg = <0x0 0x18200000 0x0 0x10000>, 3611 <0x0 0x18210000 0x0 0x10000>, 3612 <0x0 0x18220000 0x0 0x10000>; 3613 reg-names = "drv-0", "drv-1", "drv-2"; 3614 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3615 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3616 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3617 qcom,tcs-offset = <0xd00>; 3618 qcom,drv-id = <2>; 3619 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 3620 <WAKE_TCS 3>, <CONTROL_TCS 0>; 3621 power-domains = <&cluster_pd>; 3622 3623 rpmhcc: clock-controller { 3624 compatible = "qcom,sm8350-rpmh-clk"; 3625 #clock-cells = <1>; 3626 clock-names = "xo"; 3627 clocks = <&xo_board>; 3628 }; 3629 3630 rpmhpd: power-controller { 3631 compatible = "qcom,sm8350-rpmhpd"; 3632 #power-domain-cells = <1>; 3633 operating-points-v2 = <&rpmhpd_opp_table>; 3634 3635 rpmhpd_opp_table: opp-table { 3636 compatible = "operating-points-v2"; 3637 3638 rpmhpd_opp_ret: opp1 { 3639 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3640 }; 3641 3642 rpmhpd_opp_min_svs: opp2 { 3643 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3644 }; 3645 3646 rpmhpd_opp_low_svs: opp3 { 3647 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3648 }; 3649 3650 rpmhpd_opp_svs: opp4 { 3651 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3652 }; 3653 3654 rpmhpd_opp_svs_l1: opp5 { 3655 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3656 }; 3657 3658 rpmhpd_opp_nom: opp6 { 3659 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3660 }; 3661 3662 rpmhpd_opp_nom_l1: opp7 { 3663 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3664 }; 3665 3666 rpmhpd_opp_nom_l2: opp8 { 3667 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3668 }; 3669 3670 rpmhpd_opp_turbo: opp9 { 3671 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3672 }; 3673 3674 rpmhpd_opp_turbo_l1: opp10 { 3675 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3676 }; 3677 }; 3678 }; 3679 3680 apps_bcm_voter: bcm-voter { 3681 compatible = "qcom,bcm-voter"; 3682 }; 3683 }; 3684 3685 cpufreq_hw: cpufreq@18591000 { 3686 compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss"; 3687 reg = <0 0x18591000 0 0x1000>, 3688 <0 0x18592000 0 0x1000>, 3689 <0 0x18593000 0 0x1000>; 3690 reg-names = "freq-domain0", "freq-domain1", "freq-domain2"; 3691 3692 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 3693 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 3694 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 3695 interrupt-names = "dcvsh-irq-0", 3696 "dcvsh-irq-1", 3697 "dcvsh-irq-2"; 3698 3699 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 3700 clock-names = "xo", "alternate"; 3701 3702 #freq-domain-cells = <1>; 3703 #clock-cells = <1>; 3704 }; 3705 }; 3706 3707 thermal_zones: thermal-zones { 3708 cpu0-thermal { 3709 polling-delay-passive = <250>; 3710 3711 thermal-sensors = <&tsens0 1>; 3712 3713 trips { 3714 cpu0_alert0: trip-point0 { 3715 temperature = <90000>; 3716 hysteresis = <2000>; 3717 type = "passive"; 3718 }; 3719 3720 cpu0_alert1: trip-point1 { 3721 temperature = <95000>; 3722 hysteresis = <2000>; 3723 type = "passive"; 3724 }; 3725 3726 cpu0_crit: cpu-crit { 3727 temperature = <110000>; 3728 hysteresis = <1000>; 3729 type = "critical"; 3730 }; 3731 }; 3732 3733 cooling-maps { 3734 map0 { 3735 trip = <&cpu0_alert0>; 3736 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3737 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3738 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3739 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3740 }; 3741 map1 { 3742 trip = <&cpu0_alert1>; 3743 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3744 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3745 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3746 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3747 }; 3748 }; 3749 }; 3750 3751 cpu1-thermal { 3752 polling-delay-passive = <250>; 3753 3754 thermal-sensors = <&tsens0 2>; 3755 3756 trips { 3757 cpu1_alert0: trip-point0 { 3758 temperature = <90000>; 3759 hysteresis = <2000>; 3760 type = "passive"; 3761 }; 3762 3763 cpu1_alert1: trip-point1 { 3764 temperature = <95000>; 3765 hysteresis = <2000>; 3766 type = "passive"; 3767 }; 3768 3769 cpu1_crit: cpu-crit { 3770 temperature = <110000>; 3771 hysteresis = <1000>; 3772 type = "critical"; 3773 }; 3774 }; 3775 3776 cooling-maps { 3777 map0 { 3778 trip = <&cpu1_alert0>; 3779 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3783 }; 3784 map1 { 3785 trip = <&cpu1_alert1>; 3786 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3787 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3788 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3789 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3790 }; 3791 }; 3792 }; 3793 3794 cpu2-thermal { 3795 polling-delay-passive = <250>; 3796 3797 thermal-sensors = <&tsens0 3>; 3798 3799 trips { 3800 cpu2_alert0: trip-point0 { 3801 temperature = <90000>; 3802 hysteresis = <2000>; 3803 type = "passive"; 3804 }; 3805 3806 cpu2_alert1: trip-point1 { 3807 temperature = <95000>; 3808 hysteresis = <2000>; 3809 type = "passive"; 3810 }; 3811 3812 cpu2_crit: cpu-crit { 3813 temperature = <110000>; 3814 hysteresis = <1000>; 3815 type = "critical"; 3816 }; 3817 }; 3818 3819 cooling-maps { 3820 map0 { 3821 trip = <&cpu2_alert0>; 3822 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3823 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3824 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3825 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3826 }; 3827 map1 { 3828 trip = <&cpu2_alert1>; 3829 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3830 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3831 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3832 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3833 }; 3834 }; 3835 }; 3836 3837 cpu3-thermal { 3838 polling-delay-passive = <250>; 3839 3840 thermal-sensors = <&tsens0 4>; 3841 3842 trips { 3843 cpu3_alert0: trip-point0 { 3844 temperature = <90000>; 3845 hysteresis = <2000>; 3846 type = "passive"; 3847 }; 3848 3849 cpu3_alert1: trip-point1 { 3850 temperature = <95000>; 3851 hysteresis = <2000>; 3852 type = "passive"; 3853 }; 3854 3855 cpu3_crit: cpu-crit { 3856 temperature = <110000>; 3857 hysteresis = <1000>; 3858 type = "critical"; 3859 }; 3860 }; 3861 3862 cooling-maps { 3863 map0 { 3864 trip = <&cpu3_alert0>; 3865 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3866 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3867 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3868 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3869 }; 3870 map1 { 3871 trip = <&cpu3_alert1>; 3872 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3873 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3874 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3875 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3876 }; 3877 }; 3878 }; 3879 3880 cpu4-top-thermal { 3881 polling-delay-passive = <250>; 3882 3883 thermal-sensors = <&tsens0 7>; 3884 3885 trips { 3886 cpu4_top_alert0: trip-point0 { 3887 temperature = <90000>; 3888 hysteresis = <2000>; 3889 type = "passive"; 3890 }; 3891 3892 cpu4_top_alert1: trip-point1 { 3893 temperature = <95000>; 3894 hysteresis = <2000>; 3895 type = "passive"; 3896 }; 3897 3898 cpu4_top_crit: cpu-crit { 3899 temperature = <110000>; 3900 hysteresis = <1000>; 3901 type = "critical"; 3902 }; 3903 }; 3904 3905 cooling-maps { 3906 map0 { 3907 trip = <&cpu4_top_alert0>; 3908 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3909 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3910 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3911 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3912 }; 3913 map1 { 3914 trip = <&cpu4_top_alert1>; 3915 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3916 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3917 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3918 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3919 }; 3920 }; 3921 }; 3922 3923 cpu5-top-thermal { 3924 polling-delay-passive = <250>; 3925 3926 thermal-sensors = <&tsens0 8>; 3927 3928 trips { 3929 cpu5_top_alert0: trip-point0 { 3930 temperature = <90000>; 3931 hysteresis = <2000>; 3932 type = "passive"; 3933 }; 3934 3935 cpu5_top_alert1: trip-point1 { 3936 temperature = <95000>; 3937 hysteresis = <2000>; 3938 type = "passive"; 3939 }; 3940 3941 cpu5_top_crit: cpu-crit { 3942 temperature = <110000>; 3943 hysteresis = <1000>; 3944 type = "critical"; 3945 }; 3946 }; 3947 3948 cooling-maps { 3949 map0 { 3950 trip = <&cpu5_top_alert0>; 3951 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3952 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3953 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3954 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3955 }; 3956 map1 { 3957 trip = <&cpu5_top_alert1>; 3958 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3959 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3960 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3962 }; 3963 }; 3964 }; 3965 3966 cpu6-top-thermal { 3967 polling-delay-passive = <250>; 3968 3969 thermal-sensors = <&tsens0 9>; 3970 3971 trips { 3972 cpu6_top_alert0: trip-point0 { 3973 temperature = <90000>; 3974 hysteresis = <2000>; 3975 type = "passive"; 3976 }; 3977 3978 cpu6_top_alert1: trip-point1 { 3979 temperature = <95000>; 3980 hysteresis = <2000>; 3981 type = "passive"; 3982 }; 3983 3984 cpu6_top_crit: cpu-crit { 3985 temperature = <110000>; 3986 hysteresis = <1000>; 3987 type = "critical"; 3988 }; 3989 }; 3990 3991 cooling-maps { 3992 map0 { 3993 trip = <&cpu6_top_alert0>; 3994 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3995 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3996 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3997 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3998 }; 3999 map1 { 4000 trip = <&cpu6_top_alert1>; 4001 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4002 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4003 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4004 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4005 }; 4006 }; 4007 }; 4008 4009 cpu7-top-thermal { 4010 polling-delay-passive = <250>; 4011 4012 thermal-sensors = <&tsens0 10>; 4013 4014 trips { 4015 cpu7_top_alert0: trip-point0 { 4016 temperature = <90000>; 4017 hysteresis = <2000>; 4018 type = "passive"; 4019 }; 4020 4021 cpu7_top_alert1: trip-point1 { 4022 temperature = <95000>; 4023 hysteresis = <2000>; 4024 type = "passive"; 4025 }; 4026 4027 cpu7_top_crit: cpu-crit { 4028 temperature = <110000>; 4029 hysteresis = <1000>; 4030 type = "critical"; 4031 }; 4032 }; 4033 4034 cooling-maps { 4035 map0 { 4036 trip = <&cpu7_top_alert0>; 4037 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4038 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4039 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4040 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4041 }; 4042 map1 { 4043 trip = <&cpu7_top_alert1>; 4044 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4045 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4046 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4047 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4048 }; 4049 }; 4050 }; 4051 4052 cpu4-bottom-thermal { 4053 polling-delay-passive = <250>; 4054 4055 thermal-sensors = <&tsens0 11>; 4056 4057 trips { 4058 cpu4_bottom_alert0: trip-point0 { 4059 temperature = <90000>; 4060 hysteresis = <2000>; 4061 type = "passive"; 4062 }; 4063 4064 cpu4_bottom_alert1: trip-point1 { 4065 temperature = <95000>; 4066 hysteresis = <2000>; 4067 type = "passive"; 4068 }; 4069 4070 cpu4_bottom_crit: cpu-crit { 4071 temperature = <110000>; 4072 hysteresis = <1000>; 4073 type = "critical"; 4074 }; 4075 }; 4076 4077 cooling-maps { 4078 map0 { 4079 trip = <&cpu4_bottom_alert0>; 4080 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4081 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4082 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4083 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4084 }; 4085 map1 { 4086 trip = <&cpu4_bottom_alert1>; 4087 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4088 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4089 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4090 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4091 }; 4092 }; 4093 }; 4094 4095 cpu5-bottom-thermal { 4096 polling-delay-passive = <250>; 4097 4098 thermal-sensors = <&tsens0 12>; 4099 4100 trips { 4101 cpu5_bottom_alert0: trip-point0 { 4102 temperature = <90000>; 4103 hysteresis = <2000>; 4104 type = "passive"; 4105 }; 4106 4107 cpu5_bottom_alert1: trip-point1 { 4108 temperature = <95000>; 4109 hysteresis = <2000>; 4110 type = "passive"; 4111 }; 4112 4113 cpu5_bottom_crit: cpu-crit { 4114 temperature = <110000>; 4115 hysteresis = <1000>; 4116 type = "critical"; 4117 }; 4118 }; 4119 4120 cooling-maps { 4121 map0 { 4122 trip = <&cpu5_bottom_alert0>; 4123 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4124 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4125 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4126 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4127 }; 4128 map1 { 4129 trip = <&cpu5_bottom_alert1>; 4130 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4131 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4132 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4133 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4134 }; 4135 }; 4136 }; 4137 4138 cpu6-bottom-thermal { 4139 polling-delay-passive = <250>; 4140 4141 thermal-sensors = <&tsens0 13>; 4142 4143 trips { 4144 cpu6_bottom_alert0: trip-point0 { 4145 temperature = <90000>; 4146 hysteresis = <2000>; 4147 type = "passive"; 4148 }; 4149 4150 cpu6_bottom_alert1: trip-point1 { 4151 temperature = <95000>; 4152 hysteresis = <2000>; 4153 type = "passive"; 4154 }; 4155 4156 cpu6_bottom_crit: cpu-crit { 4157 temperature = <110000>; 4158 hysteresis = <1000>; 4159 type = "critical"; 4160 }; 4161 }; 4162 4163 cooling-maps { 4164 map0 { 4165 trip = <&cpu6_bottom_alert0>; 4166 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4167 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4168 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4169 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4170 }; 4171 map1 { 4172 trip = <&cpu6_bottom_alert1>; 4173 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4174 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4175 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4176 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4177 }; 4178 }; 4179 }; 4180 4181 cpu7-bottom-thermal { 4182 polling-delay-passive = <250>; 4183 4184 thermal-sensors = <&tsens0 14>; 4185 4186 trips { 4187 cpu7_bottom_alert0: trip-point0 { 4188 temperature = <90000>; 4189 hysteresis = <2000>; 4190 type = "passive"; 4191 }; 4192 4193 cpu7_bottom_alert1: trip-point1 { 4194 temperature = <95000>; 4195 hysteresis = <2000>; 4196 type = "passive"; 4197 }; 4198 4199 cpu7_bottom_crit: cpu-crit { 4200 temperature = <110000>; 4201 hysteresis = <1000>; 4202 type = "critical"; 4203 }; 4204 }; 4205 4206 cooling-maps { 4207 map0 { 4208 trip = <&cpu7_bottom_alert0>; 4209 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4210 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4211 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4212 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4213 }; 4214 map1 { 4215 trip = <&cpu7_bottom_alert1>; 4216 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4217 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4218 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 4219 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4220 }; 4221 }; 4222 }; 4223 4224 aoss0-thermal { 4225 polling-delay-passive = <250>; 4226 4227 thermal-sensors = <&tsens0 0>; 4228 4229 trips { 4230 aoss0_alert0: trip-point0 { 4231 temperature = <90000>; 4232 hysteresis = <2000>; 4233 type = "hot"; 4234 }; 4235 }; 4236 }; 4237 4238 cluster0-thermal { 4239 polling-delay-passive = <250>; 4240 4241 thermal-sensors = <&tsens0 5>; 4242 4243 trips { 4244 cluster0_alert0: trip-point0 { 4245 temperature = <90000>; 4246 hysteresis = <2000>; 4247 type = "hot"; 4248 }; 4249 cluster0_crit: cluster0-crit { 4250 temperature = <110000>; 4251 hysteresis = <2000>; 4252 type = "critical"; 4253 }; 4254 }; 4255 }; 4256 4257 cluster1-thermal { 4258 polling-delay-passive = <250>; 4259 4260 thermal-sensors = <&tsens0 6>; 4261 4262 trips { 4263 cluster1_alert0: trip-point0 { 4264 temperature = <90000>; 4265 hysteresis = <2000>; 4266 type = "hot"; 4267 }; 4268 cluster1_crit: cluster1-crit { 4269 temperature = <110000>; 4270 hysteresis = <2000>; 4271 type = "critical"; 4272 }; 4273 }; 4274 }; 4275 4276 aoss1-thermal { 4277 polling-delay-passive = <250>; 4278 4279 thermal-sensors = <&tsens1 0>; 4280 4281 trips { 4282 aoss1_alert0: trip-point0 { 4283 temperature = <90000>; 4284 hysteresis = <2000>; 4285 type = "hot"; 4286 }; 4287 }; 4288 }; 4289 4290 gpu-top-thermal { 4291 polling-delay-passive = <250>; 4292 4293 thermal-sensors = <&tsens1 1>; 4294 4295 cooling-maps { 4296 map0 { 4297 trip = <&gpu_top_alert0>; 4298 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4299 }; 4300 }; 4301 4302 trips { 4303 gpu_top_alert0: trip-point0 { 4304 temperature = <85000>; 4305 hysteresis = <1000>; 4306 type = "passive"; 4307 }; 4308 4309 trip-point1 { 4310 temperature = <90000>; 4311 hysteresis = <1000>; 4312 type = "hot"; 4313 }; 4314 4315 trip-point2 { 4316 temperature = <110000>; 4317 hysteresis = <1000>; 4318 type = "critical"; 4319 }; 4320 }; 4321 }; 4322 4323 gpu-bottom-thermal { 4324 polling-delay-passive = <250>; 4325 4326 thermal-sensors = <&tsens1 2>; 4327 4328 cooling-maps { 4329 map0 { 4330 trip = <&gpu_bottom_alert0>; 4331 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 4332 }; 4333 }; 4334 4335 trips { 4336 gpu_bottom_alert0: trip-point0 { 4337 temperature = <85000>; 4338 hysteresis = <1000>; 4339 type = "passive"; 4340 }; 4341 4342 trip-point1 { 4343 temperature = <90000>; 4344 hysteresis = <1000>; 4345 type = "hot"; 4346 }; 4347 4348 trip-point2 { 4349 temperature = <110000>; 4350 hysteresis = <1000>; 4351 type = "critical"; 4352 }; 4353 }; 4354 }; 4355 4356 nspss1-thermal { 4357 polling-delay-passive = <250>; 4358 4359 thermal-sensors = <&tsens1 3>; 4360 4361 trips { 4362 nspss1_alert0: trip-point0 { 4363 temperature = <90000>; 4364 hysteresis = <1000>; 4365 type = "hot"; 4366 }; 4367 }; 4368 }; 4369 4370 nspss2-thermal { 4371 polling-delay-passive = <250>; 4372 4373 thermal-sensors = <&tsens1 4>; 4374 4375 trips { 4376 nspss2_alert0: trip-point0 { 4377 temperature = <90000>; 4378 hysteresis = <1000>; 4379 type = "hot"; 4380 }; 4381 }; 4382 }; 4383 4384 nspss3-thermal { 4385 polling-delay-passive = <250>; 4386 4387 thermal-sensors = <&tsens1 5>; 4388 4389 trips { 4390 nspss3_alert0: trip-point0 { 4391 temperature = <90000>; 4392 hysteresis = <1000>; 4393 type = "hot"; 4394 }; 4395 }; 4396 }; 4397 4398 video-thermal { 4399 polling-delay-passive = <250>; 4400 4401 thermal-sensors = <&tsens1 6>; 4402 4403 trips { 4404 video_alert0: trip-point0 { 4405 temperature = <90000>; 4406 hysteresis = <2000>; 4407 type = "hot"; 4408 }; 4409 }; 4410 }; 4411 4412 mem-thermal { 4413 polling-delay-passive = <250>; 4414 4415 thermal-sensors = <&tsens1 7>; 4416 4417 trips { 4418 mem_alert0: trip-point0 { 4419 temperature = <90000>; 4420 hysteresis = <2000>; 4421 type = "hot"; 4422 }; 4423 }; 4424 }; 4425 4426 modem1-top-thermal { 4427 polling-delay-passive = <250>; 4428 4429 thermal-sensors = <&tsens1 8>; 4430 4431 trips { 4432 modem1_alert0: trip-point0 { 4433 temperature = <90000>; 4434 hysteresis = <2000>; 4435 type = "hot"; 4436 }; 4437 }; 4438 }; 4439 4440 modem2-top-thermal { 4441 polling-delay-passive = <250>; 4442 4443 thermal-sensors = <&tsens1 9>; 4444 4445 trips { 4446 modem2_alert0: trip-point0 { 4447 temperature = <90000>; 4448 hysteresis = <2000>; 4449 type = "hot"; 4450 }; 4451 }; 4452 }; 4453 4454 modem3-top-thermal { 4455 polling-delay-passive = <250>; 4456 4457 thermal-sensors = <&tsens1 10>; 4458 4459 trips { 4460 modem3_alert0: trip-point0 { 4461 temperature = <90000>; 4462 hysteresis = <2000>; 4463 type = "hot"; 4464 }; 4465 }; 4466 }; 4467 4468 modem4-top-thermal { 4469 polling-delay-passive = <250>; 4470 4471 thermal-sensors = <&tsens1 11>; 4472 4473 trips { 4474 modem4_alert0: trip-point0 { 4475 temperature = <90000>; 4476 hysteresis = <2000>; 4477 type = "hot"; 4478 }; 4479 }; 4480 }; 4481 4482 camera-top-thermal { 4483 polling-delay-passive = <250>; 4484 4485 thermal-sensors = <&tsens1 12>; 4486 4487 trips { 4488 camera1_alert0: trip-point0 { 4489 temperature = <90000>; 4490 hysteresis = <2000>; 4491 type = "hot"; 4492 }; 4493 }; 4494 }; 4495 4496 cam-bottom-thermal { 4497 polling-delay-passive = <250>; 4498 4499 thermal-sensors = <&tsens1 13>; 4500 4501 trips { 4502 camera2_alert0: trip-point0 { 4503 temperature = <90000>; 4504 hysteresis = <2000>; 4505 type = "hot"; 4506 }; 4507 }; 4508 }; 4509 }; 4510 4511 timer { 4512 compatible = "arm,armv8-timer"; 4513 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4514 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4515 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4516 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4517 }; 4518}; 4519