1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,dispcc-sm8250.h> 8#include <dt-bindings/clock/qcom,gcc-sm8250.h> 9#include <dt-bindings/clock/qcom,gpucc-sm8250.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/dma/qcom-gpi.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sm8250.h> 15#include <dt-bindings/mailbox/qcom-ipcc.h> 16#include <dt-bindings/phy/phy-qcom-qmp.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/power/qcom,rpmhpd.h> 19#include <dt-bindings/soc/qcom,apr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23#include <dt-bindings/clock/qcom,camcc-sm8250.h> 24#include <dt-bindings/clock/qcom,videocc-sm8250.h> 25 26/ { 27 interrupt-parent = <&intc>; 28 29 #address-cells = <2>; 30 #size-cells = <2>; 31 32 aliases { 33 i2c0 = &i2c0; 34 i2c1 = &i2c1; 35 i2c2 = &i2c2; 36 i2c3 = &i2c3; 37 i2c4 = &i2c4; 38 i2c5 = &i2c5; 39 i2c6 = &i2c6; 40 i2c7 = &i2c7; 41 i2c8 = &i2c8; 42 i2c9 = &i2c9; 43 i2c10 = &i2c10; 44 i2c11 = &i2c11; 45 i2c12 = &i2c12; 46 i2c13 = &i2c13; 47 i2c14 = &i2c14; 48 i2c15 = &i2c15; 49 i2c16 = &i2c16; 50 i2c17 = &i2c17; 51 i2c18 = &i2c18; 52 i2c19 = &i2c19; 53 spi0 = &spi0; 54 spi1 = &spi1; 55 spi2 = &spi2; 56 spi3 = &spi3; 57 spi4 = &spi4; 58 spi5 = &spi5; 59 spi6 = &spi6; 60 spi7 = &spi7; 61 spi8 = &spi8; 62 spi9 = &spi9; 63 spi10 = &spi10; 64 spi11 = &spi11; 65 spi12 = &spi12; 66 spi13 = &spi13; 67 spi14 = &spi14; 68 spi15 = &spi15; 69 spi16 = &spi16; 70 spi17 = &spi17; 71 spi18 = &spi18; 72 spi19 = &spi19; 73 }; 74 75 chosen { }; 76 77 clocks { 78 xo_board: xo-board { 79 compatible = "fixed-clock"; 80 #clock-cells = <0>; 81 clock-frequency = <38400000>; 82 clock-output-names = "xo_board"; 83 }; 84 85 sleep_clk: sleep-clk { 86 compatible = "fixed-clock"; 87 clock-frequency = <32764>; 88 #clock-cells = <0>; 89 }; 90 }; 91 92 cpus { 93 #address-cells = <2>; 94 #size-cells = <0>; 95 96 cpu0: cpu@0 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo485"; 99 reg = <0x0 0x0>; 100 clocks = <&cpufreq_hw 0>; 101 enable-method = "psci"; 102 capacity-dmips-mhz = <448>; 103 dynamic-power-coefficient = <105>; 104 next-level-cache = <&l2_0>; 105 power-domains = <&cpu_pd0>; 106 power-domain-names = "psci"; 107 qcom,freq-domain = <&cpufreq_hw 0>; 108 operating-points-v2 = <&cpu0_opp_table>; 109 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 110 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 111 #cooling-cells = <2>; 112 l2_0: l2-cache { 113 compatible = "cache"; 114 cache-level = <2>; 115 cache-size = <0x20000>; 116 cache-unified; 117 next-level-cache = <&l3_0>; 118 l3_0: l3-cache { 119 compatible = "cache"; 120 cache-level = <3>; 121 cache-size = <0x400000>; 122 cache-unified; 123 }; 124 }; 125 }; 126 127 cpu1: cpu@100 { 128 device_type = "cpu"; 129 compatible = "qcom,kryo485"; 130 reg = <0x0 0x100>; 131 clocks = <&cpufreq_hw 0>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <448>; 134 dynamic-power-coefficient = <105>; 135 next-level-cache = <&l2_100>; 136 power-domains = <&cpu_pd1>; 137 power-domain-names = "psci"; 138 qcom,freq-domain = <&cpufreq_hw 0>; 139 operating-points-v2 = <&cpu0_opp_table>; 140 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 141 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 142 #cooling-cells = <2>; 143 l2_100: l2-cache { 144 compatible = "cache"; 145 cache-level = <2>; 146 cache-size = <0x20000>; 147 cache-unified; 148 next-level-cache = <&l3_0>; 149 }; 150 }; 151 152 cpu2: cpu@200 { 153 device_type = "cpu"; 154 compatible = "qcom,kryo485"; 155 reg = <0x0 0x200>; 156 clocks = <&cpufreq_hw 0>; 157 enable-method = "psci"; 158 capacity-dmips-mhz = <448>; 159 dynamic-power-coefficient = <105>; 160 next-level-cache = <&l2_200>; 161 power-domains = <&cpu_pd2>; 162 power-domain-names = "psci"; 163 qcom,freq-domain = <&cpufreq_hw 0>; 164 operating-points-v2 = <&cpu0_opp_table>; 165 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 166 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 167 #cooling-cells = <2>; 168 l2_200: l2-cache { 169 compatible = "cache"; 170 cache-level = <2>; 171 cache-size = <0x20000>; 172 cache-unified; 173 next-level-cache = <&l3_0>; 174 }; 175 }; 176 177 cpu3: cpu@300 { 178 device_type = "cpu"; 179 compatible = "qcom,kryo485"; 180 reg = <0x0 0x300>; 181 clocks = <&cpufreq_hw 0>; 182 enable-method = "psci"; 183 capacity-dmips-mhz = <448>; 184 dynamic-power-coefficient = <105>; 185 next-level-cache = <&l2_300>; 186 power-domains = <&cpu_pd3>; 187 power-domain-names = "psci"; 188 qcom,freq-domain = <&cpufreq_hw 0>; 189 operating-points-v2 = <&cpu0_opp_table>; 190 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 191 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 192 #cooling-cells = <2>; 193 l2_300: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-size = <0x20000>; 197 cache-unified; 198 next-level-cache = <&l3_0>; 199 }; 200 }; 201 202 cpu4: cpu@400 { 203 device_type = "cpu"; 204 compatible = "qcom,kryo485"; 205 reg = <0x0 0x400>; 206 clocks = <&cpufreq_hw 1>; 207 enable-method = "psci"; 208 capacity-dmips-mhz = <1024>; 209 dynamic-power-coefficient = <379>; 210 next-level-cache = <&l2_400>; 211 power-domains = <&cpu_pd4>; 212 power-domain-names = "psci"; 213 qcom,freq-domain = <&cpufreq_hw 1>; 214 operating-points-v2 = <&cpu4_opp_table>; 215 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 216 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 217 #cooling-cells = <2>; 218 l2_400: l2-cache { 219 compatible = "cache"; 220 cache-level = <2>; 221 cache-size = <0x40000>; 222 cache-unified; 223 next-level-cache = <&l3_0>; 224 }; 225 }; 226 227 cpu5: cpu@500 { 228 device_type = "cpu"; 229 compatible = "qcom,kryo485"; 230 reg = <0x0 0x500>; 231 clocks = <&cpufreq_hw 1>; 232 enable-method = "psci"; 233 capacity-dmips-mhz = <1024>; 234 dynamic-power-coefficient = <379>; 235 next-level-cache = <&l2_500>; 236 power-domains = <&cpu_pd5>; 237 power-domain-names = "psci"; 238 qcom,freq-domain = <&cpufreq_hw 1>; 239 operating-points-v2 = <&cpu4_opp_table>; 240 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 241 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 242 #cooling-cells = <2>; 243 l2_500: l2-cache { 244 compatible = "cache"; 245 cache-level = <2>; 246 cache-size = <0x40000>; 247 cache-unified; 248 next-level-cache = <&l3_0>; 249 }; 250 }; 251 252 cpu6: cpu@600 { 253 device_type = "cpu"; 254 compatible = "qcom,kryo485"; 255 reg = <0x0 0x600>; 256 clocks = <&cpufreq_hw 1>; 257 enable-method = "psci"; 258 capacity-dmips-mhz = <1024>; 259 dynamic-power-coefficient = <379>; 260 next-level-cache = <&l2_600>; 261 power-domains = <&cpu_pd6>; 262 power-domain-names = "psci"; 263 qcom,freq-domain = <&cpufreq_hw 1>; 264 operating-points-v2 = <&cpu4_opp_table>; 265 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 266 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 267 #cooling-cells = <2>; 268 l2_600: l2-cache { 269 compatible = "cache"; 270 cache-level = <2>; 271 cache-size = <0x40000>; 272 cache-unified; 273 next-level-cache = <&l3_0>; 274 }; 275 }; 276 277 cpu7: cpu@700 { 278 device_type = "cpu"; 279 compatible = "qcom,kryo485"; 280 reg = <0x0 0x700>; 281 clocks = <&cpufreq_hw 2>; 282 enable-method = "psci"; 283 capacity-dmips-mhz = <1024>; 284 dynamic-power-coefficient = <444>; 285 next-level-cache = <&l2_700>; 286 power-domains = <&cpu_pd7>; 287 power-domain-names = "psci"; 288 qcom,freq-domain = <&cpufreq_hw 2>; 289 operating-points-v2 = <&cpu7_opp_table>; 290 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>, 291 <&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>; 292 #cooling-cells = <2>; 293 l2_700: l2-cache { 294 compatible = "cache"; 295 cache-level = <2>; 296 cache-size = <0x80000>; 297 cache-unified; 298 next-level-cache = <&l3_0>; 299 }; 300 }; 301 302 cpu-map { 303 cluster0 { 304 core0 { 305 cpu = <&cpu0>; 306 }; 307 308 core1 { 309 cpu = <&cpu1>; 310 }; 311 312 core2 { 313 cpu = <&cpu2>; 314 }; 315 316 core3 { 317 cpu = <&cpu3>; 318 }; 319 320 core4 { 321 cpu = <&cpu4>; 322 }; 323 324 core5 { 325 cpu = <&cpu5>; 326 }; 327 328 core6 { 329 cpu = <&cpu6>; 330 }; 331 332 core7 { 333 cpu = <&cpu7>; 334 }; 335 }; 336 }; 337 338 idle-states { 339 entry-method = "psci"; 340 341 little_cpu_sleep_0: cpu-sleep-0-0 { 342 compatible = "arm,idle-state"; 343 idle-state-name = "silver-rail-power-collapse"; 344 arm,psci-suspend-param = <0x40000004>; 345 entry-latency-us = <360>; 346 exit-latency-us = <531>; 347 min-residency-us = <3934>; 348 local-timer-stop; 349 }; 350 351 big_cpu_sleep_0: cpu-sleep-1-0 { 352 compatible = "arm,idle-state"; 353 idle-state-name = "gold-rail-power-collapse"; 354 arm,psci-suspend-param = <0x40000004>; 355 entry-latency-us = <702>; 356 exit-latency-us = <1061>; 357 min-residency-us = <4488>; 358 local-timer-stop; 359 }; 360 }; 361 362 domain-idle-states { 363 cluster_sleep_0: cluster-sleep-0 { 364 compatible = "domain-idle-state"; 365 arm,psci-suspend-param = <0x4100c244>; 366 entry-latency-us = <3264>; 367 exit-latency-us = <6562>; 368 min-residency-us = <9987>; 369 }; 370 }; 371 }; 372 373 qup_virt: interconnect-qup-virt { 374 compatible = "qcom,sm8250-qup-virt"; 375 #interconnect-cells = <2>; 376 qcom,bcm-voters = <&apps_bcm_voter>; 377 }; 378 379 cpu0_opp_table: opp-table-cpu0 { 380 compatible = "operating-points-v2"; 381 opp-shared; 382 383 cpu0_opp1: opp-300000000 { 384 opp-hz = /bits/ 64 <300000000>; 385 opp-peak-kBps = <800000 9600000>; 386 }; 387 388 cpu0_opp2: opp-403200000 { 389 opp-hz = /bits/ 64 <403200000>; 390 opp-peak-kBps = <800000 9600000>; 391 }; 392 393 cpu0_opp3: opp-518400000 { 394 opp-hz = /bits/ 64 <518400000>; 395 opp-peak-kBps = <800000 16588800>; 396 }; 397 398 cpu0_opp4: opp-614400000 { 399 opp-hz = /bits/ 64 <614400000>; 400 opp-peak-kBps = <800000 16588800>; 401 }; 402 403 cpu0_opp5: opp-691200000 { 404 opp-hz = /bits/ 64 <691200000>; 405 opp-peak-kBps = <800000 19660800>; 406 }; 407 408 cpu0_opp6: opp-787200000 { 409 opp-hz = /bits/ 64 <787200000>; 410 opp-peak-kBps = <1804000 19660800>; 411 }; 412 413 cpu0_opp7: opp-883200000 { 414 opp-hz = /bits/ 64 <883200000>; 415 opp-peak-kBps = <1804000 23347200>; 416 }; 417 418 cpu0_opp8: opp-979200000 { 419 opp-hz = /bits/ 64 <979200000>; 420 opp-peak-kBps = <1804000 26419200>; 421 }; 422 423 cpu0_opp9: opp-1075200000 { 424 opp-hz = /bits/ 64 <1075200000>; 425 opp-peak-kBps = <1804000 29491200>; 426 }; 427 428 cpu0_opp10: opp-1171200000 { 429 opp-hz = /bits/ 64 <1171200000>; 430 opp-peak-kBps = <1804000 32563200>; 431 }; 432 433 cpu0_opp11: opp-1248000000 { 434 opp-hz = /bits/ 64 <1248000000>; 435 opp-peak-kBps = <1804000 36249600>; 436 }; 437 438 cpu0_opp12: opp-1344000000 { 439 opp-hz = /bits/ 64 <1344000000>; 440 opp-peak-kBps = <2188000 36249600>; 441 }; 442 443 cpu0_opp13: opp-1420800000 { 444 opp-hz = /bits/ 64 <1420800000>; 445 opp-peak-kBps = <2188000 39321600>; 446 }; 447 448 cpu0_opp14: opp-1516800000 { 449 opp-hz = /bits/ 64 <1516800000>; 450 opp-peak-kBps = <3072000 42393600>; 451 }; 452 453 cpu0_opp15: opp-1612800000 { 454 opp-hz = /bits/ 64 <1612800000>; 455 opp-peak-kBps = <3072000 42393600>; 456 }; 457 458 cpu0_opp16: opp-1708800000 { 459 opp-hz = /bits/ 64 <1708800000>; 460 opp-peak-kBps = <4068000 42393600>; 461 }; 462 463 cpu0_opp17: opp-1804800000 { 464 opp-hz = /bits/ 64 <1804800000>; 465 opp-peak-kBps = <4068000 42393600>; 466 }; 467 }; 468 469 cpu4_opp_table: opp-table-cpu4 { 470 compatible = "operating-points-v2"; 471 opp-shared; 472 473 cpu4_opp1: opp-710400000 { 474 opp-hz = /bits/ 64 <710400000>; 475 opp-peak-kBps = <1804000 19660800>; 476 }; 477 478 cpu4_opp2: opp-825600000 { 479 opp-hz = /bits/ 64 <825600000>; 480 opp-peak-kBps = <2188000 23347200>; 481 }; 482 483 cpu4_opp3: opp-940800000 { 484 opp-hz = /bits/ 64 <940800000>; 485 opp-peak-kBps = <2188000 26419200>; 486 }; 487 488 cpu4_opp4: opp-1056000000 { 489 opp-hz = /bits/ 64 <1056000000>; 490 opp-peak-kBps = <3072000 26419200>; 491 }; 492 493 cpu4_opp5: opp-1171200000 { 494 opp-hz = /bits/ 64 <1171200000>; 495 opp-peak-kBps = <3072000 29491200>; 496 }; 497 498 cpu4_opp6: opp-1286400000 { 499 opp-hz = /bits/ 64 <1286400000>; 500 opp-peak-kBps = <4068000 29491200>; 501 }; 502 503 cpu4_opp7: opp-1382400000 { 504 opp-hz = /bits/ 64 <1382400000>; 505 opp-peak-kBps = <4068000 32563200>; 506 }; 507 508 cpu4_opp8: opp-1478400000 { 509 opp-hz = /bits/ 64 <1478400000>; 510 opp-peak-kBps = <4068000 32563200>; 511 }; 512 513 cpu4_opp9: opp-1574400000 { 514 opp-hz = /bits/ 64 <1574400000>; 515 opp-peak-kBps = <5412000 39321600>; 516 }; 517 518 cpu4_opp10: opp-1670400000 { 519 opp-hz = /bits/ 64 <1670400000>; 520 opp-peak-kBps = <5412000 42393600>; 521 }; 522 523 cpu4_opp11: opp-1766400000 { 524 opp-hz = /bits/ 64 <1766400000>; 525 opp-peak-kBps = <5412000 45465600>; 526 }; 527 528 cpu4_opp12: opp-1862400000 { 529 opp-hz = /bits/ 64 <1862400000>; 530 opp-peak-kBps = <6220000 45465600>; 531 }; 532 533 cpu4_opp13: opp-1958400000 { 534 opp-hz = /bits/ 64 <1958400000>; 535 opp-peak-kBps = <6220000 48537600>; 536 }; 537 538 cpu4_opp14: opp-2054400000 { 539 opp-hz = /bits/ 64 <2054400000>; 540 opp-peak-kBps = <7216000 48537600>; 541 }; 542 543 cpu4_opp15: opp-2150400000 { 544 opp-hz = /bits/ 64 <2150400000>; 545 opp-peak-kBps = <7216000 51609600>; 546 }; 547 548 cpu4_opp16: opp-2246400000 { 549 opp-hz = /bits/ 64 <2246400000>; 550 opp-peak-kBps = <7216000 51609600>; 551 }; 552 553 cpu4_opp17: opp-2342400000 { 554 opp-hz = /bits/ 64 <2342400000>; 555 opp-peak-kBps = <8368000 51609600>; 556 }; 557 558 cpu4_opp18: opp-2419200000 { 559 opp-hz = /bits/ 64 <2419200000>; 560 opp-peak-kBps = <8368000 51609600>; 561 }; 562 }; 563 564 cpu7_opp_table: opp-table-cpu7 { 565 compatible = "operating-points-v2"; 566 opp-shared; 567 568 cpu7_opp1: opp-844800000 { 569 opp-hz = /bits/ 64 <844800000>; 570 opp-peak-kBps = <2188000 19660800>; 571 }; 572 573 cpu7_opp2: opp-960000000 { 574 opp-hz = /bits/ 64 <960000000>; 575 opp-peak-kBps = <2188000 26419200>; 576 }; 577 578 cpu7_opp3: opp-1075200000 { 579 opp-hz = /bits/ 64 <1075200000>; 580 opp-peak-kBps = <3072000 26419200>; 581 }; 582 583 cpu7_opp4: opp-1190400000 { 584 opp-hz = /bits/ 64 <1190400000>; 585 opp-peak-kBps = <3072000 29491200>; 586 }; 587 588 cpu7_opp5: opp-1305600000 { 589 opp-hz = /bits/ 64 <1305600000>; 590 opp-peak-kBps = <4068000 32563200>; 591 }; 592 593 cpu7_opp6: opp-1401600000 { 594 opp-hz = /bits/ 64 <1401600000>; 595 opp-peak-kBps = <4068000 32563200>; 596 }; 597 598 cpu7_opp7: opp-1516800000 { 599 opp-hz = /bits/ 64 <1516800000>; 600 opp-peak-kBps = <4068000 36249600>; 601 }; 602 603 cpu7_opp8: opp-1632000000 { 604 opp-hz = /bits/ 64 <1632000000>; 605 opp-peak-kBps = <5412000 39321600>; 606 }; 607 608 cpu7_opp9: opp-1747200000 { 609 opp-hz = /bits/ 64 <1708800000>; 610 opp-peak-kBps = <5412000 42393600>; 611 }; 612 613 cpu7_opp10: opp-1862400000 { 614 opp-hz = /bits/ 64 <1862400000>; 615 opp-peak-kBps = <6220000 45465600>; 616 }; 617 618 cpu7_opp11: opp-1977600000 { 619 opp-hz = /bits/ 64 <1977600000>; 620 opp-peak-kBps = <6220000 48537600>; 621 }; 622 623 cpu7_opp12: opp-2073600000 { 624 opp-hz = /bits/ 64 <2073600000>; 625 opp-peak-kBps = <7216000 48537600>; 626 }; 627 628 cpu7_opp13: opp-2169600000 { 629 opp-hz = /bits/ 64 <2169600000>; 630 opp-peak-kBps = <7216000 51609600>; 631 }; 632 633 cpu7_opp14: opp-2265600000 { 634 opp-hz = /bits/ 64 <2265600000>; 635 opp-peak-kBps = <7216000 51609600>; 636 }; 637 638 cpu7_opp15: opp-2361600000 { 639 opp-hz = /bits/ 64 <2361600000>; 640 opp-peak-kBps = <8368000 51609600>; 641 }; 642 643 cpu7_opp16: opp-2457600000 { 644 opp-hz = /bits/ 64 <2457600000>; 645 opp-peak-kBps = <8368000 51609600>; 646 }; 647 648 cpu7_opp17: opp-2553600000 { 649 opp-hz = /bits/ 64 <2553600000>; 650 opp-peak-kBps = <8368000 51609600>; 651 }; 652 653 cpu7_opp18: opp-2649600000 { 654 opp-hz = /bits/ 64 <2649600000>; 655 opp-peak-kBps = <8368000 51609600>; 656 }; 657 658 cpu7_opp19: opp-2745600000 { 659 opp-hz = /bits/ 64 <2745600000>; 660 opp-peak-kBps = <8368000 51609600>; 661 }; 662 663 cpu7_opp20: opp-2841600000 { 664 opp-hz = /bits/ 64 <2841600000>; 665 opp-peak-kBps = <8368000 51609600>; 666 }; 667 }; 668 669 firmware { 670 scm: scm { 671 compatible = "qcom,scm-sm8250", "qcom,scm"; 672 qcom,dload-mode = <&tcsr 0x13000>; 673 #reset-cells = <1>; 674 }; 675 }; 676 677 memory@80000000 { 678 device_type = "memory"; 679 /* We expect the bootloader to fill in the size */ 680 reg = <0x0 0x80000000 0x0 0x0>; 681 }; 682 683 pmu { 684 compatible = "arm,armv8-pmuv3"; 685 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 686 }; 687 688 psci { 689 compatible = "arm,psci-1.0"; 690 method = "smc"; 691 692 cpu_pd0: power-domain-cpu0 { 693 #power-domain-cells = <0>; 694 power-domains = <&cluster_pd>; 695 domain-idle-states = <&little_cpu_sleep_0>; 696 }; 697 698 cpu_pd1: power-domain-cpu1 { 699 #power-domain-cells = <0>; 700 power-domains = <&cluster_pd>; 701 domain-idle-states = <&little_cpu_sleep_0>; 702 }; 703 704 cpu_pd2: power-domain-cpu2 { 705 #power-domain-cells = <0>; 706 power-domains = <&cluster_pd>; 707 domain-idle-states = <&little_cpu_sleep_0>; 708 }; 709 710 cpu_pd3: power-domain-cpu3 { 711 #power-domain-cells = <0>; 712 power-domains = <&cluster_pd>; 713 domain-idle-states = <&little_cpu_sleep_0>; 714 }; 715 716 cpu_pd4: power-domain-cpu4 { 717 #power-domain-cells = <0>; 718 power-domains = <&cluster_pd>; 719 domain-idle-states = <&big_cpu_sleep_0>; 720 }; 721 722 cpu_pd5: power-domain-cpu5 { 723 #power-domain-cells = <0>; 724 power-domains = <&cluster_pd>; 725 domain-idle-states = <&big_cpu_sleep_0>; 726 }; 727 728 cpu_pd6: power-domain-cpu6 { 729 #power-domain-cells = <0>; 730 power-domains = <&cluster_pd>; 731 domain-idle-states = <&big_cpu_sleep_0>; 732 }; 733 734 cpu_pd7: power-domain-cpu7 { 735 #power-domain-cells = <0>; 736 power-domains = <&cluster_pd>; 737 domain-idle-states = <&big_cpu_sleep_0>; 738 }; 739 740 cluster_pd: power-domain-cpu-cluster0 { 741 #power-domain-cells = <0>; 742 domain-idle-states = <&cluster_sleep_0>; 743 }; 744 }; 745 746 qup_opp_table: opp-table-qup { 747 compatible = "operating-points-v2"; 748 749 opp-50000000 { 750 opp-hz = /bits/ 64 <50000000>; 751 required-opps = <&rpmhpd_opp_min_svs>; 752 }; 753 754 opp-75000000 { 755 opp-hz = /bits/ 64 <75000000>; 756 required-opps = <&rpmhpd_opp_low_svs>; 757 }; 758 759 opp-120000000 { 760 opp-hz = /bits/ 64 <120000000>; 761 required-opps = <&rpmhpd_opp_svs>; 762 }; 763 }; 764 765 reserved-memory { 766 #address-cells = <2>; 767 #size-cells = <2>; 768 ranges; 769 770 hyp_mem: memory@80000000 { 771 reg = <0x0 0x80000000 0x0 0x600000>; 772 no-map; 773 }; 774 775 xbl_aop_mem: memory@80700000 { 776 reg = <0x0 0x80700000 0x0 0x160000>; 777 no-map; 778 }; 779 780 cmd_db: memory@80860000 { 781 compatible = "qcom,cmd-db"; 782 reg = <0x0 0x80860000 0x0 0x20000>; 783 no-map; 784 }; 785 786 smem_mem: memory@80900000 { 787 reg = <0x0 0x80900000 0x0 0x200000>; 788 no-map; 789 }; 790 791 removed_mem: memory@80b00000 { 792 reg = <0x0 0x80b00000 0x0 0x5300000>; 793 no-map; 794 }; 795 796 camera_mem: memory@86200000 { 797 reg = <0x0 0x86200000 0x0 0x500000>; 798 no-map; 799 }; 800 801 wlan_mem: memory@86700000 { 802 reg = <0x0 0x86700000 0x0 0x100000>; 803 no-map; 804 }; 805 806 ipa_fw_mem: memory@86800000 { 807 reg = <0x0 0x86800000 0x0 0x10000>; 808 no-map; 809 }; 810 811 ipa_gsi_mem: memory@86810000 { 812 reg = <0x0 0x86810000 0x0 0xa000>; 813 no-map; 814 }; 815 816 gpu_mem: memory@8681a000 { 817 reg = <0x0 0x8681a000 0x0 0x2000>; 818 no-map; 819 }; 820 821 npu_mem: memory@86900000 { 822 reg = <0x0 0x86900000 0x0 0x500000>; 823 no-map; 824 }; 825 826 video_mem: memory@86e00000 { 827 reg = <0x0 0x86e00000 0x0 0x500000>; 828 no-map; 829 }; 830 831 cvp_mem: memory@87300000 { 832 reg = <0x0 0x87300000 0x0 0x500000>; 833 no-map; 834 }; 835 836 cdsp_mem: memory@87800000 { 837 reg = <0x0 0x87800000 0x0 0x1400000>; 838 no-map; 839 }; 840 841 slpi_mem: memory@88c00000 { 842 reg = <0x0 0x88c00000 0x0 0x1500000>; 843 no-map; 844 }; 845 846 adsp_mem: memory@8a100000 { 847 reg = <0x0 0x8a100000 0x0 0x1d00000>; 848 no-map; 849 }; 850 851 spss_mem: memory@8be00000 { 852 reg = <0x0 0x8be00000 0x0 0x100000>; 853 no-map; 854 }; 855 856 cdsp_secure_heap: memory@8bf00000 { 857 reg = <0x0 0x8bf00000 0x0 0x4600000>; 858 no-map; 859 }; 860 }; 861 862 smem { 863 compatible = "qcom,smem"; 864 memory-region = <&smem_mem>; 865 hwlocks = <&tcsr_mutex 3>; 866 }; 867 868 smp2p-adsp { 869 compatible = "qcom,smp2p"; 870 qcom,smem = <443>, <429>; 871 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 872 IPCC_MPROC_SIGNAL_SMP2P 873 IRQ_TYPE_EDGE_RISING>; 874 mboxes = <&ipcc IPCC_CLIENT_LPASS 875 IPCC_MPROC_SIGNAL_SMP2P>; 876 877 qcom,local-pid = <0>; 878 qcom,remote-pid = <2>; 879 880 smp2p_adsp_out: master-kernel { 881 qcom,entry-name = "master-kernel"; 882 #qcom,smem-state-cells = <1>; 883 }; 884 885 smp2p_adsp_in: slave-kernel { 886 qcom,entry-name = "slave-kernel"; 887 interrupt-controller; 888 #interrupt-cells = <2>; 889 }; 890 }; 891 892 smp2p-cdsp { 893 compatible = "qcom,smp2p"; 894 qcom,smem = <94>, <432>; 895 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 896 IPCC_MPROC_SIGNAL_SMP2P 897 IRQ_TYPE_EDGE_RISING>; 898 mboxes = <&ipcc IPCC_CLIENT_CDSP 899 IPCC_MPROC_SIGNAL_SMP2P>; 900 901 qcom,local-pid = <0>; 902 qcom,remote-pid = <5>; 903 904 smp2p_cdsp_out: master-kernel { 905 qcom,entry-name = "master-kernel"; 906 #qcom,smem-state-cells = <1>; 907 }; 908 909 smp2p_cdsp_in: slave-kernel { 910 qcom,entry-name = "slave-kernel"; 911 interrupt-controller; 912 #interrupt-cells = <2>; 913 }; 914 }; 915 916 smp2p-slpi { 917 compatible = "qcom,smp2p"; 918 qcom,smem = <481>, <430>; 919 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 920 IPCC_MPROC_SIGNAL_SMP2P 921 IRQ_TYPE_EDGE_RISING>; 922 mboxes = <&ipcc IPCC_CLIENT_SLPI 923 IPCC_MPROC_SIGNAL_SMP2P>; 924 925 qcom,local-pid = <0>; 926 qcom,remote-pid = <3>; 927 928 smp2p_slpi_out: master-kernel { 929 qcom,entry-name = "master-kernel"; 930 #qcom,smem-state-cells = <1>; 931 }; 932 933 smp2p_slpi_in: slave-kernel { 934 qcom,entry-name = "slave-kernel"; 935 interrupt-controller; 936 #interrupt-cells = <2>; 937 }; 938 }; 939 940 soc: soc@0 { 941 #address-cells = <2>; 942 #size-cells = <2>; 943 ranges = <0 0 0 0 0x10 0>; 944 dma-ranges = <0 0 0 0 0x10 0>; 945 compatible = "simple-bus"; 946 947 gcc: clock-controller@100000 { 948 compatible = "qcom,gcc-sm8250"; 949 reg = <0x0 0x00100000 0x0 0x1f0000>; 950 #clock-cells = <1>; 951 #reset-cells = <1>; 952 #power-domain-cells = <1>; 953 clock-names = "bi_tcxo", 954 "bi_tcxo_ao", 955 "sleep_clk"; 956 clocks = <&rpmhcc RPMH_CXO_CLK>, 957 <&rpmhcc RPMH_CXO_CLK_A>, 958 <&sleep_clk>; 959 }; 960 961 ipcc: mailbox@408000 { 962 compatible = "qcom,sm8250-ipcc", "qcom,ipcc"; 963 reg = <0 0x00408000 0 0x1000>; 964 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 965 interrupt-controller; 966 #interrupt-cells = <3>; 967 #mbox-cells = <2>; 968 }; 969 970 qfprom: efuse@784000 { 971 compatible = "qcom,sm8250-qfprom", "qcom,qfprom"; 972 reg = <0 0x00784000 0 0x8ff>; 973 #address-cells = <1>; 974 #size-cells = <1>; 975 976 gpu_speed_bin: gpu-speed-bin@19b { 977 reg = <0x19b 0x1>; 978 bits = <5 3>; 979 }; 980 }; 981 982 rng: rng@793000 { 983 compatible = "qcom,prng-ee"; 984 reg = <0 0x00793000 0 0x1000>; 985 clocks = <&gcc GCC_PRNG_AHB_CLK>; 986 clock-names = "core"; 987 }; 988 989 gpi_dma2: dma-controller@800000 { 990 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 991 reg = <0 0x00800000 0 0x70000>; 992 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 994 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 995 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 996 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 998 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 999 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1000 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1001 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 1002 dma-channels = <10>; 1003 dma-channel-mask = <0x3f>; 1004 iommus = <&apps_smmu 0x76 0x0>; 1005 #dma-cells = <3>; 1006 status = "disabled"; 1007 }; 1008 1009 qupv3_id_2: geniqup@8c0000 { 1010 compatible = "qcom,geni-se-qup"; 1011 reg = <0x0 0x008c0000 0x0 0x6000>; 1012 clock-names = "m-ahb", "s-ahb"; 1013 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 1014 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 1015 #address-cells = <2>; 1016 #size-cells = <2>; 1017 iommus = <&apps_smmu 0x63 0x0>; 1018 ranges; 1019 status = "disabled"; 1020 1021 i2c14: i2c@880000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0 0x00880000 0 0x4000>; 1024 clock-names = "se"; 1025 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&qup_i2c14_default>; 1028 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1029 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 1030 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 1031 dma-names = "tx", "rx"; 1032 power-domains = <&rpmhpd SM8250_CX>; 1033 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1034 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1035 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1036 interconnect-names = "qup-core", 1037 "qup-config", 1038 "qup-memory"; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 status = "disabled"; 1042 }; 1043 1044 spi14: spi@880000 { 1045 compatible = "qcom,geni-spi"; 1046 reg = <0 0x00880000 0 0x4000>; 1047 clock-names = "se"; 1048 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1049 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1050 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 1051 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 1052 dma-names = "tx", "rx"; 1053 power-domains = <&rpmhpd RPMHPD_CX>; 1054 operating-points-v2 = <&qup_opp_table>; 1055 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1056 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1057 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1058 interconnect-names = "qup-core", 1059 "qup-config", 1060 "qup-memory"; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 status = "disabled"; 1064 }; 1065 1066 i2c15: i2c@884000 { 1067 compatible = "qcom,geni-i2c"; 1068 reg = <0 0x00884000 0 0x4000>; 1069 clock-names = "se"; 1070 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1071 pinctrl-names = "default"; 1072 pinctrl-0 = <&qup_i2c15_default>; 1073 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1074 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 1075 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 1076 dma-names = "tx", "rx"; 1077 power-domains = <&rpmhpd SM8250_CX>; 1078 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1079 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1080 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1081 interconnect-names = "qup-core", 1082 "qup-config", 1083 "qup-memory"; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 status = "disabled"; 1087 }; 1088 1089 spi15: spi@884000 { 1090 compatible = "qcom,geni-spi"; 1091 reg = <0 0x00884000 0 0x4000>; 1092 clock-names = "se"; 1093 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1094 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1095 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 1096 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 1097 dma-names = "tx", "rx"; 1098 power-domains = <&rpmhpd RPMHPD_CX>; 1099 operating-points-v2 = <&qup_opp_table>; 1100 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1101 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1102 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1103 interconnect-names = "qup-core", 1104 "qup-config", 1105 "qup-memory"; 1106 #address-cells = <1>; 1107 #size-cells = <0>; 1108 status = "disabled"; 1109 }; 1110 1111 i2c16: i2c@888000 { 1112 compatible = "qcom,geni-i2c"; 1113 reg = <0 0x00888000 0 0x4000>; 1114 clock-names = "se"; 1115 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1116 pinctrl-names = "default"; 1117 pinctrl-0 = <&qup_i2c16_default>; 1118 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1119 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 1120 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 1121 dma-names = "tx", "rx"; 1122 power-domains = <&rpmhpd SM8250_CX>; 1123 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1124 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1125 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1126 interconnect-names = "qup-core", 1127 "qup-config", 1128 "qup-memory"; 1129 #address-cells = <1>; 1130 #size-cells = <0>; 1131 status = "disabled"; 1132 }; 1133 1134 spi16: spi@888000 { 1135 compatible = "qcom,geni-spi"; 1136 reg = <0 0x00888000 0 0x4000>; 1137 clock-names = "se"; 1138 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1139 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1140 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 1141 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 1142 dma-names = "tx", "rx"; 1143 power-domains = <&rpmhpd RPMHPD_CX>; 1144 operating-points-v2 = <&qup_opp_table>; 1145 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1146 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1147 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1148 interconnect-names = "qup-core", 1149 "qup-config", 1150 "qup-memory"; 1151 #address-cells = <1>; 1152 #size-cells = <0>; 1153 status = "disabled"; 1154 }; 1155 1156 i2c17: i2c@88c000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x0088c000 0 0x4000>; 1159 clock-names = "se"; 1160 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1161 pinctrl-names = "default"; 1162 pinctrl-0 = <&qup_i2c17_default>; 1163 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1164 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 1165 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 1166 dma-names = "tx", "rx"; 1167 power-domains = <&rpmhpd SM8250_CX>; 1168 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1169 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1170 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1171 interconnect-names = "qup-core", 1172 "qup-config", 1173 "qup-memory"; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 status = "disabled"; 1177 }; 1178 1179 spi17: spi@88c000 { 1180 compatible = "qcom,geni-spi"; 1181 reg = <0 0x0088c000 0 0x4000>; 1182 clock-names = "se"; 1183 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1184 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1185 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 1186 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 1187 dma-names = "tx", "rx"; 1188 power-domains = <&rpmhpd RPMHPD_CX>; 1189 operating-points-v2 = <&qup_opp_table>; 1190 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1191 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1192 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1193 interconnect-names = "qup-core", 1194 "qup-config", 1195 "qup-memory"; 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 status = "disabled"; 1199 }; 1200 1201 uart17: serial@88c000 { 1202 compatible = "qcom,geni-uart"; 1203 reg = <0 0x0088c000 0 0x4000>; 1204 clock-names = "se"; 1205 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&qup_uart17_default>; 1208 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1209 power-domains = <&rpmhpd RPMHPD_CX>; 1210 operating-points-v2 = <&qup_opp_table>; 1211 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1212 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1213 interconnect-names = "qup-core", 1214 "qup-config"; 1215 status = "disabled"; 1216 }; 1217 1218 i2c18: i2c@890000 { 1219 compatible = "qcom,geni-i2c"; 1220 reg = <0 0x00890000 0 0x4000>; 1221 clock-names = "se"; 1222 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1223 pinctrl-names = "default"; 1224 pinctrl-0 = <&qup_i2c18_default>; 1225 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1226 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 1227 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 1228 dma-names = "tx", "rx"; 1229 power-domains = <&rpmhpd SM8250_CX>; 1230 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1231 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1232 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1233 interconnect-names = "qup-core", 1234 "qup-config", 1235 "qup-memory"; 1236 #address-cells = <1>; 1237 #size-cells = <0>; 1238 status = "disabled"; 1239 }; 1240 1241 spi18: spi@890000 { 1242 compatible = "qcom,geni-spi"; 1243 reg = <0 0x00890000 0 0x4000>; 1244 clock-names = "se"; 1245 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1246 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1247 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1248 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1249 dma-names = "tx", "rx"; 1250 power-domains = <&rpmhpd RPMHPD_CX>; 1251 operating-points-v2 = <&qup_opp_table>; 1252 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1253 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1254 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1255 interconnect-names = "qup-core", 1256 "qup-config", 1257 "qup-memory"; 1258 #address-cells = <1>; 1259 #size-cells = <0>; 1260 status = "disabled"; 1261 }; 1262 1263 uart18: serial@890000 { 1264 compatible = "qcom,geni-uart"; 1265 reg = <0 0x00890000 0 0x4000>; 1266 clock-names = "se"; 1267 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1268 pinctrl-names = "default"; 1269 pinctrl-0 = <&qup_uart18_default>; 1270 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1271 power-domains = <&rpmhpd RPMHPD_CX>; 1272 operating-points-v2 = <&qup_opp_table>; 1273 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1274 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>; 1275 interconnect-names = "qup-core", 1276 "qup-config"; 1277 status = "disabled"; 1278 }; 1279 1280 i2c19: i2c@894000 { 1281 compatible = "qcom,geni-i2c"; 1282 reg = <0 0x00894000 0 0x4000>; 1283 clock-names = "se"; 1284 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1285 pinctrl-names = "default"; 1286 pinctrl-0 = <&qup_i2c19_default>; 1287 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1288 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1289 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1290 dma-names = "tx", "rx"; 1291 power-domains = <&rpmhpd SM8250_CX>; 1292 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1293 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1294 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1295 interconnect-names = "qup-core", 1296 "qup-config", 1297 "qup-memory"; 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 status = "disabled"; 1301 }; 1302 1303 spi19: spi@894000 { 1304 compatible = "qcom,geni-spi"; 1305 reg = <0 0x00894000 0 0x4000>; 1306 clock-names = "se"; 1307 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1308 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1309 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1310 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1311 dma-names = "tx", "rx"; 1312 power-domains = <&rpmhpd RPMHPD_CX>; 1313 operating-points-v2 = <&qup_opp_table>; 1314 interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>, 1315 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>, 1316 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>; 1317 interconnect-names = "qup-core", 1318 "qup-config", 1319 "qup-memory"; 1320 #address-cells = <1>; 1321 #size-cells = <0>; 1322 status = "disabled"; 1323 }; 1324 }; 1325 1326 gpi_dma0: dma-controller@900000 { 1327 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1328 reg = <0 0x00900000 0 0x70000>; 1329 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1330 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1332 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1333 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1334 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1335 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1336 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1337 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1338 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1339 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1340 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 1341 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1342 dma-channels = <15>; 1343 dma-channel-mask = <0x7ff>; 1344 iommus = <&apps_smmu 0x5b6 0x0>; 1345 #dma-cells = <3>; 1346 status = "disabled"; 1347 }; 1348 1349 qupv3_id_0: geniqup@9c0000 { 1350 compatible = "qcom,geni-se-qup"; 1351 reg = <0x0 0x009c0000 0x0 0x6000>; 1352 clock-names = "m-ahb", "s-ahb"; 1353 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1354 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1355 #address-cells = <2>; 1356 #size-cells = <2>; 1357 iommus = <&apps_smmu 0x5a3 0x0>; 1358 ranges; 1359 status = "disabled"; 1360 1361 i2c0: i2c@980000 { 1362 compatible = "qcom,geni-i2c"; 1363 reg = <0 0x00980000 0 0x4000>; 1364 clock-names = "se"; 1365 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1366 pinctrl-names = "default"; 1367 pinctrl-0 = <&qup_i2c0_default>; 1368 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1369 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1370 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1371 dma-names = "tx", "rx"; 1372 power-domains = <&rpmhpd SM8250_CX>; 1373 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1374 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1375 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1376 interconnect-names = "qup-core", 1377 "qup-config", 1378 "qup-memory"; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 status = "disabled"; 1382 }; 1383 1384 spi0: spi@980000 { 1385 compatible = "qcom,geni-spi"; 1386 reg = <0 0x00980000 0 0x4000>; 1387 clock-names = "se"; 1388 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1389 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1390 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1391 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1392 dma-names = "tx", "rx"; 1393 power-domains = <&rpmhpd RPMHPD_CX>; 1394 operating-points-v2 = <&qup_opp_table>; 1395 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1396 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1397 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1398 interconnect-names = "qup-core", 1399 "qup-config", 1400 "qup-memory"; 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 status = "disabled"; 1404 }; 1405 1406 i2c1: i2c@984000 { 1407 compatible = "qcom,geni-i2c"; 1408 reg = <0 0x00984000 0 0x4000>; 1409 clock-names = "se"; 1410 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1411 pinctrl-names = "default"; 1412 pinctrl-0 = <&qup_i2c1_default>; 1413 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1414 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1415 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1416 dma-names = "tx", "rx"; 1417 power-domains = <&rpmhpd SM8250_CX>; 1418 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1419 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1420 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1421 interconnect-names = "qup-core", 1422 "qup-config", 1423 "qup-memory"; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 status = "disabled"; 1427 }; 1428 1429 spi1: spi@984000 { 1430 compatible = "qcom,geni-spi"; 1431 reg = <0 0x00984000 0 0x4000>; 1432 clock-names = "se"; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1434 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1435 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1436 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1437 dma-names = "tx", "rx"; 1438 power-domains = <&rpmhpd RPMHPD_CX>; 1439 operating-points-v2 = <&qup_opp_table>; 1440 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1441 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1442 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1443 interconnect-names = "qup-core", 1444 "qup-config", 1445 "qup-memory"; 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 status = "disabled"; 1449 }; 1450 1451 i2c2: i2c@988000 { 1452 compatible = "qcom,geni-i2c"; 1453 reg = <0 0x00988000 0 0x4000>; 1454 clock-names = "se"; 1455 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1456 pinctrl-names = "default"; 1457 pinctrl-0 = <&qup_i2c2_default>; 1458 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1459 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1460 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1461 dma-names = "tx", "rx"; 1462 power-domains = <&rpmhpd SM8250_CX>; 1463 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1464 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1465 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1466 interconnect-names = "qup-core", 1467 "qup-config", 1468 "qup-memory"; 1469 #address-cells = <1>; 1470 #size-cells = <0>; 1471 status = "disabled"; 1472 }; 1473 1474 spi2: spi@988000 { 1475 compatible = "qcom,geni-spi"; 1476 reg = <0 0x00988000 0 0x4000>; 1477 clock-names = "se"; 1478 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1479 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1480 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1481 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1482 dma-names = "tx", "rx"; 1483 power-domains = <&rpmhpd RPMHPD_CX>; 1484 operating-points-v2 = <&qup_opp_table>; 1485 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1486 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1487 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1488 interconnect-names = "qup-core", 1489 "qup-config", 1490 "qup-memory"; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 status = "disabled"; 1494 }; 1495 1496 uart2: serial@988000 { 1497 compatible = "qcom,geni-debug-uart"; 1498 reg = <0 0x00988000 0 0x4000>; 1499 clock-names = "se"; 1500 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_uart2_default>; 1503 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1504 power-domains = <&rpmhpd RPMHPD_CX>; 1505 operating-points-v2 = <&qup_opp_table>; 1506 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1507 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1508 interconnect-names = "qup-core", 1509 "qup-config"; 1510 status = "disabled"; 1511 }; 1512 1513 i2c3: i2c@98c000 { 1514 compatible = "qcom,geni-i2c"; 1515 reg = <0 0x0098c000 0 0x4000>; 1516 clock-names = "se"; 1517 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1518 pinctrl-names = "default"; 1519 pinctrl-0 = <&qup_i2c3_default>; 1520 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1521 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1522 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1523 dma-names = "tx", "rx"; 1524 power-domains = <&rpmhpd SM8250_CX>; 1525 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1526 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1527 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1528 interconnect-names = "qup-core", 1529 "qup-config", 1530 "qup-memory"; 1531 #address-cells = <1>; 1532 #size-cells = <0>; 1533 status = "disabled"; 1534 }; 1535 1536 spi3: spi@98c000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0 0x0098c000 0 0x4000>; 1539 clock-names = "se"; 1540 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1541 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1542 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1543 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1544 dma-names = "tx", "rx"; 1545 power-domains = <&rpmhpd RPMHPD_CX>; 1546 operating-points-v2 = <&qup_opp_table>; 1547 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1548 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1549 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1550 interconnect-names = "qup-core", 1551 "qup-config", 1552 "qup-memory"; 1553 #address-cells = <1>; 1554 #size-cells = <0>; 1555 status = "disabled"; 1556 }; 1557 1558 i2c4: i2c@990000 { 1559 compatible = "qcom,geni-i2c"; 1560 reg = <0 0x00990000 0 0x4000>; 1561 clock-names = "se"; 1562 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1563 pinctrl-names = "default"; 1564 pinctrl-0 = <&qup_i2c4_default>; 1565 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1566 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1567 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1568 dma-names = "tx", "rx"; 1569 power-domains = <&rpmhpd SM8250_CX>; 1570 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1571 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1572 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1573 interconnect-names = "qup-core", 1574 "qup-config", 1575 "qup-memory"; 1576 #address-cells = <1>; 1577 #size-cells = <0>; 1578 status = "disabled"; 1579 }; 1580 1581 spi4: spi@990000 { 1582 compatible = "qcom,geni-spi"; 1583 reg = <0 0x00990000 0 0x4000>; 1584 clock-names = "se"; 1585 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1586 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1587 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1588 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1589 dma-names = "tx", "rx"; 1590 power-domains = <&rpmhpd RPMHPD_CX>; 1591 operating-points-v2 = <&qup_opp_table>; 1592 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1593 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1594 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1595 interconnect-names = "qup-core", 1596 "qup-config", 1597 "qup-memory"; 1598 #address-cells = <1>; 1599 #size-cells = <0>; 1600 status = "disabled"; 1601 }; 1602 1603 i2c5: i2c@994000 { 1604 compatible = "qcom,geni-i2c"; 1605 reg = <0 0x00994000 0 0x4000>; 1606 clock-names = "se"; 1607 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1608 pinctrl-names = "default"; 1609 pinctrl-0 = <&qup_i2c5_default>; 1610 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1611 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1612 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1613 dma-names = "tx", "rx"; 1614 power-domains = <&rpmhpd SM8250_CX>; 1615 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1616 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1617 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1618 interconnect-names = "qup-core", 1619 "qup-config", 1620 "qup-memory"; 1621 #address-cells = <1>; 1622 #size-cells = <0>; 1623 status = "disabled"; 1624 }; 1625 1626 spi5: spi@994000 { 1627 compatible = "qcom,geni-spi"; 1628 reg = <0 0x00994000 0 0x4000>; 1629 clock-names = "se"; 1630 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1631 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1632 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1633 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1634 dma-names = "tx", "rx"; 1635 power-domains = <&rpmhpd RPMHPD_CX>; 1636 operating-points-v2 = <&qup_opp_table>; 1637 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1638 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1639 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1640 interconnect-names = "qup-core", 1641 "qup-config", 1642 "qup-memory"; 1643 #address-cells = <1>; 1644 #size-cells = <0>; 1645 status = "disabled"; 1646 }; 1647 1648 i2c6: i2c@998000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x00998000 0 0x4000>; 1651 clock-names = "se"; 1652 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1653 pinctrl-names = "default"; 1654 pinctrl-0 = <&qup_i2c6_default>; 1655 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1656 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1657 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1658 dma-names = "tx", "rx"; 1659 power-domains = <&rpmhpd SM8250_CX>; 1660 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1661 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1662 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1663 interconnect-names = "qup-core", 1664 "qup-config", 1665 "qup-memory"; 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 status = "disabled"; 1669 }; 1670 1671 spi6: spi@998000 { 1672 compatible = "qcom,geni-spi"; 1673 reg = <0 0x00998000 0 0x4000>; 1674 clock-names = "se"; 1675 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1676 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1677 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1678 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1679 dma-names = "tx", "rx"; 1680 power-domains = <&rpmhpd RPMHPD_CX>; 1681 operating-points-v2 = <&qup_opp_table>; 1682 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1683 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1684 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1685 interconnect-names = "qup-core", 1686 "qup-config", 1687 "qup-memory"; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 status = "disabled"; 1691 }; 1692 1693 uart6: serial@998000 { 1694 compatible = "qcom,geni-uart"; 1695 reg = <0 0x00998000 0 0x4000>; 1696 clock-names = "se"; 1697 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1698 pinctrl-names = "default"; 1699 pinctrl-0 = <&qup_uart6_default>; 1700 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1701 power-domains = <&rpmhpd RPMHPD_CX>; 1702 operating-points-v2 = <&qup_opp_table>; 1703 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1704 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>; 1705 interconnect-names = "qup-core", 1706 "qup-config"; 1707 status = "disabled"; 1708 }; 1709 1710 i2c7: i2c@99c000 { 1711 compatible = "qcom,geni-i2c"; 1712 reg = <0 0x0099c000 0 0x4000>; 1713 clock-names = "se"; 1714 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1715 pinctrl-names = "default"; 1716 pinctrl-0 = <&qup_i2c7_default>; 1717 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1718 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1719 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1720 dma-names = "tx", "rx"; 1721 power-domains = <&rpmhpd SM8250_CX>; 1722 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1723 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1724 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1725 interconnect-names = "qup-core", 1726 "qup-config", 1727 "qup-memory"; 1728 #address-cells = <1>; 1729 #size-cells = <0>; 1730 status = "disabled"; 1731 }; 1732 1733 spi7: spi@99c000 { 1734 compatible = "qcom,geni-spi"; 1735 reg = <0 0x0099c000 0 0x4000>; 1736 clock-names = "se"; 1737 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1738 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1739 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1740 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1741 dma-names = "tx", "rx"; 1742 power-domains = <&rpmhpd RPMHPD_CX>; 1743 operating-points-v2 = <&qup_opp_table>; 1744 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>, 1745 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>, 1746 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>; 1747 interconnect-names = "qup-core", 1748 "qup-config", 1749 "qup-memory"; 1750 #address-cells = <1>; 1751 #size-cells = <0>; 1752 status = "disabled"; 1753 }; 1754 }; 1755 1756 gpi_dma1: dma-controller@a00000 { 1757 compatible = "qcom,sm8250-gpi-dma", "qcom,sdm845-gpi-dma"; 1758 reg = <0 0x00a00000 0 0x70000>; 1759 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1760 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1761 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1762 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1763 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1765 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1766 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1767 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1768 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1769 dma-channels = <10>; 1770 dma-channel-mask = <0x3f>; 1771 iommus = <&apps_smmu 0x56 0x0>; 1772 #dma-cells = <3>; 1773 status = "disabled"; 1774 }; 1775 1776 qupv3_id_1: geniqup@ac0000 { 1777 compatible = "qcom,geni-se-qup"; 1778 reg = <0x0 0x00ac0000 0x0 0x6000>; 1779 clock-names = "m-ahb", "s-ahb"; 1780 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1781 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1782 #address-cells = <2>; 1783 #size-cells = <2>; 1784 iommus = <&apps_smmu 0x43 0x0>; 1785 ranges; 1786 status = "disabled"; 1787 1788 i2c8: i2c@a80000 { 1789 compatible = "qcom,geni-i2c"; 1790 reg = <0 0x00a80000 0 0x4000>; 1791 clock-names = "se"; 1792 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1793 pinctrl-names = "default"; 1794 pinctrl-0 = <&qup_i2c8_default>; 1795 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1796 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1797 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1798 dma-names = "tx", "rx"; 1799 power-domains = <&rpmhpd SM8250_CX>; 1800 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1801 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1802 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1803 interconnect-names = "qup-core", 1804 "qup-config", 1805 "qup-memory"; 1806 #address-cells = <1>; 1807 #size-cells = <0>; 1808 status = "disabled"; 1809 }; 1810 1811 spi8: spi@a80000 { 1812 compatible = "qcom,geni-spi"; 1813 reg = <0 0x00a80000 0 0x4000>; 1814 clock-names = "se"; 1815 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1816 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1817 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1818 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1819 dma-names = "tx", "rx"; 1820 power-domains = <&rpmhpd RPMHPD_CX>; 1821 operating-points-v2 = <&qup_opp_table>; 1822 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1823 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1824 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1825 interconnect-names = "qup-core", 1826 "qup-config", 1827 "qup-memory"; 1828 #address-cells = <1>; 1829 #size-cells = <0>; 1830 status = "disabled"; 1831 }; 1832 1833 i2c9: i2c@a84000 { 1834 compatible = "qcom,geni-i2c"; 1835 reg = <0 0x00a84000 0 0x4000>; 1836 clock-names = "se"; 1837 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1838 pinctrl-names = "default"; 1839 pinctrl-0 = <&qup_i2c9_default>; 1840 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1841 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1842 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1843 dma-names = "tx", "rx"; 1844 power-domains = <&rpmhpd SM8250_CX>; 1845 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1846 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1847 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1848 interconnect-names = "qup-core", 1849 "qup-config", 1850 "qup-memory"; 1851 #address-cells = <1>; 1852 #size-cells = <0>; 1853 status = "disabled"; 1854 }; 1855 1856 spi9: spi@a84000 { 1857 compatible = "qcom,geni-spi"; 1858 reg = <0 0x00a84000 0 0x4000>; 1859 clock-names = "se"; 1860 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1861 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1862 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1863 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1864 dma-names = "tx", "rx"; 1865 power-domains = <&rpmhpd RPMHPD_CX>; 1866 operating-points-v2 = <&qup_opp_table>; 1867 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1868 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1869 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1870 interconnect-names = "qup-core", 1871 "qup-config", 1872 "qup-memory"; 1873 #address-cells = <1>; 1874 #size-cells = <0>; 1875 status = "disabled"; 1876 }; 1877 1878 i2c10: i2c@a88000 { 1879 compatible = "qcom,geni-i2c"; 1880 reg = <0 0x00a88000 0 0x4000>; 1881 clock-names = "se"; 1882 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1883 pinctrl-names = "default"; 1884 pinctrl-0 = <&qup_i2c10_default>; 1885 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1886 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1887 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1888 dma-names = "tx", "rx"; 1889 power-domains = <&rpmhpd SM8250_CX>; 1890 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1891 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1892 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1893 interconnect-names = "qup-core", 1894 "qup-config", 1895 "qup-memory"; 1896 #address-cells = <1>; 1897 #size-cells = <0>; 1898 status = "disabled"; 1899 }; 1900 1901 spi10: spi@a88000 { 1902 compatible = "qcom,geni-spi"; 1903 reg = <0 0x00a88000 0 0x4000>; 1904 clock-names = "se"; 1905 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1906 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1907 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1908 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1909 dma-names = "tx", "rx"; 1910 power-domains = <&rpmhpd RPMHPD_CX>; 1911 operating-points-v2 = <&qup_opp_table>; 1912 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1913 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1914 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1915 interconnect-names = "qup-core", 1916 "qup-config", 1917 "qup-memory"; 1918 #address-cells = <1>; 1919 #size-cells = <0>; 1920 status = "disabled"; 1921 }; 1922 1923 i2c11: i2c@a8c000 { 1924 compatible = "qcom,geni-i2c"; 1925 reg = <0 0x00a8c000 0 0x4000>; 1926 clock-names = "se"; 1927 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1928 pinctrl-names = "default"; 1929 pinctrl-0 = <&qup_i2c11_default>; 1930 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1931 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1932 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1933 dma-names = "tx", "rx"; 1934 power-domains = <&rpmhpd SM8250_CX>; 1935 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1936 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1937 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1938 interconnect-names = "qup-core", 1939 "qup-config", 1940 "qup-memory"; 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 status = "disabled"; 1944 }; 1945 1946 spi11: spi@a8c000 { 1947 compatible = "qcom,geni-spi"; 1948 reg = <0 0x00a8c000 0 0x4000>; 1949 clock-names = "se"; 1950 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1951 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1952 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1953 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1954 dma-names = "tx", "rx"; 1955 power-domains = <&rpmhpd RPMHPD_CX>; 1956 operating-points-v2 = <&qup_opp_table>; 1957 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1958 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1959 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1960 interconnect-names = "qup-core", 1961 "qup-config", 1962 "qup-memory"; 1963 #address-cells = <1>; 1964 #size-cells = <0>; 1965 status = "disabled"; 1966 }; 1967 1968 i2c12: i2c@a90000 { 1969 compatible = "qcom,geni-i2c"; 1970 reg = <0 0x00a90000 0 0x4000>; 1971 clock-names = "se"; 1972 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1973 pinctrl-names = "default"; 1974 pinctrl-0 = <&qup_i2c12_default>; 1975 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1976 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1977 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1978 dma-names = "tx", "rx"; 1979 power-domains = <&rpmhpd SM8250_CX>; 1980 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 1981 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 1982 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 1983 interconnect-names = "qup-core", 1984 "qup-config", 1985 "qup-memory"; 1986 #address-cells = <1>; 1987 #size-cells = <0>; 1988 status = "disabled"; 1989 }; 1990 1991 spi12: spi@a90000 { 1992 compatible = "qcom,geni-spi"; 1993 reg = <0 0x00a90000 0 0x4000>; 1994 clock-names = "se"; 1995 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1996 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1997 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1998 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1999 dma-names = "tx", "rx"; 2000 power-domains = <&rpmhpd RPMHPD_CX>; 2001 operating-points-v2 = <&qup_opp_table>; 2002 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2003 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2004 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2005 interconnect-names = "qup-core", 2006 "qup-config", 2007 "qup-memory"; 2008 #address-cells = <1>; 2009 #size-cells = <0>; 2010 status = "disabled"; 2011 }; 2012 2013 uart12: serial@a90000 { 2014 compatible = "qcom,geni-debug-uart"; 2015 reg = <0x0 0x00a90000 0x0 0x4000>; 2016 clock-names = "se"; 2017 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 2018 pinctrl-names = "default"; 2019 pinctrl-0 = <&qup_uart12_default>; 2020 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 2021 power-domains = <&rpmhpd RPMHPD_CX>; 2022 operating-points-v2 = <&qup_opp_table>; 2023 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2024 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>; 2025 interconnect-names = "qup-core", 2026 "qup-config"; 2027 status = "disabled"; 2028 }; 2029 2030 i2c13: i2c@a94000 { 2031 compatible = "qcom,geni-i2c"; 2032 reg = <0 0x00a94000 0 0x4000>; 2033 clock-names = "se"; 2034 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2035 pinctrl-names = "default"; 2036 pinctrl-0 = <&qup_i2c13_default>; 2037 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2038 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 2039 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 2040 dma-names = "tx", "rx"; 2041 power-domains = <&rpmhpd SM8250_CX>; 2042 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2043 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2044 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2045 interconnect-names = "qup-core", 2046 "qup-config", 2047 "qup-memory"; 2048 #address-cells = <1>; 2049 #size-cells = <0>; 2050 status = "disabled"; 2051 }; 2052 2053 spi13: spi@a94000 { 2054 compatible = "qcom,geni-spi"; 2055 reg = <0 0x00a94000 0 0x4000>; 2056 clock-names = "se"; 2057 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 2058 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 2059 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 2060 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 2061 dma-names = "tx", "rx"; 2062 power-domains = <&rpmhpd RPMHPD_CX>; 2063 operating-points-v2 = <&qup_opp_table>; 2064 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>, 2065 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>, 2066 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>; 2067 interconnect-names = "qup-core", 2068 "qup-config", 2069 "qup-memory"; 2070 #address-cells = <1>; 2071 #size-cells = <0>; 2072 status = "disabled"; 2073 }; 2074 }; 2075 2076 config_noc: interconnect@1500000 { 2077 compatible = "qcom,sm8250-config-noc"; 2078 reg = <0 0x01500000 0 0xa580>; 2079 #interconnect-cells = <2>; 2080 qcom,bcm-voters = <&apps_bcm_voter>; 2081 }; 2082 2083 system_noc: interconnect@1620000 { 2084 compatible = "qcom,sm8250-system-noc"; 2085 reg = <0 0x01620000 0 0x1c200>; 2086 #interconnect-cells = <2>; 2087 qcom,bcm-voters = <&apps_bcm_voter>; 2088 }; 2089 2090 mc_virt: interconnect@163d000 { 2091 compatible = "qcom,sm8250-mc-virt"; 2092 reg = <0 0x0163d000 0 0x1000>; 2093 #interconnect-cells = <2>; 2094 qcom,bcm-voters = <&apps_bcm_voter>; 2095 }; 2096 2097 aggre1_noc: interconnect@16e0000 { 2098 compatible = "qcom,sm8250-aggre1-noc"; 2099 reg = <0 0x016e0000 0 0x1f180>; 2100 #interconnect-cells = <2>; 2101 qcom,bcm-voters = <&apps_bcm_voter>; 2102 }; 2103 2104 aggre2_noc: interconnect@1700000 { 2105 compatible = "qcom,sm8250-aggre2-noc"; 2106 reg = <0 0x01700000 0 0x33000>; 2107 #interconnect-cells = <2>; 2108 qcom,bcm-voters = <&apps_bcm_voter>; 2109 }; 2110 2111 compute_noc: interconnect@1733000 { 2112 compatible = "qcom,sm8250-compute-noc"; 2113 reg = <0 0x01733000 0 0xa180>; 2114 #interconnect-cells = <2>; 2115 qcom,bcm-voters = <&apps_bcm_voter>; 2116 }; 2117 2118 mmss_noc: interconnect@1740000 { 2119 compatible = "qcom,sm8250-mmss-noc"; 2120 reg = <0 0x01740000 0 0x1f080>; 2121 #interconnect-cells = <2>; 2122 qcom,bcm-voters = <&apps_bcm_voter>; 2123 }; 2124 2125 pcie0: pcie@1c00000 { 2126 compatible = "qcom,pcie-sm8250"; 2127 reg = <0 0x01c00000 0 0x3000>, 2128 <0 0x60000000 0 0xf1d>, 2129 <0 0x60000f20 0 0xa8>, 2130 <0 0x60001000 0 0x1000>, 2131 <0 0x60100000 0 0x100000>, 2132 <0 0x01c03000 0 0x1000>; 2133 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2134 device_type = "pci"; 2135 linux,pci-domain = <0>; 2136 bus-range = <0x00 0xff>; 2137 num-lanes = <1>; 2138 2139 #address-cells = <3>; 2140 #size-cells = <2>; 2141 2142 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2143 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2144 2145 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2153 interrupt-names = "msi0", 2154 "msi1", 2155 "msi2", 2156 "msi3", 2157 "msi4", 2158 "msi5", 2159 "msi6", 2160 "msi7"; 2161 #interrupt-cells = <1>; 2162 interrupt-map-mask = <0 0 0 0x7>; 2163 interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2164 <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2165 <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2166 <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2167 2168 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2169 <&gcc GCC_PCIE_0_AUX_CLK>, 2170 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2171 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2172 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2173 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2174 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2175 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2176 clock-names = "pipe", 2177 "aux", 2178 "cfg", 2179 "bus_master", 2180 "bus_slave", 2181 "slave_q2a", 2182 "tbu", 2183 "ddrss_sf_tbu"; 2184 2185 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2186 <0x100 &apps_smmu 0x1c01 0x1>; 2187 2188 resets = <&gcc GCC_PCIE_0_BCR>; 2189 reset-names = "pci"; 2190 2191 power-domains = <&gcc PCIE_0_GDSC>; 2192 2193 phys = <&pcie0_phy>; 2194 phy-names = "pciephy"; 2195 2196 perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>; 2197 wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>; 2198 2199 pinctrl-names = "default"; 2200 pinctrl-0 = <&pcie0_default_state>; 2201 dma-coherent; 2202 2203 status = "disabled"; 2204 2205 pcieport0: pcie@0 { 2206 device_type = "pci"; 2207 reg = <0x0 0x0 0x0 0x0 0x0>; 2208 bus-range = <0x01 0xff>; 2209 2210 #address-cells = <3>; 2211 #size-cells = <2>; 2212 ranges; 2213 }; 2214 }; 2215 2216 pcie0_phy: phy@1c06000 { 2217 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2218 reg = <0 0x01c06000 0 0x1000>; 2219 2220 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2221 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2222 <&gcc GCC_PCIE_WIFI_CLKREF_EN>, 2223 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 2224 <&gcc GCC_PCIE_0_PIPE_CLK>; 2225 clock-names = "aux", 2226 "cfg_ahb", 2227 "ref", 2228 "refgen", 2229 "pipe"; 2230 2231 clock-output-names = "pcie_0_pipe_clk"; 2232 #clock-cells = <0>; 2233 2234 #phy-cells = <0>; 2235 2236 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2237 reset-names = "phy"; 2238 2239 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 2240 assigned-clock-rates = <100000000>; 2241 2242 status = "disabled"; 2243 }; 2244 2245 pcie1: pcie@1c08000 { 2246 compatible = "qcom,pcie-sm8250"; 2247 reg = <0 0x01c08000 0 0x3000>, 2248 <0 0x40000000 0 0xf1d>, 2249 <0 0x40000f20 0 0xa8>, 2250 <0 0x40001000 0 0x1000>, 2251 <0 0x40100000 0 0x100000>, 2252 <0 0x01c0b000 0 0x1000>; 2253 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2254 device_type = "pci"; 2255 linux,pci-domain = <1>; 2256 bus-range = <0x00 0xff>; 2257 num-lanes = <2>; 2258 2259 #address-cells = <3>; 2260 #size-cells = <2>; 2261 2262 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2263 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2264 2265 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2266 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; 2273 interrupt-names = "msi0", 2274 "msi1", 2275 "msi2", 2276 "msi3", 2277 "msi4", 2278 "msi5", 2279 "msi6", 2280 "msi7"; 2281 #interrupt-cells = <1>; 2282 interrupt-map-mask = <0 0 0 0x7>; 2283 interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2284 <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2285 <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2286 <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2287 2288 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2289 <&gcc GCC_PCIE_1_AUX_CLK>, 2290 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2291 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2292 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2293 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2294 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2295 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2296 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2297 clock-names = "pipe", 2298 "aux", 2299 "cfg", 2300 "bus_master", 2301 "bus_slave", 2302 "slave_q2a", 2303 "ref", 2304 "tbu", 2305 "ddrss_sf_tbu"; 2306 2307 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2308 assigned-clock-rates = <19200000>; 2309 2310 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2311 <0x100 &apps_smmu 0x1c81 0x1>; 2312 2313 resets = <&gcc GCC_PCIE_1_BCR>; 2314 reset-names = "pci"; 2315 2316 power-domains = <&gcc PCIE_1_GDSC>; 2317 2318 phys = <&pcie1_phy>; 2319 phy-names = "pciephy"; 2320 2321 perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>; 2322 wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>; 2323 2324 pinctrl-names = "default"; 2325 pinctrl-0 = <&pcie1_default_state>; 2326 dma-coherent; 2327 2328 status = "disabled"; 2329 2330 pcie@0 { 2331 device_type = "pci"; 2332 reg = <0x0 0x0 0x0 0x0 0x0>; 2333 bus-range = <0x01 0xff>; 2334 2335 #address-cells = <3>; 2336 #size-cells = <2>; 2337 ranges; 2338 }; 2339 }; 2340 2341 pcie1_phy: phy@1c0e000 { 2342 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2343 reg = <0 0x01c0e000 0 0x1000>; 2344 2345 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2346 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2347 <&gcc GCC_PCIE_WIGIG_CLKREF_EN>, 2348 <&gcc GCC_PCIE1_PHY_REFGEN_CLK>, 2349 <&gcc GCC_PCIE_1_PIPE_CLK>; 2350 clock-names = "aux", 2351 "cfg_ahb", 2352 "ref", 2353 "refgen", 2354 "pipe"; 2355 2356 clock-output-names = "pcie_1_pipe_clk"; 2357 #clock-cells = <0>; 2358 2359 #phy-cells = <0>; 2360 2361 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2362 reset-names = "phy"; 2363 2364 assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>; 2365 assigned-clock-rates = <100000000>; 2366 2367 status = "disabled"; 2368 }; 2369 2370 pcie2: pcie@1c10000 { 2371 compatible = "qcom,pcie-sm8250"; 2372 reg = <0 0x01c10000 0 0x3000>, 2373 <0 0x64000000 0 0xf1d>, 2374 <0 0x64000f20 0 0xa8>, 2375 <0 0x64001000 0 0x1000>, 2376 <0 0x64100000 0 0x100000>, 2377 <0 0x01c13000 0 0x1000>; 2378 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2379 device_type = "pci"; 2380 linux,pci-domain = <2>; 2381 bus-range = <0x00 0xff>; 2382 num-lanes = <2>; 2383 2384 #address-cells = <3>; 2385 #size-cells = <2>; 2386 2387 ranges = <0x01000000 0x0 0x00000000 0x0 0x64200000 0x0 0x100000>, 2388 <0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>; 2389 2390 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 2391 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2394 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 2395 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 2396 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 2397 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 2398 interrupt-names = "msi0", 2399 "msi1", 2400 "msi2", 2401 "msi3", 2402 "msi4", 2403 "msi5", 2404 "msi6", 2405 "msi7"; 2406 #interrupt-cells = <1>; 2407 interrupt-map-mask = <0 0 0 0x7>; 2408 interrupt-map = <0 0 0 1 &intc 0 290 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 2409 <0 0 0 2 &intc 0 415 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 2410 <0 0 0 3 &intc 0 416 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 2411 <0 0 0 4 &intc 0 417 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 2412 2413 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, 2414 <&gcc GCC_PCIE_2_AUX_CLK>, 2415 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2416 <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, 2417 <&gcc GCC_PCIE_2_SLV_AXI_CLK>, 2418 <&gcc GCC_PCIE_2_SLV_Q2A_AXI_CLK>, 2419 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2420 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2421 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>; 2422 clock-names = "pipe", 2423 "aux", 2424 "cfg", 2425 "bus_master", 2426 "bus_slave", 2427 "slave_q2a", 2428 "ref", 2429 "tbu", 2430 "ddrss_sf_tbu"; 2431 2432 assigned-clocks = <&gcc GCC_PCIE_2_AUX_CLK>; 2433 assigned-clock-rates = <19200000>; 2434 2435 iommu-map = <0x0 &apps_smmu 0x1d00 0x1>, 2436 <0x100 &apps_smmu 0x1d01 0x1>; 2437 2438 resets = <&gcc GCC_PCIE_2_BCR>; 2439 reset-names = "pci"; 2440 2441 power-domains = <&gcc PCIE_2_GDSC>; 2442 2443 phys = <&pcie2_phy>; 2444 phy-names = "pciephy"; 2445 2446 perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; 2447 wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>; 2448 2449 pinctrl-names = "default"; 2450 pinctrl-0 = <&pcie2_default_state>; 2451 dma-coherent; 2452 2453 status = "disabled"; 2454 2455 pcie@0 { 2456 device_type = "pci"; 2457 reg = <0x0 0x0 0x0 0x0 0x0>; 2458 bus-range = <0x01 0xff>; 2459 2460 #address-cells = <3>; 2461 #size-cells = <2>; 2462 ranges; 2463 }; 2464 }; 2465 2466 pcie2_phy: phy@1c16000 { 2467 compatible = "qcom,sm8250-qmp-modem-pcie-phy"; 2468 reg = <0 0x01c16000 0 0x1000>; 2469 2470 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 2471 <&gcc GCC_PCIE_2_CFG_AHB_CLK>, 2472 <&gcc GCC_PCIE_MDM_CLKREF_EN>, 2473 <&gcc GCC_PCIE2_PHY_REFGEN_CLK>, 2474 <&gcc GCC_PCIE_2_PIPE_CLK>; 2475 clock-names = "aux", 2476 "cfg_ahb", 2477 "ref", 2478 "refgen", 2479 "pipe"; 2480 2481 clock-output-names = "pcie_2_pipe_clk"; 2482 #clock-cells = <0>; 2483 2484 #phy-cells = <0>; 2485 2486 resets = <&gcc GCC_PCIE_2_PHY_BCR>; 2487 reset-names = "phy"; 2488 2489 assigned-clocks = <&gcc GCC_PCIE2_PHY_REFGEN_CLK>; 2490 assigned-clock-rates = <100000000>; 2491 2492 status = "disabled"; 2493 }; 2494 2495 ufs_mem_hc: ufshc@1d84000 { 2496 compatible = "qcom,sm8250-ufshc", "qcom,ufshc", 2497 "jedec,ufs-2.0"; 2498 reg = <0 0x01d84000 0 0x3000>; 2499 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2500 phys = <&ufs_mem_phy>; 2501 phy-names = "ufsphy"; 2502 lanes-per-direction = <2>; 2503 #reset-cells = <1>; 2504 resets = <&gcc GCC_UFS_PHY_BCR>; 2505 reset-names = "rst"; 2506 2507 power-domains = <&gcc UFS_PHY_GDSC>; 2508 2509 iommus = <&apps_smmu 0x0e0 0>, <&apps_smmu 0x4e0 0>; 2510 2511 clock-names = 2512 "core_clk", 2513 "bus_aggr_clk", 2514 "iface_clk", 2515 "core_clk_unipro", 2516 "ref_clk", 2517 "tx_lane0_sync_clk", 2518 "rx_lane0_sync_clk", 2519 "rx_lane1_sync_clk"; 2520 clocks = 2521 <&gcc GCC_UFS_PHY_AXI_CLK>, 2522 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2523 <&gcc GCC_UFS_PHY_AHB_CLK>, 2524 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2525 <&rpmhcc RPMH_CXO_CLK>, 2526 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2527 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2528 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2529 2530 operating-points-v2 = <&ufs_opp_table>; 2531 2532 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI_CH0 0>, 2533 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_UFS_MEM_CFG 0>; 2534 interconnect-names = "ufs-ddr", "cpu-ufs"; 2535 2536 status = "disabled"; 2537 2538 ufs_opp_table: opp-table { 2539 compatible = "operating-points-v2"; 2540 2541 opp-37500000 { 2542 opp-hz = /bits/ 64 <37500000>, 2543 /bits/ 64 <0>, 2544 /bits/ 64 <0>, 2545 /bits/ 64 <37500000>, 2546 /bits/ 64 <0>, 2547 /bits/ 64 <0>, 2548 /bits/ 64 <0>, 2549 /bits/ 64 <0>; 2550 required-opps = <&rpmhpd_opp_low_svs>; 2551 }; 2552 2553 opp-300000000 { 2554 opp-hz = /bits/ 64 <300000000>, 2555 /bits/ 64 <0>, 2556 /bits/ 64 <0>, 2557 /bits/ 64 <300000000>, 2558 /bits/ 64 <0>, 2559 /bits/ 64 <0>, 2560 /bits/ 64 <0>, 2561 /bits/ 64 <0>; 2562 required-opps = <&rpmhpd_opp_nom>; 2563 }; 2564 }; 2565 }; 2566 2567 ufs_mem_phy: phy@1d87000 { 2568 compatible = "qcom,sm8250-qmp-ufs-phy"; 2569 reg = <0 0x01d87000 0 0x1000>; 2570 2571 clocks = <&rpmhcc RPMH_CXO_CLK>, 2572 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2573 <&gcc GCC_UFS_1X_CLKREF_EN>; 2574 clock-names = "ref", 2575 "ref_aux", 2576 "qref"; 2577 2578 resets = <&ufs_mem_hc 0>; 2579 reset-names = "ufsphy"; 2580 2581 power-domains = <&gcc UFS_PHY_GDSC>; 2582 2583 #phy-cells = <0>; 2584 2585 status = "disabled"; 2586 }; 2587 2588 cryptobam: dma-controller@1dc4000 { 2589 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2590 reg = <0 0x01dc4000 0 0x24000>; 2591 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2592 #dma-cells = <1>; 2593 qcom,ee = <0>; 2594 qcom,controlled-remotely; 2595 num-channels = <8>; 2596 qcom,num-ees = <2>; 2597 iommus = <&apps_smmu 0x592 0x0000>, 2598 <&apps_smmu 0x598 0x0000>, 2599 <&apps_smmu 0x599 0x0000>, 2600 <&apps_smmu 0x59f 0x0000>, 2601 <&apps_smmu 0x586 0x0011>, 2602 <&apps_smmu 0x596 0x0011>; 2603 }; 2604 2605 crypto: crypto@1dfa000 { 2606 compatible = "qcom,sm8250-qce", "qcom,sm8150-qce", "qcom,qce"; 2607 reg = <0 0x01dfa000 0 0x6000>; 2608 dmas = <&cryptobam 4>, <&cryptobam 5>; 2609 dma-names = "rx", "tx"; 2610 iommus = <&apps_smmu 0x592 0x0000>, 2611 <&apps_smmu 0x598 0x0000>, 2612 <&apps_smmu 0x599 0x0000>, 2613 <&apps_smmu 0x59f 0x0000>, 2614 <&apps_smmu 0x586 0x0011>, 2615 <&apps_smmu 0x596 0x0011>; 2616 interconnects = <&aggre2_noc MASTER_CRYPTO_CORE_0 0 &mc_virt SLAVE_EBI_CH0 0>; 2617 interconnect-names = "memory"; 2618 }; 2619 2620 tcsr_mutex: hwlock@1f40000 { 2621 compatible = "qcom,tcsr-mutex"; 2622 reg = <0x0 0x01f40000 0x0 0x40000>; 2623 #hwlock-cells = <1>; 2624 }; 2625 2626 tcsr: syscon@1fc0000 { 2627 compatible = "qcom,sm8250-tcsr", "syscon"; 2628 reg = <0x0 0x1fc0000 0x0 0x30000>; 2629 }; 2630 2631 wsamacro: codec@3240000 { 2632 compatible = "qcom,sm8250-lpass-wsa-macro"; 2633 reg = <0 0x03240000 0 0x1000>; 2634 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2635 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2636 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2637 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2638 <&vamacro>; 2639 2640 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2641 2642 #clock-cells = <0>; 2643 clock-output-names = "mclk"; 2644 #sound-dai-cells = <1>; 2645 2646 pinctrl-names = "default"; 2647 pinctrl-0 = <&wsa_swr_active>; 2648 2649 status = "disabled"; 2650 }; 2651 2652 swr0: soundwire@3250000 { 2653 reg = <0 0x03250000 0 0x2000>; 2654 compatible = "qcom,soundwire-v1.5.1"; 2655 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 2656 clocks = <&wsamacro>; 2657 clock-names = "iface"; 2658 2659 qcom,din-ports = <2>; 2660 qcom,dout-ports = <6>; 2661 2662 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2663 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2664 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2665 qcom,ports-block-pack-mode = /bits/ 8 <0x0 0x0 0x1 0x0 0x0 0x1 0x0 0x0>; 2666 2667 #sound-dai-cells = <1>; 2668 #address-cells = <2>; 2669 #size-cells = <0>; 2670 2671 status = "disabled"; 2672 }; 2673 2674 vamacro: codec@3370000 { 2675 compatible = "qcom,sm8250-lpass-va-macro"; 2676 reg = <0 0x03370000 0 0x1000>; 2677 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2678 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2679 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2680 2681 clock-names = "mclk", "macro", "dcodec"; 2682 2683 #clock-cells = <0>; 2684 clock-output-names = "fsgen"; 2685 #sound-dai-cells = <1>; 2686 }; 2687 2688 rxmacro: rxmacro@3200000 { 2689 pinctrl-names = "default"; 2690 pinctrl-0 = <&rx_swr_active>; 2691 compatible = "qcom,sm8250-lpass-rx-macro"; 2692 reg = <0 0x03200000 0 0x1000>; 2693 status = "disabled"; 2694 2695 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2696 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2697 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2698 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2699 <&vamacro>; 2700 2701 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2702 2703 #clock-cells = <0>; 2704 clock-output-names = "mclk"; 2705 #sound-dai-cells = <1>; 2706 }; 2707 2708 swr1: soundwire@3210000 { 2709 reg = <0 0x03210000 0 0x2000>; 2710 compatible = "qcom,soundwire-v1.5.1"; 2711 status = "disabled"; 2712 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2713 clocks = <&rxmacro>; 2714 clock-names = "iface"; 2715 label = "RX"; 2716 qcom,din-ports = <0>; 2717 qcom,dout-ports = <5>; 2718 2719 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2720 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>; 2721 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2722 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2723 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2724 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2725 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2726 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2727 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2728 2729 #sound-dai-cells = <1>; 2730 #address-cells = <2>; 2731 #size-cells = <0>; 2732 }; 2733 2734 txmacro: txmacro@3220000 { 2735 pinctrl-names = "default"; 2736 pinctrl-0 = <&tx_swr_active>; 2737 compatible = "qcom,sm8250-lpass-tx-macro"; 2738 reg = <0 0x03220000 0 0x1000>; 2739 status = "disabled"; 2740 2741 clocks = <&q6afecc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2742 <&q6afecc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2743 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2744 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2745 <&vamacro>; 2746 2747 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2748 2749 #clock-cells = <0>; 2750 clock-output-names = "mclk"; 2751 #sound-dai-cells = <1>; 2752 }; 2753 2754 /* tx macro */ 2755 swr2: soundwire@3230000 { 2756 reg = <0 0x03230000 0 0x2000>; 2757 compatible = "qcom,soundwire-v1.5.1"; 2758 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 2759 interrupt-names = "core"; 2760 status = "disabled"; 2761 2762 clocks = <&txmacro>; 2763 clock-names = "iface"; 2764 label = "TX"; 2765 2766 qcom,din-ports = <5>; 2767 qcom,dout-ports = <0>; 2768 qcom,ports-sinterval-low = /bits/ 8 <0xff 0x01 0x01 0x03 0x03>; 2769 qcom,ports-offset1 = /bits/ 8 <0xff 0x01 0x00 0x02 0x00>; 2770 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x00 0x00 0x00>; 2771 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2772 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2773 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2774 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2775 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2776 qcom,ports-lane-control = /bits/ 8 <0xff 0x00 0x01 0x00 0x01>; 2777 #sound-dai-cells = <1>; 2778 #address-cells = <2>; 2779 #size-cells = <0>; 2780 }; 2781 2782 lpass_tlmm: pinctrl@33c0000 { 2783 compatible = "qcom,sm8250-lpass-lpi-pinctrl"; 2784 reg = <0 0x033c0000 0x0 0x20000>, 2785 <0 0x03550000 0x0 0x10000>; 2786 gpio-controller; 2787 #gpio-cells = <2>; 2788 gpio-ranges = <&lpass_tlmm 0 0 14>; 2789 2790 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2791 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2792 clock-names = "core", "audio"; 2793 2794 wsa_swr_active: wsa-swr-active-state { 2795 clk-pins { 2796 pins = "gpio10"; 2797 function = "wsa_swr_clk"; 2798 drive-strength = <2>; 2799 slew-rate = <1>; 2800 bias-disable; 2801 }; 2802 2803 data-pins { 2804 pins = "gpio11"; 2805 function = "wsa_swr_data"; 2806 drive-strength = <2>; 2807 slew-rate = <1>; 2808 bias-bus-hold; 2809 }; 2810 }; 2811 2812 wsa_swr_sleep: wsa-swr-sleep-state { 2813 clk-pins { 2814 pins = "gpio10"; 2815 function = "wsa_swr_clk"; 2816 drive-strength = <2>; 2817 bias-pull-down; 2818 }; 2819 2820 data-pins { 2821 pins = "gpio11"; 2822 function = "wsa_swr_data"; 2823 drive-strength = <2>; 2824 bias-pull-down; 2825 }; 2826 }; 2827 2828 dmic01_active: dmic01-active-state { 2829 clk-pins { 2830 pins = "gpio6"; 2831 function = "dmic1_clk"; 2832 drive-strength = <8>; 2833 output-high; 2834 }; 2835 data-pins { 2836 pins = "gpio7"; 2837 function = "dmic1_data"; 2838 drive-strength = <8>; 2839 }; 2840 }; 2841 2842 dmic01_sleep: dmic01-sleep-state { 2843 clk-pins { 2844 pins = "gpio6"; 2845 function = "dmic1_clk"; 2846 drive-strength = <2>; 2847 bias-disable; 2848 output-low; 2849 }; 2850 2851 data-pins { 2852 pins = "gpio7"; 2853 function = "dmic1_data"; 2854 drive-strength = <2>; 2855 bias-pull-down; 2856 }; 2857 }; 2858 2859 rx_swr_active: rx-swr-active-state { 2860 clk-pins { 2861 pins = "gpio3"; 2862 function = "swr_rx_clk"; 2863 drive-strength = <2>; 2864 slew-rate = <1>; 2865 bias-disable; 2866 }; 2867 2868 data-pins { 2869 pins = "gpio4", "gpio5"; 2870 function = "swr_rx_data"; 2871 drive-strength = <2>; 2872 slew-rate = <1>; 2873 bias-bus-hold; 2874 }; 2875 }; 2876 2877 tx_swr_active: tx-swr-active-state { 2878 clk-pins { 2879 pins = "gpio0"; 2880 function = "swr_tx_clk"; 2881 drive-strength = <2>; 2882 slew-rate = <1>; 2883 bias-disable; 2884 }; 2885 2886 data-pins { 2887 pins = "gpio1", "gpio2"; 2888 function = "swr_tx_data"; 2889 drive-strength = <2>; 2890 slew-rate = <1>; 2891 bias-bus-hold; 2892 }; 2893 }; 2894 2895 tx_swr_sleep: tx-swr-sleep-state { 2896 clk-pins { 2897 pins = "gpio0"; 2898 function = "swr_tx_clk"; 2899 drive-strength = <2>; 2900 bias-pull-down; 2901 }; 2902 2903 data1-pins { 2904 pins = "gpio1"; 2905 function = "swr_tx_data"; 2906 drive-strength = <2>; 2907 bias-bus-hold; 2908 }; 2909 2910 data2-pins { 2911 pins = "gpio2"; 2912 function = "swr_tx_data"; 2913 drive-strength = <2>; 2914 bias-pull-down; 2915 }; 2916 }; 2917 }; 2918 2919 gpu: gpu@3d00000 { 2920 compatible = "qcom,adreno-650.2", 2921 "qcom,adreno"; 2922 2923 reg = <0 0x03d00000 0 0x40000>; 2924 reg-names = "kgsl_3d0_reg_memory"; 2925 2926 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2927 2928 iommus = <&adreno_smmu 0 0x401>; 2929 2930 operating-points-v2 = <&gpu_opp_table>; 2931 2932 qcom,gmu = <&gmu>; 2933 2934 nvmem-cells = <&gpu_speed_bin>; 2935 nvmem-cell-names = "speed_bin"; 2936 #cooling-cells = <2>; 2937 2938 status = "disabled"; 2939 2940 zap-shader { 2941 memory-region = <&gpu_mem>; 2942 }; 2943 2944 gpu_opp_table: opp-table { 2945 compatible = "operating-points-v2"; 2946 2947 opp-670000000 { 2948 opp-hz = /bits/ 64 <670000000>; 2949 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2950 opp-supported-hw = <0xa>; 2951 }; 2952 2953 opp-587000000 { 2954 opp-hz = /bits/ 64 <587000000>; 2955 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2956 opp-supported-hw = <0xb>; 2957 }; 2958 2959 opp-525000000 { 2960 opp-hz = /bits/ 64 <525000000>; 2961 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2962 opp-supported-hw = <0xf>; 2963 }; 2964 2965 opp-490000000 { 2966 opp-hz = /bits/ 64 <490000000>; 2967 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2968 opp-supported-hw = <0xf>; 2969 }; 2970 2971 opp-441600000 { 2972 opp-hz = /bits/ 64 <441600000>; 2973 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 2974 opp-supported-hw = <0xf>; 2975 }; 2976 2977 opp-400000000 { 2978 opp-hz = /bits/ 64 <400000000>; 2979 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2980 opp-supported-hw = <0xf>; 2981 }; 2982 2983 opp-305000000 { 2984 opp-hz = /bits/ 64 <305000000>; 2985 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2986 opp-supported-hw = <0xf>; 2987 }; 2988 }; 2989 }; 2990 2991 gmu: gmu@3d6a000 { 2992 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu"; 2993 2994 reg = <0 0x03d6a000 0 0x30000>, 2995 <0 0x3de0000 0 0x10000>, 2996 <0 0xb290000 0 0x10000>, 2997 <0 0xb490000 0 0x10000>; 2998 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq"; 2999 3000 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3001 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3002 interrupt-names = "hfi", "gmu"; 3003 3004 clocks = <&gpucc GPU_CC_AHB_CLK>, 3005 <&gpucc GPU_CC_CX_GMU_CLK>, 3006 <&gpucc GPU_CC_CXO_CLK>, 3007 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3008 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 3009 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc"; 3010 3011 power-domains = <&gpucc GPU_CX_GDSC>, 3012 <&gpucc GPU_GX_GDSC>; 3013 power-domain-names = "cx", "gx"; 3014 3015 iommus = <&adreno_smmu 5 0x400>; 3016 3017 operating-points-v2 = <&gmu_opp_table>; 3018 3019 status = "disabled"; 3020 3021 gmu_opp_table: opp-table { 3022 compatible = "operating-points-v2"; 3023 3024 opp-200000000 { 3025 opp-hz = /bits/ 64 <200000000>; 3026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3027 }; 3028 }; 3029 }; 3030 3031 gpucc: clock-controller@3d90000 { 3032 compatible = "qcom,sm8250-gpucc"; 3033 reg = <0 0x03d90000 0 0x9000>; 3034 clocks = <&rpmhcc RPMH_CXO_CLK>, 3035 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3036 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3037 clock-names = "bi_tcxo", 3038 "gcc_gpu_gpll0_clk_src", 3039 "gcc_gpu_gpll0_div_clk_src"; 3040 #clock-cells = <1>; 3041 #reset-cells = <1>; 3042 #power-domain-cells = <1>; 3043 }; 3044 3045 adreno_smmu: iommu@3da0000 { 3046 compatible = "qcom,sm8250-smmu-500", "qcom,adreno-smmu", 3047 "qcom,smmu-500", "arm,mmu-500"; 3048 reg = <0 0x03da0000 0 0x10000>; 3049 #iommu-cells = <2>; 3050 #global-interrupts = <2>; 3051 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 3052 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3054 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3056 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3058 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>; 3061 clocks = <&gpucc GPU_CC_AHB_CLK>, 3062 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3063 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 3064 clock-names = "ahb", "bus", "iface"; 3065 3066 power-domains = <&gpucc GPU_CX_GDSC>; 3067 dma-coherent; 3068 }; 3069 3070 slpi: remoteproc@5c00000 { 3071 compatible = "qcom,sm8250-slpi-pas"; 3072 reg = <0 0x05c00000 0 0x4000>; 3073 3074 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>, 3075 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>, 3076 <&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>, 3077 <&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>, 3078 <&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>; 3079 interrupt-names = "wdog", "fatal", "ready", 3080 "handover", "stop-ack"; 3081 3082 clocks = <&rpmhcc RPMH_CXO_CLK>; 3083 clock-names = "xo"; 3084 3085 power-domains = <&rpmhpd RPMHPD_LCX>, 3086 <&rpmhpd RPMHPD_LMX>; 3087 power-domain-names = "lcx", "lmx"; 3088 3089 memory-region = <&slpi_mem>; 3090 3091 qcom,qmp = <&aoss_qmp>; 3092 3093 qcom,smem-states = <&smp2p_slpi_out 0>; 3094 qcom,smem-state-names = "stop"; 3095 3096 status = "disabled"; 3097 3098 glink-edge { 3099 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI 3100 IPCC_MPROC_SIGNAL_GLINK_QMP 3101 IRQ_TYPE_EDGE_RISING>; 3102 mboxes = <&ipcc IPCC_CLIENT_SLPI 3103 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3104 3105 label = "slpi"; 3106 qcom,remote-pid = <3>; 3107 3108 fastrpc { 3109 compatible = "qcom,fastrpc"; 3110 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3111 label = "sdsp"; 3112 qcom,non-secure-domain; 3113 #address-cells = <1>; 3114 #size-cells = <0>; 3115 3116 compute-cb@1 { 3117 compatible = "qcom,fastrpc-compute-cb"; 3118 reg = <1>; 3119 iommus = <&apps_smmu 0x0541 0x0>; 3120 }; 3121 3122 compute-cb@2 { 3123 compatible = "qcom,fastrpc-compute-cb"; 3124 reg = <2>; 3125 iommus = <&apps_smmu 0x0542 0x0>; 3126 }; 3127 3128 compute-cb@3 { 3129 compatible = "qcom,fastrpc-compute-cb"; 3130 reg = <3>; 3131 iommus = <&apps_smmu 0x0543 0x0>; 3132 /* note: shared-cb = <4> in downstream */ 3133 }; 3134 }; 3135 }; 3136 }; 3137 3138 stm@6002000 { 3139 compatible = "arm,coresight-stm", "arm,primecell"; 3140 reg = <0 0x06002000 0 0x1000>, <0 0x16280000 0 0x180000>; 3141 reg-names = "stm-base", "stm-stimulus-base"; 3142 3143 clocks = <&aoss_qmp>; 3144 clock-names = "apb_pclk"; 3145 3146 out-ports { 3147 port { 3148 stm_out: endpoint { 3149 remote-endpoint = <&funnel0_in7>; 3150 }; 3151 }; 3152 }; 3153 }; 3154 3155 tpda@6004000 { 3156 compatible = "qcom,coresight-tpda", "arm,primecell"; 3157 reg = <0 0x06004000 0 0x1000>; 3158 3159 clocks = <&aoss_qmp>; 3160 clock-names = "apb_pclk"; 3161 3162 out-ports { 3163 3164 port { 3165 tpda_out_funnel_qatb: endpoint { 3166 remote-endpoint = <&funnel_qatb_in_tpda>; 3167 }; 3168 }; 3169 }; 3170 3171 in-ports { 3172 #address-cells = <1>; 3173 #size-cells = <0>; 3174 3175 port@9 { 3176 reg = <9>; 3177 tpda_9_in_tpdm_mm: endpoint { 3178 remote-endpoint = <&tpdm_mm_out_tpda9>; 3179 }; 3180 }; 3181 3182 port@17 { 3183 reg = <23>; 3184 tpda_23_in_tpdm_prng: endpoint { 3185 remote-endpoint = <&tpdm_prng_out_tpda_23>; 3186 }; 3187 }; 3188 }; 3189 }; 3190 3191 funnel@6005000 { 3192 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3193 reg = <0 0x06005000 0 0x1000>; 3194 3195 clocks = <&aoss_qmp>; 3196 clock-names = "apb_pclk"; 3197 3198 out-ports { 3199 port { 3200 funnel_qatb_out_funnel_in0: endpoint { 3201 remote-endpoint = <&funnel_in0_in_funnel_qatb>; 3202 }; 3203 }; 3204 }; 3205 3206 in-ports { 3207 port { 3208 funnel_qatb_in_tpda: endpoint { 3209 remote-endpoint = <&tpda_out_funnel_qatb>; 3210 }; 3211 }; 3212 }; 3213 }; 3214 3215 funnel@6041000 { 3216 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3217 reg = <0 0x06041000 0 0x1000>; 3218 3219 clocks = <&aoss_qmp>; 3220 clock-names = "apb_pclk"; 3221 3222 out-ports { 3223 port { 3224 funnel_in0_out_funnel_merg: endpoint { 3225 remote-endpoint = <&funnel_merg_in_funnel_in0>; 3226 }; 3227 }; 3228 }; 3229 3230 in-ports { 3231 #address-cells = <1>; 3232 #size-cells = <0>; 3233 3234 port@6 { 3235 reg = <6>; 3236 funnel_in0_in_funnel_qatb: endpoint { 3237 remote-endpoint = <&funnel_qatb_out_funnel_in0>; 3238 }; 3239 }; 3240 3241 port@7 { 3242 reg = <7>; 3243 funnel0_in7: endpoint { 3244 remote-endpoint = <&stm_out>; 3245 }; 3246 }; 3247 }; 3248 }; 3249 3250 funnel@6042000 { 3251 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3252 reg = <0 0x06042000 0 0x1000>; 3253 3254 clocks = <&aoss_qmp>; 3255 clock-names = "apb_pclk"; 3256 3257 out-ports { 3258 port { 3259 funnel_in1_out_funnel_merg: endpoint { 3260 remote-endpoint = <&funnel_merg_in_funnel_in1>; 3261 }; 3262 }; 3263 }; 3264 3265 in-ports { 3266 #address-cells = <1>; 3267 #size-cells = <0>; 3268 3269 port@4 { 3270 reg = <4>; 3271 funnel_in1_in_funnel_apss_merg: endpoint { 3272 remote-endpoint = <&funnel_apss_merg_out_funnel_in1>; 3273 }; 3274 }; 3275 }; 3276 }; 3277 3278 funnel@6045000 { 3279 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3280 reg = <0 0x06045000 0 0x1000>; 3281 3282 clocks = <&aoss_qmp>; 3283 clock-names = "apb_pclk"; 3284 3285 out-ports { 3286 port { 3287 funnel_merg_out_funnel_swao: endpoint { 3288 remote-endpoint = <&funnel_swao_in_funnel_merg>; 3289 }; 3290 }; 3291 }; 3292 3293 in-ports { 3294 #address-cells = <1>; 3295 #size-cells = <0>; 3296 3297 port@0 { 3298 reg = <0>; 3299 funnel_merg_in_funnel_in0: endpoint { 3300 remote-endpoint = <&funnel_in0_out_funnel_merg>; 3301 }; 3302 }; 3303 3304 port@1 { 3305 reg = <1>; 3306 funnel_merg_in_funnel_in1: endpoint { 3307 remote-endpoint = <&funnel_in1_out_funnel_merg>; 3308 }; 3309 }; 3310 }; 3311 }; 3312 3313 replicator@6046000 { 3314 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3315 reg = <0 0x06046000 0 0x1000>; 3316 3317 clocks = <&aoss_qmp>; 3318 clock-names = "apb_pclk"; 3319 3320 out-ports { 3321 port { 3322 replicator_out: endpoint { 3323 remote-endpoint = <&etr_in>; 3324 }; 3325 }; 3326 }; 3327 3328 in-ports { 3329 port { 3330 replicator_cx_in_swao_out: endpoint { 3331 remote-endpoint = <&replicator_swao_out_cx_in>; 3332 }; 3333 }; 3334 }; 3335 }; 3336 3337 etr@6048000 { 3338 compatible = "arm,coresight-tmc", "arm,primecell"; 3339 reg = <0 0x06048000 0 0x1000>; 3340 3341 clocks = <&aoss_qmp>; 3342 clock-names = "apb_pclk"; 3343 arm,scatter-gather; 3344 3345 in-ports { 3346 port { 3347 etr_in: endpoint { 3348 remote-endpoint = <&replicator_out>; 3349 }; 3350 }; 3351 }; 3352 }; 3353 3354 tpdm@684c000 { 3355 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3356 reg = <0 0x0684c000 0 0x1000>; 3357 3358 clocks = <&aoss_qmp>; 3359 clock-names = "apb_pclk"; 3360 3361 out-ports { 3362 port { 3363 tpdm_prng_out_tpda_23: endpoint { 3364 remote-endpoint = <&tpda_23_in_tpdm_prng>; 3365 }; 3366 }; 3367 }; 3368 }; 3369 3370 funnel@6b04000 { 3371 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3372 arm,primecell-periphid = <0x000bb908>; 3373 3374 reg = <0 0x06b04000 0 0x1000>; 3375 3376 clocks = <&aoss_qmp>; 3377 clock-names = "apb_pclk"; 3378 3379 out-ports { 3380 port { 3381 funnel_swao_out_etf: endpoint { 3382 remote-endpoint = <&etf_in_funnel_swao_out>; 3383 }; 3384 }; 3385 }; 3386 3387 in-ports { 3388 #address-cells = <1>; 3389 #size-cells = <0>; 3390 3391 port@7 { 3392 reg = <7>; 3393 funnel_swao_in_funnel_merg: endpoint { 3394 remote-endpoint = <&funnel_merg_out_funnel_swao>; 3395 }; 3396 }; 3397 }; 3398 }; 3399 3400 etf@6b05000 { 3401 compatible = "arm,coresight-tmc", "arm,primecell"; 3402 reg = <0 0x06b05000 0 0x1000>; 3403 3404 clocks = <&aoss_qmp>; 3405 clock-names = "apb_pclk"; 3406 3407 out-ports { 3408 port { 3409 etf_out: endpoint { 3410 remote-endpoint = <&replicator_in>; 3411 }; 3412 }; 3413 }; 3414 3415 in-ports { 3416 3417 port { 3418 etf_in_funnel_swao_out: endpoint { 3419 remote-endpoint = <&funnel_swao_out_etf>; 3420 }; 3421 }; 3422 }; 3423 }; 3424 3425 replicator@6b06000 { 3426 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3427 reg = <0 0x06b06000 0 0x1000>; 3428 3429 clocks = <&aoss_qmp>; 3430 clock-names = "apb_pclk"; 3431 3432 out-ports { 3433 port { 3434 replicator_swao_out_cx_in: endpoint { 3435 remote-endpoint = <&replicator_cx_in_swao_out>; 3436 }; 3437 }; 3438 }; 3439 3440 in-ports { 3441 port { 3442 replicator_in: endpoint { 3443 remote-endpoint = <&etf_out>; 3444 }; 3445 }; 3446 }; 3447 }; 3448 3449 tpdm@6c08000 { 3450 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3451 reg = <0 0x06c08000 0 0x1000>; 3452 3453 clocks = <&aoss_qmp>; 3454 clock-names = "apb_pclk"; 3455 3456 out-ports { 3457 port { 3458 tpdm_mm_out_funnel_dl_mm: endpoint { 3459 remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>; 3460 }; 3461 }; 3462 }; 3463 }; 3464 3465 funnel@6c0b000 { 3466 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3467 reg = <0 0x06c0b000 0 0x1000>; 3468 3469 clocks = <&aoss_qmp>; 3470 clock-names = "apb_pclk"; 3471 3472 out-ports { 3473 port { 3474 funnel_dl_mm_out_funnel_dl_center: endpoint { 3475 remote-endpoint = <&funnel_dl_center_in_funnel_dl_mm>; 3476 }; 3477 }; 3478 }; 3479 3480 in-ports { 3481 #address-cells = <1>; 3482 #size-cells = <0>; 3483 3484 port@3 { 3485 reg = <3>; 3486 funnel_dl_mm_in_tpdm_mm: endpoint { 3487 remote-endpoint = <&tpdm_mm_out_funnel_dl_mm>; 3488 }; 3489 }; 3490 }; 3491 }; 3492 3493 funnel@6c2d000 { 3494 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3495 reg = <0 0x06c2d000 0 0x1000>; 3496 3497 clocks = <&aoss_qmp>; 3498 clock-names = "apb_pclk"; 3499 3500 out-ports { 3501 port { 3502 tpdm_mm_out_tpda9: endpoint { 3503 remote-endpoint = <&tpda_9_in_tpdm_mm>; 3504 }; 3505 }; 3506 }; 3507 3508 in-ports { 3509 #address-cells = <1>; 3510 #size-cells = <0>; 3511 3512 port@2 { 3513 reg = <2>; 3514 funnel_dl_center_in_funnel_dl_mm: endpoint { 3515 remote-endpoint = <&funnel_dl_mm_out_funnel_dl_center>; 3516 }; 3517 }; 3518 }; 3519 }; 3520 3521 etm@7040000 { 3522 compatible = "arm,coresight-etm4x", "arm,primecell"; 3523 reg = <0 0x07040000 0 0x1000>; 3524 3525 cpu = <&cpu0>; 3526 3527 clocks = <&aoss_qmp>; 3528 clock-names = "apb_pclk"; 3529 arm,coresight-loses-context-with-cpu; 3530 3531 out-ports { 3532 port { 3533 etm0_out: endpoint { 3534 remote-endpoint = <&apss_funnel_in0>; 3535 }; 3536 }; 3537 }; 3538 }; 3539 3540 etm@7140000 { 3541 compatible = "arm,coresight-etm4x", "arm,primecell"; 3542 reg = <0 0x07140000 0 0x1000>; 3543 3544 cpu = <&cpu1>; 3545 3546 clocks = <&aoss_qmp>; 3547 clock-names = "apb_pclk"; 3548 arm,coresight-loses-context-with-cpu; 3549 3550 out-ports { 3551 port { 3552 etm1_out: endpoint { 3553 remote-endpoint = <&apss_funnel_in1>; 3554 }; 3555 }; 3556 }; 3557 }; 3558 3559 etm@7240000 { 3560 compatible = "arm,coresight-etm4x", "arm,primecell"; 3561 reg = <0 0x07240000 0 0x1000>; 3562 3563 cpu = <&cpu2>; 3564 3565 clocks = <&aoss_qmp>; 3566 clock-names = "apb_pclk"; 3567 arm,coresight-loses-context-with-cpu; 3568 3569 out-ports { 3570 port { 3571 etm2_out: endpoint { 3572 remote-endpoint = <&apss_funnel_in2>; 3573 }; 3574 }; 3575 }; 3576 }; 3577 3578 etm@7340000 { 3579 compatible = "arm,coresight-etm4x", "arm,primecell"; 3580 reg = <0 0x07340000 0 0x1000>; 3581 3582 cpu = <&cpu3>; 3583 3584 clocks = <&aoss_qmp>; 3585 clock-names = "apb_pclk"; 3586 arm,coresight-loses-context-with-cpu; 3587 3588 out-ports { 3589 port { 3590 etm3_out: endpoint { 3591 remote-endpoint = <&apss_funnel_in3>; 3592 }; 3593 }; 3594 }; 3595 }; 3596 3597 etm@7440000 { 3598 compatible = "arm,coresight-etm4x", "arm,primecell"; 3599 reg = <0 0x07440000 0 0x1000>; 3600 3601 cpu = <&cpu4>; 3602 3603 clocks = <&aoss_qmp>; 3604 clock-names = "apb_pclk"; 3605 arm,coresight-loses-context-with-cpu; 3606 3607 out-ports { 3608 port { 3609 etm4_out: endpoint { 3610 remote-endpoint = <&apss_funnel_in4>; 3611 }; 3612 }; 3613 }; 3614 }; 3615 3616 etm@7540000 { 3617 compatible = "arm,coresight-etm4x", "arm,primecell"; 3618 reg = <0 0x07540000 0 0x1000>; 3619 3620 cpu = <&cpu5>; 3621 3622 clocks = <&aoss_qmp>; 3623 clock-names = "apb_pclk"; 3624 arm,coresight-loses-context-with-cpu; 3625 3626 out-ports { 3627 port { 3628 etm5_out: endpoint { 3629 remote-endpoint = <&apss_funnel_in5>; 3630 }; 3631 }; 3632 }; 3633 }; 3634 3635 etm@7640000 { 3636 compatible = "arm,coresight-etm4x", "arm,primecell"; 3637 reg = <0 0x07640000 0 0x1000>; 3638 3639 cpu = <&cpu6>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 arm,coresight-loses-context-with-cpu; 3644 3645 out-ports { 3646 port { 3647 etm6_out: endpoint { 3648 remote-endpoint = <&apss_funnel_in6>; 3649 }; 3650 }; 3651 }; 3652 }; 3653 3654 etm@7740000 { 3655 compatible = "arm,coresight-etm4x", "arm,primecell"; 3656 reg = <0 0x07740000 0 0x1000>; 3657 3658 cpu = <&cpu7>; 3659 3660 clocks = <&aoss_qmp>; 3661 clock-names = "apb_pclk"; 3662 arm,coresight-loses-context-with-cpu; 3663 3664 out-ports { 3665 port { 3666 etm7_out: endpoint { 3667 remote-endpoint = <&apss_funnel_in7>; 3668 }; 3669 }; 3670 }; 3671 }; 3672 3673 funnel@7800000 { 3674 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3675 reg = <0 0x07800000 0 0x1000>; 3676 3677 clocks = <&aoss_qmp>; 3678 clock-names = "apb_pclk"; 3679 3680 out-ports { 3681 port { 3682 funnel_apss_out_funnel_apss_merg: endpoint { 3683 remote-endpoint = <&funnel_apss_merg_in_funnel_apss>; 3684 }; 3685 }; 3686 }; 3687 3688 in-ports { 3689 #address-cells = <1>; 3690 #size-cells = <0>; 3691 3692 port@0 { 3693 reg = <0>; 3694 apss_funnel_in0: endpoint { 3695 remote-endpoint = <&etm0_out>; 3696 }; 3697 }; 3698 3699 port@1 { 3700 reg = <1>; 3701 apss_funnel_in1: endpoint { 3702 remote-endpoint = <&etm1_out>; 3703 }; 3704 }; 3705 3706 port@2 { 3707 reg = <2>; 3708 apss_funnel_in2: endpoint { 3709 remote-endpoint = <&etm2_out>; 3710 }; 3711 }; 3712 3713 port@3 { 3714 reg = <3>; 3715 apss_funnel_in3: endpoint { 3716 remote-endpoint = <&etm3_out>; 3717 }; 3718 }; 3719 3720 port@4 { 3721 reg = <4>; 3722 apss_funnel_in4: endpoint { 3723 remote-endpoint = <&etm4_out>; 3724 }; 3725 }; 3726 3727 port@5 { 3728 reg = <5>; 3729 apss_funnel_in5: endpoint { 3730 remote-endpoint = <&etm5_out>; 3731 }; 3732 }; 3733 3734 port@6 { 3735 reg = <6>; 3736 apss_funnel_in6: endpoint { 3737 remote-endpoint = <&etm6_out>; 3738 }; 3739 }; 3740 3741 port@7 { 3742 reg = <7>; 3743 apss_funnel_in7: endpoint { 3744 remote-endpoint = <&etm7_out>; 3745 }; 3746 }; 3747 }; 3748 }; 3749 3750 funnel@7810000 { 3751 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3752 reg = <0 0x07810000 0 0x1000>; 3753 3754 clocks = <&aoss_qmp>; 3755 clock-names = "apb_pclk"; 3756 3757 out-ports { 3758 port { 3759 funnel_apss_merg_out_funnel_in1: endpoint { 3760 remote-endpoint = <&funnel_in1_in_funnel_apss_merg>; 3761 }; 3762 }; 3763 }; 3764 3765 in-ports { 3766 port { 3767 funnel_apss_merg_in_funnel_apss: endpoint { 3768 remote-endpoint = <&funnel_apss_out_funnel_apss_merg>; 3769 }; 3770 }; 3771 }; 3772 }; 3773 3774 cdsp: remoteproc@8300000 { 3775 compatible = "qcom,sm8250-cdsp-pas"; 3776 reg = <0 0x08300000 0 0x10000>; 3777 3778 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3779 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 3780 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 3781 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 3782 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 3783 interrupt-names = "wdog", "fatal", "ready", 3784 "handover", "stop-ack"; 3785 3786 clocks = <&rpmhcc RPMH_CXO_CLK>; 3787 clock-names = "xo"; 3788 3789 power-domains = <&rpmhpd RPMHPD_CX>; 3790 3791 memory-region = <&cdsp_mem>; 3792 3793 qcom,qmp = <&aoss_qmp>; 3794 3795 qcom,smem-states = <&smp2p_cdsp_out 0>; 3796 qcom,smem-state-names = "stop"; 3797 3798 status = "disabled"; 3799 3800 glink-edge { 3801 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 3802 IPCC_MPROC_SIGNAL_GLINK_QMP 3803 IRQ_TYPE_EDGE_RISING>; 3804 mboxes = <&ipcc IPCC_CLIENT_CDSP 3805 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3806 3807 label = "cdsp"; 3808 qcom,remote-pid = <5>; 3809 3810 fastrpc { 3811 compatible = "qcom,fastrpc"; 3812 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3813 label = "cdsp"; 3814 qcom,non-secure-domain; 3815 #address-cells = <1>; 3816 #size-cells = <0>; 3817 3818 compute-cb@1 { 3819 compatible = "qcom,fastrpc-compute-cb"; 3820 reg = <1>; 3821 iommus = <&apps_smmu 0x1001 0x0460>; 3822 }; 3823 3824 compute-cb@2 { 3825 compatible = "qcom,fastrpc-compute-cb"; 3826 reg = <2>; 3827 iommus = <&apps_smmu 0x1002 0x0460>; 3828 }; 3829 3830 compute-cb@3 { 3831 compatible = "qcom,fastrpc-compute-cb"; 3832 reg = <3>; 3833 iommus = <&apps_smmu 0x1003 0x0460>; 3834 }; 3835 3836 compute-cb@4 { 3837 compatible = "qcom,fastrpc-compute-cb"; 3838 reg = <4>; 3839 iommus = <&apps_smmu 0x1004 0x0460>; 3840 }; 3841 3842 compute-cb@5 { 3843 compatible = "qcom,fastrpc-compute-cb"; 3844 reg = <5>; 3845 iommus = <&apps_smmu 0x1005 0x0460>; 3846 }; 3847 3848 compute-cb@6 { 3849 compatible = "qcom,fastrpc-compute-cb"; 3850 reg = <6>; 3851 iommus = <&apps_smmu 0x1006 0x0460>; 3852 }; 3853 3854 compute-cb@7 { 3855 compatible = "qcom,fastrpc-compute-cb"; 3856 reg = <7>; 3857 iommus = <&apps_smmu 0x1007 0x0460>; 3858 }; 3859 3860 compute-cb@8 { 3861 compatible = "qcom,fastrpc-compute-cb"; 3862 reg = <8>; 3863 iommus = <&apps_smmu 0x1008 0x0460>; 3864 }; 3865 3866 /* note: secure cb9 in downstream */ 3867 }; 3868 }; 3869 }; 3870 3871 usb_1_hsphy: phy@88e3000 { 3872 compatible = "qcom,sm8250-usb-hs-phy", 3873 "qcom,usb-snps-hs-7nm-phy"; 3874 reg = <0 0x088e3000 0 0x400>; 3875 status = "disabled"; 3876 #phy-cells = <0>; 3877 3878 clocks = <&rpmhcc RPMH_CXO_CLK>; 3879 clock-names = "ref"; 3880 3881 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 3882 }; 3883 3884 usb_2_hsphy: phy@88e4000 { 3885 compatible = "qcom,sm8250-usb-hs-phy", 3886 "qcom,usb-snps-hs-7nm-phy"; 3887 reg = <0 0x088e4000 0 0x400>; 3888 status = "disabled"; 3889 #phy-cells = <0>; 3890 3891 clocks = <&rpmhcc RPMH_CXO_CLK>; 3892 clock-names = "ref"; 3893 3894 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3895 }; 3896 3897 usb_1_qmpphy: phy@88e8000 { 3898 compatible = "qcom,sm8250-qmp-usb3-dp-phy"; 3899 reg = <0 0x088e8000 0 0x3000>; 3900 status = "disabled"; 3901 3902 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3903 <&rpmhcc RPMH_CXO_CLK>, 3904 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3905 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3906 clock-names = "aux", 3907 "ref", 3908 "com_aux", 3909 "usb3_pipe"; 3910 3911 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 3912 <&gcc GCC_USB3_PHY_PRIM_BCR>; 3913 reset-names = "phy", "common"; 3914 3915 #clock-cells = <1>; 3916 #phy-cells = <1>; 3917 3918 orientation-switch; 3919 3920 ports { 3921 #address-cells = <1>; 3922 #size-cells = <0>; 3923 3924 port@0 { 3925 reg = <0>; 3926 usb_1_qmpphy_out: endpoint {}; 3927 }; 3928 3929 port@1 { 3930 reg = <1>; 3931 3932 usb_1_qmpphy_usb_ss_in: endpoint { 3933 remote-endpoint = <&usb_1_dwc3_ss_out>; 3934 }; 3935 }; 3936 3937 port@2 { 3938 reg = <2>; 3939 3940 usb_1_qmpphy_dp_in: endpoint {}; 3941 }; 3942 }; 3943 }; 3944 3945 usb_2_qmpphy: phy@88eb000 { 3946 compatible = "qcom,sm8250-qmp-usb3-uni-phy"; 3947 reg = <0 0x088eb000 0 0x1000>; 3948 3949 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3950 <&gcc GCC_USB3_SEC_CLKREF_EN>, 3951 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3952 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3953 clock-names = "aux", 3954 "ref", 3955 "com_aux", 3956 "pipe"; 3957 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 3958 #clock-cells = <0>; 3959 #phy-cells = <0>; 3960 3961 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3962 <&gcc GCC_USB3PHY_PHY_SEC_BCR>; 3963 reset-names = "phy", 3964 "phy_phy"; 3965 3966 status = "disabled"; 3967 }; 3968 3969 sdhc_2: mmc@8804000 { 3970 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; 3971 reg = <0 0x08804000 0 0x1000>; 3972 3973 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3974 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3975 interrupt-names = "hc_irq", "pwr_irq"; 3976 3977 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3978 <&gcc GCC_SDCC2_APPS_CLK>, 3979 <&rpmhcc RPMH_CXO_CLK>; 3980 clock-names = "iface", "core", "xo"; 3981 iommus = <&apps_smmu 0x4a0 0x0>; 3982 qcom,dll-config = <0x0007642c>; 3983 qcom,ddr-config = <0x80040868>; 3984 power-domains = <&rpmhpd RPMHPD_CX>; 3985 operating-points-v2 = <&sdhc2_opp_table>; 3986 3987 status = "disabled"; 3988 3989 sdhc2_opp_table: opp-table { 3990 compatible = "operating-points-v2"; 3991 3992 opp-19200000 { 3993 opp-hz = /bits/ 64 <19200000>; 3994 required-opps = <&rpmhpd_opp_min_svs>; 3995 }; 3996 3997 opp-50000000 { 3998 opp-hz = /bits/ 64 <50000000>; 3999 required-opps = <&rpmhpd_opp_low_svs>; 4000 }; 4001 4002 opp-100000000 { 4003 opp-hz = /bits/ 64 <100000000>; 4004 required-opps = <&rpmhpd_opp_svs>; 4005 }; 4006 4007 opp-202000000 { 4008 opp-hz = /bits/ 64 <202000000>; 4009 required-opps = <&rpmhpd_opp_svs_l1>; 4010 }; 4011 }; 4012 }; 4013 4014 pmu@9091000 { 4015 compatible = "qcom,sm8250-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4016 reg = <0 0x09091000 0 0x1000>; 4017 4018 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4019 4020 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI_CH0 3>; 4021 4022 operating-points-v2 = <&llcc_bwmon_opp_table>; 4023 4024 llcc_bwmon_opp_table: opp-table { 4025 compatible = "operating-points-v2"; 4026 4027 opp-800000 { 4028 opp-peak-kBps = <(200 * 4 * 1000)>; 4029 }; 4030 4031 opp-1200000 { 4032 opp-peak-kBps = <(300 * 4 * 1000)>; 4033 }; 4034 4035 opp-1804000 { 4036 opp-peak-kBps = <(451 * 4 * 1000)>; 4037 }; 4038 4039 opp-2188000 { 4040 opp-peak-kBps = <(547 * 4 * 1000)>; 4041 }; 4042 4043 opp-2724000 { 4044 opp-peak-kBps = <(681 * 4 * 1000)>; 4045 }; 4046 4047 opp-3072000 { 4048 opp-peak-kBps = <(768 * 4 * 1000)>; 4049 }; 4050 4051 opp-4068000 { 4052 opp-peak-kBps = <(1017 * 4 * 1000)>; 4053 }; 4054 4055 /* 1353 MHz, LPDDR4X */ 4056 4057 opp-6220000 { 4058 opp-peak-kBps = <(1555 * 4 * 1000)>; 4059 }; 4060 4061 opp-7216000 { 4062 opp-peak-kBps = <(1804 * 4 * 1000)>; 4063 }; 4064 4065 opp-8368000 { 4066 opp-peak-kBps = <(2092 * 4 * 1000)>; 4067 }; 4068 4069 /* LPDDR5 */ 4070 opp-10944000 { 4071 opp-peak-kBps = <(2736 * 4 * 1000)>; 4072 }; 4073 }; 4074 }; 4075 4076 pmu@90b6400 { 4077 compatible = "qcom,sm8250-cpu-bwmon", "qcom,sdm845-bwmon"; 4078 reg = <0 0x090b6400 0 0x600>; 4079 4080 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4081 4082 interconnects = <&gem_noc MASTER_AMPSS_M0 3 &gem_noc SLAVE_LLCC 3>; 4083 operating-points-v2 = <&cpu_bwmon_opp_table>; 4084 4085 cpu_bwmon_opp_table: opp-table { 4086 compatible = "operating-points-v2"; 4087 4088 opp-800000 { 4089 opp-peak-kBps = <(200 * 4 * 1000)>; 4090 }; 4091 4092 opp-1804000 { 4093 opp-peak-kBps = <(451 * 4 * 1000)>; 4094 }; 4095 4096 opp-2188000 { 4097 opp-peak-kBps = <(547 * 4 * 1000)>; 4098 }; 4099 4100 opp-2724000 { 4101 opp-peak-kBps = <(681 * 4 * 1000)>; 4102 }; 4103 4104 opp-3072000 { 4105 opp-peak-kBps = <(768 * 4 * 1000)>; 4106 }; 4107 4108 /* 1017MHz, 1353 MHz, LPDDR4X */ 4109 4110 opp-6220000 { 4111 opp-peak-kBps = <(1555 * 4 * 1000)>; 4112 }; 4113 4114 opp-6832000 { 4115 opp-peak-kBps = <(1708 * 4 * 1000)>; 4116 }; 4117 4118 opp-8368000 { 4119 opp-peak-kBps = <(2092 * 4 * 1000)>; 4120 }; 4121 4122 /* 2133MHz, LPDDR4X */ 4123 4124 /* LPDDR5 */ 4125 opp-10944000 { 4126 opp-peak-kBps = <(2736 * 4 * 1000)>; 4127 }; 4128 4129 /* LPDDR5 */ 4130 opp-12784000 { 4131 opp-peak-kBps = <(3196 * 4 * 1000)>; 4132 }; 4133 }; 4134 }; 4135 4136 dc_noc: interconnect@90c0000 { 4137 compatible = "qcom,sm8250-dc-noc"; 4138 reg = <0 0x090c0000 0 0x4200>; 4139 #interconnect-cells = <2>; 4140 qcom,bcm-voters = <&apps_bcm_voter>; 4141 }; 4142 4143 gem_noc: interconnect@9100000 { 4144 compatible = "qcom,sm8250-gem-noc"; 4145 reg = <0 0x09100000 0 0xb4000>; 4146 #interconnect-cells = <2>; 4147 qcom,bcm-voters = <&apps_bcm_voter>; 4148 }; 4149 4150 npu_noc: interconnect@9990000 { 4151 compatible = "qcom,sm8250-npu-noc"; 4152 reg = <0 0x09990000 0 0x1600>; 4153 #interconnect-cells = <2>; 4154 qcom,bcm-voters = <&apps_bcm_voter>; 4155 }; 4156 4157 usb_1: usb@a6f8800 { 4158 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4159 reg = <0 0x0a6f8800 0 0x400>; 4160 status = "disabled"; 4161 #address-cells = <2>; 4162 #size-cells = <2>; 4163 ranges; 4164 dma-ranges; 4165 4166 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4167 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4168 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4169 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4170 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4171 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4172 clock-names = "cfg_noc", 4173 "core", 4174 "iface", 4175 "sleep", 4176 "mock_utmi", 4177 "xo"; 4178 4179 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4180 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4181 assigned-clock-rates = <19200000>, <200000000>; 4182 4183 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4184 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4185 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4186 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4187 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4188 interrupt-names = "pwr_event", 4189 "hs_phy_irq", 4190 "dp_hs_phy_irq", 4191 "dm_hs_phy_irq", 4192 "ss_phy_irq"; 4193 4194 power-domains = <&gcc USB30_PRIM_GDSC>; 4195 wakeup-source; 4196 4197 resets = <&gcc GCC_USB30_PRIM_BCR>; 4198 4199 interconnects = <&aggre1_noc MASTER_USB3 0 &mc_virt SLAVE_EBI_CH0 0>, 4200 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 4201 interconnect-names = "usb-ddr", "apps-usb"; 4202 4203 usb_1_dwc3: usb@a600000 { 4204 compatible = "snps,dwc3"; 4205 reg = <0 0x0a600000 0 0xcd00>; 4206 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4207 iommus = <&apps_smmu 0x0 0x0>; 4208 snps,dis_u2_susphy_quirk; 4209 snps,dis_enblslpm_quirk; 4210 snps,dis-u1-entry-quirk; 4211 snps,dis-u2-entry-quirk; 4212 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4213 phy-names = "usb2-phy", "usb3-phy"; 4214 4215 ports { 4216 #address-cells = <1>; 4217 #size-cells = <0>; 4218 4219 port@0 { 4220 reg = <0>; 4221 4222 usb_1_dwc3_hs_out: endpoint { 4223 }; 4224 }; 4225 4226 port@1 { 4227 reg = <1>; 4228 4229 usb_1_dwc3_ss_out: endpoint { 4230 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 4231 }; 4232 }; 4233 }; 4234 }; 4235 }; 4236 4237 system-cache-controller@9200000 { 4238 compatible = "qcom,sm8250-llcc"; 4239 reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, 4240 <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, 4241 <0 0x09600000 0 0x50000>; 4242 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 4243 "llcc3_base", "llcc_broadcast_base"; 4244 }; 4245 4246 usb_2: usb@a8f8800 { 4247 compatible = "qcom,sm8250-dwc3", "qcom,dwc3"; 4248 reg = <0 0x0a8f8800 0 0x400>; 4249 status = "disabled"; 4250 #address-cells = <2>; 4251 #size-cells = <2>; 4252 ranges; 4253 dma-ranges; 4254 4255 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4256 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4257 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4258 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4259 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4260 <&gcc GCC_USB3_SEC_CLKREF_EN>; 4261 clock-names = "cfg_noc", 4262 "core", 4263 "iface", 4264 "sleep", 4265 "mock_utmi", 4266 "xo"; 4267 4268 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4269 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4270 assigned-clock-rates = <19200000>, <200000000>; 4271 4272 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4273 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 4274 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4275 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 4276 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>; 4277 interrupt-names = "pwr_event", 4278 "hs_phy_irq", 4279 "dp_hs_phy_irq", 4280 "dm_hs_phy_irq", 4281 "ss_phy_irq"; 4282 4283 power-domains = <&gcc USB30_SEC_GDSC>; 4284 wakeup-source; 4285 4286 resets = <&gcc GCC_USB30_SEC_BCR>; 4287 4288 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI_CH0 0>, 4289 <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3_1 0>; 4290 interconnect-names = "usb-ddr", "apps-usb"; 4291 4292 usb_2_dwc3: usb@a800000 { 4293 compatible = "snps,dwc3"; 4294 reg = <0 0x0a800000 0 0xcd00>; 4295 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4296 iommus = <&apps_smmu 0x20 0>; 4297 snps,dis_u2_susphy_quirk; 4298 snps,dis_enblslpm_quirk; 4299 snps,dis-u1-entry-quirk; 4300 snps,dis-u2-entry-quirk; 4301 phys = <&usb_2_hsphy>, <&usb_2_qmpphy>; 4302 phy-names = "usb2-phy", "usb3-phy"; 4303 }; 4304 }; 4305 4306 venus: video-codec@aa00000 { 4307 compatible = "qcom,sm8250-venus"; 4308 reg = <0 0x0aa00000 0 0x100000>; 4309 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4310 power-domains = <&videocc MVS0C_GDSC>, 4311 <&videocc MVS0_GDSC>, 4312 <&rpmhpd RPMHPD_MX>; 4313 power-domain-names = "venus", "vcodec0", "mx"; 4314 operating-points-v2 = <&venus_opp_table>; 4315 4316 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4317 <&videocc VIDEO_CC_MVS0C_CLK>, 4318 <&videocc VIDEO_CC_MVS0_CLK>; 4319 clock-names = "iface", "core", "vcodec0_core"; 4320 4321 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_VENUS_CFG 0>, 4322 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI_CH0 0>; 4323 interconnect-names = "cpu-cfg", "video-mem"; 4324 4325 iommus = <&apps_smmu 0x2100 0x0400>; 4326 memory-region = <&video_mem>; 4327 4328 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, 4329 <&videocc VIDEO_CC_MVS0C_CLK_ARES>; 4330 reset-names = "bus", "core"; 4331 4332 status = "disabled"; 4333 4334 video-decoder { 4335 compatible = "venus-decoder"; 4336 }; 4337 4338 video-encoder { 4339 compatible = "venus-encoder"; 4340 }; 4341 4342 venus_opp_table: opp-table { 4343 compatible = "operating-points-v2"; 4344 4345 opp-720000000 { 4346 opp-hz = /bits/ 64 <720000000>; 4347 required-opps = <&rpmhpd_opp_low_svs>; 4348 }; 4349 4350 opp-1014000000 { 4351 opp-hz = /bits/ 64 <1014000000>; 4352 required-opps = <&rpmhpd_opp_svs>; 4353 }; 4354 4355 opp-1098000000 { 4356 opp-hz = /bits/ 64 <1098000000>; 4357 required-opps = <&rpmhpd_opp_svs_l1>; 4358 }; 4359 4360 opp-1332000000 { 4361 opp-hz = /bits/ 64 <1332000000>; 4362 required-opps = <&rpmhpd_opp_nom>; 4363 }; 4364 }; 4365 }; 4366 4367 videocc: clock-controller@abf0000 { 4368 compatible = "qcom,sm8250-videocc"; 4369 reg = <0 0x0abf0000 0 0x10000>; 4370 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4371 <&rpmhcc RPMH_CXO_CLK>, 4372 <&rpmhcc RPMH_CXO_CLK_A>; 4373 power-domains = <&rpmhpd RPMHPD_MMCX>; 4374 required-opps = <&rpmhpd_opp_low_svs>; 4375 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao"; 4376 #clock-cells = <1>; 4377 #reset-cells = <1>; 4378 #power-domain-cells = <1>; 4379 }; 4380 4381 cci0: cci@ac4f000 { 4382 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4383 #address-cells = <1>; 4384 #size-cells = <0>; 4385 4386 reg = <0 0x0ac4f000 0 0x1000>; 4387 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 4388 power-domains = <&camcc TITAN_TOP_GDSC>; 4389 4390 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4391 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4392 <&camcc CAM_CC_CPAS_AHB_CLK>, 4393 <&camcc CAM_CC_CCI_0_CLK>, 4394 <&camcc CAM_CC_CCI_0_CLK_SRC>; 4395 clock-names = "camnoc_axi", 4396 "slow_ahb_src", 4397 "cpas_ahb", 4398 "cci", 4399 "cci_src"; 4400 4401 pinctrl-0 = <&cci0_default>; 4402 pinctrl-1 = <&cci0_sleep>; 4403 pinctrl-names = "default", "sleep"; 4404 4405 status = "disabled"; 4406 4407 cci0_i2c0: i2c-bus@0 { 4408 reg = <0>; 4409 clock-frequency = <1000000>; 4410 #address-cells = <1>; 4411 #size-cells = <0>; 4412 }; 4413 4414 cci0_i2c1: i2c-bus@1 { 4415 reg = <1>; 4416 clock-frequency = <1000000>; 4417 #address-cells = <1>; 4418 #size-cells = <0>; 4419 }; 4420 }; 4421 4422 cci1: cci@ac50000 { 4423 compatible = "qcom,sm8250-cci", "qcom,msm8996-cci"; 4424 #address-cells = <1>; 4425 #size-cells = <0>; 4426 4427 reg = <0 0x0ac50000 0 0x1000>; 4428 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 4429 power-domains = <&camcc TITAN_TOP_GDSC>; 4430 4431 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4432 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4433 <&camcc CAM_CC_CPAS_AHB_CLK>, 4434 <&camcc CAM_CC_CCI_1_CLK>, 4435 <&camcc CAM_CC_CCI_1_CLK_SRC>; 4436 clock-names = "camnoc_axi", 4437 "slow_ahb_src", 4438 "cpas_ahb", 4439 "cci", 4440 "cci_src"; 4441 4442 pinctrl-0 = <&cci1_default>; 4443 pinctrl-1 = <&cci1_sleep>; 4444 pinctrl-names = "default", "sleep"; 4445 4446 status = "disabled"; 4447 4448 cci1_i2c0: i2c-bus@0 { 4449 reg = <0>; 4450 clock-frequency = <1000000>; 4451 #address-cells = <1>; 4452 #size-cells = <0>; 4453 }; 4454 4455 cci1_i2c1: i2c-bus@1 { 4456 reg = <1>; 4457 clock-frequency = <1000000>; 4458 #address-cells = <1>; 4459 #size-cells = <0>; 4460 }; 4461 }; 4462 4463 camss: camss@ac6a000 { 4464 compatible = "qcom,sm8250-camss"; 4465 status = "disabled"; 4466 4467 reg = <0 0x0ac6a000 0 0x2000>, 4468 <0 0x0ac6c000 0 0x2000>, 4469 <0 0x0ac6e000 0 0x1000>, 4470 <0 0x0ac70000 0 0x1000>, 4471 <0 0x0ac72000 0 0x1000>, 4472 <0 0x0ac74000 0 0x1000>, 4473 <0 0x0acb4000 0 0xd000>, 4474 <0 0x0acc3000 0 0xd000>, 4475 <0 0x0acd9000 0 0x2200>, 4476 <0 0x0acdb200 0 0x2200>; 4477 reg-names = "csiphy0", 4478 "csiphy1", 4479 "csiphy2", 4480 "csiphy3", 4481 "csiphy4", 4482 "csiphy5", 4483 "vfe0", 4484 "vfe1", 4485 "vfe_lite0", 4486 "vfe_lite1"; 4487 4488 interrupts = <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 4489 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 4490 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 4491 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 4492 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 4493 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 4494 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 4495 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 4496 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 4497 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 4498 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 4499 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 4500 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 4501 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 4502 interrupt-names = "csiphy0", 4503 "csiphy1", 4504 "csiphy2", 4505 "csiphy3", 4506 "csiphy4", 4507 "csiphy5", 4508 "csid0", 4509 "csid1", 4510 "csid2", 4511 "csid3", 4512 "vfe0", 4513 "vfe1", 4514 "vfe_lite0", 4515 "vfe_lite1"; 4516 4517 power-domains = <&camcc IFE_0_GDSC>, 4518 <&camcc IFE_1_GDSC>, 4519 <&camcc TITAN_TOP_GDSC>; 4520 4521 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4522 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4523 <&gcc GCC_CAMERA_SF_AXI_CLK>, 4524 <&camcc CAM_CC_CAMNOC_AXI_CLK>, 4525 <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, 4526 <&camcc CAM_CC_CORE_AHB_CLK>, 4527 <&camcc CAM_CC_CPAS_AHB_CLK>, 4528 <&camcc CAM_CC_CSIPHY0_CLK>, 4529 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 4530 <&camcc CAM_CC_CSIPHY1_CLK>, 4531 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 4532 <&camcc CAM_CC_CSIPHY2_CLK>, 4533 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 4534 <&camcc CAM_CC_CSIPHY3_CLK>, 4535 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 4536 <&camcc CAM_CC_CSIPHY4_CLK>, 4537 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 4538 <&camcc CAM_CC_CSIPHY5_CLK>, 4539 <&camcc CAM_CC_CSI5PHYTIMER_CLK>, 4540 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 4541 <&camcc CAM_CC_IFE_0_AHB_CLK>, 4542 <&camcc CAM_CC_IFE_0_AXI_CLK>, 4543 <&camcc CAM_CC_IFE_0_CLK>, 4544 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 4545 <&camcc CAM_CC_IFE_0_CSID_CLK>, 4546 <&camcc CAM_CC_IFE_0_AREG_CLK>, 4547 <&camcc CAM_CC_IFE_1_AHB_CLK>, 4548 <&camcc CAM_CC_IFE_1_AXI_CLK>, 4549 <&camcc CAM_CC_IFE_1_CLK>, 4550 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 4551 <&camcc CAM_CC_IFE_1_CSID_CLK>, 4552 <&camcc CAM_CC_IFE_1_AREG_CLK>, 4553 <&camcc CAM_CC_IFE_LITE_AHB_CLK>, 4554 <&camcc CAM_CC_IFE_LITE_AXI_CLK>, 4555 <&camcc CAM_CC_IFE_LITE_CLK>, 4556 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, 4557 <&camcc CAM_CC_IFE_LITE_CSID_CLK>; 4558 4559 clock-names = "cam_ahb_clk", 4560 "cam_hf_axi", 4561 "cam_sf_axi", 4562 "camnoc_axi", 4563 "camnoc_axi_src", 4564 "core_ahb", 4565 "cpas_ahb", 4566 "csiphy0", 4567 "csiphy0_timer", 4568 "csiphy1", 4569 "csiphy1_timer", 4570 "csiphy2", 4571 "csiphy2_timer", 4572 "csiphy3", 4573 "csiphy3_timer", 4574 "csiphy4", 4575 "csiphy4_timer", 4576 "csiphy5", 4577 "csiphy5_timer", 4578 "slow_ahb_src", 4579 "vfe0_ahb", 4580 "vfe0_axi", 4581 "vfe0", 4582 "vfe0_cphy_rx", 4583 "vfe0_csid", 4584 "vfe0_areg", 4585 "vfe1_ahb", 4586 "vfe1_axi", 4587 "vfe1", 4588 "vfe1_cphy_rx", 4589 "vfe1_csid", 4590 "vfe1_areg", 4591 "vfe_lite_ahb", 4592 "vfe_lite_axi", 4593 "vfe_lite", 4594 "vfe_lite_cphy_rx", 4595 "vfe_lite_csid"; 4596 4597 iommus = <&apps_smmu 0x800 0x400>, 4598 <&apps_smmu 0x801 0x400>, 4599 <&apps_smmu 0x840 0x400>, 4600 <&apps_smmu 0x841 0x400>, 4601 <&apps_smmu 0xc00 0x400>, 4602 <&apps_smmu 0xc01 0x400>, 4603 <&apps_smmu 0xc40 0x400>, 4604 <&apps_smmu 0xc41 0x400>; 4605 4606 interconnects = <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_CAMERA_CFG 0>, 4607 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI_CH0 0>, 4608 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI_CH0 0>, 4609 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI_CH0 0>; 4610 interconnect-names = "cam_ahb", 4611 "cam_hf_0_mnoc", 4612 "cam_sf_0_mnoc", 4613 "cam_sf_icp_mnoc"; 4614 4615 ports { 4616 #address-cells = <1>; 4617 #size-cells = <0>; 4618 4619 port@0 { 4620 reg = <0>; 4621 }; 4622 4623 port@1 { 4624 reg = <1>; 4625 }; 4626 4627 port@2 { 4628 reg = <2>; 4629 }; 4630 4631 port@3 { 4632 reg = <3>; 4633 }; 4634 4635 port@4 { 4636 reg = <4>; 4637 }; 4638 4639 port@5 { 4640 reg = <5>; 4641 }; 4642 }; 4643 }; 4644 4645 camcc: clock-controller@ad00000 { 4646 compatible = "qcom,sm8250-camcc"; 4647 reg = <0 0x0ad00000 0 0x10000>; 4648 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4649 <&rpmhcc RPMH_CXO_CLK>, 4650 <&rpmhcc RPMH_CXO_CLK_A>, 4651 <&sleep_clk>; 4652 clock-names = "iface", "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 4653 power-domains = <&rpmhpd RPMHPD_MMCX>; 4654 required-opps = <&rpmhpd_opp_low_svs>; 4655 status = "disabled"; 4656 #clock-cells = <1>; 4657 #reset-cells = <1>; 4658 #power-domain-cells = <1>; 4659 }; 4660 4661 mdss: display-subsystem@ae00000 { 4662 compatible = "qcom,sm8250-mdss"; 4663 reg = <0 0x0ae00000 0 0x1000>; 4664 reg-names = "mdss"; 4665 4666 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mc_virt SLAVE_EBI_CH0 0>, 4667 <&mmss_noc MASTER_MDP_PORT1 0 &mc_virt SLAVE_EBI_CH0 0>; 4668 interconnect-names = "mdp0-mem", "mdp1-mem"; 4669 4670 power-domains = <&dispcc MDSS_GDSC>; 4671 4672 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4673 <&gcc GCC_DISP_HF_AXI_CLK>, 4674 <&gcc GCC_DISP_SF_AXI_CLK>, 4675 <&dispcc DISP_CC_MDSS_MDP_CLK>; 4676 clock-names = "iface", "bus", "nrt_bus", "core"; 4677 4678 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4679 interrupt-controller; 4680 #interrupt-cells = <1>; 4681 4682 iommus = <&apps_smmu 0x820 0x402>; 4683 4684 status = "disabled"; 4685 4686 #address-cells = <2>; 4687 #size-cells = <2>; 4688 ranges; 4689 4690 mdss_mdp: display-controller@ae01000 { 4691 compatible = "qcom,sm8250-dpu"; 4692 reg = <0 0x0ae01000 0 0x8f000>, 4693 <0 0x0aeb0000 0 0x2008>; 4694 reg-names = "mdp", "vbif"; 4695 4696 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4697 <&gcc GCC_DISP_HF_AXI_CLK>, 4698 <&dispcc DISP_CC_MDSS_MDP_CLK>, 4699 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4700 clock-names = "iface", "bus", "core", "vsync"; 4701 4702 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 4703 assigned-clock-rates = <19200000>; 4704 4705 operating-points-v2 = <&mdp_opp_table>; 4706 power-domains = <&rpmhpd RPMHPD_MMCX>; 4707 4708 interrupt-parent = <&mdss>; 4709 interrupts = <0>; 4710 4711 ports { 4712 #address-cells = <1>; 4713 #size-cells = <0>; 4714 4715 port@0 { 4716 reg = <0>; 4717 dpu_intf1_out: endpoint { 4718 remote-endpoint = <&mdss_dsi0_in>; 4719 }; 4720 }; 4721 4722 port@1 { 4723 reg = <1>; 4724 dpu_intf2_out: endpoint { 4725 remote-endpoint = <&mdss_dsi1_in>; 4726 }; 4727 }; 4728 4729 port@2 { 4730 reg = <2>; 4731 4732 dpu_intf0_out: endpoint { 4733 remote-endpoint = <&mdss_dp_in>; 4734 }; 4735 }; 4736 }; 4737 4738 mdp_opp_table: opp-table { 4739 compatible = "operating-points-v2"; 4740 4741 opp-200000000 { 4742 opp-hz = /bits/ 64 <200000000>; 4743 required-opps = <&rpmhpd_opp_low_svs>; 4744 }; 4745 4746 opp-300000000 { 4747 opp-hz = /bits/ 64 <300000000>; 4748 required-opps = <&rpmhpd_opp_svs>; 4749 }; 4750 4751 opp-345000000 { 4752 opp-hz = /bits/ 64 <345000000>; 4753 required-opps = <&rpmhpd_opp_svs_l1>; 4754 }; 4755 4756 opp-460000000 { 4757 opp-hz = /bits/ 64 <460000000>; 4758 required-opps = <&rpmhpd_opp_nom>; 4759 }; 4760 }; 4761 }; 4762 4763 mdss_dp: displayport-controller@ae90000 { 4764 compatible = "qcom,sm8250-dp", "qcom,sm8350-dp"; 4765 reg = <0 0xae90000 0 0x200>, 4766 <0 0xae90200 0 0x200>, 4767 <0 0xae90400 0 0x600>, 4768 <0 0xae91000 0 0x400>, 4769 <0 0xae91400 0 0x400>; 4770 interrupt-parent = <&mdss>; 4771 interrupts = <12>; 4772 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4773 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 4774 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 4775 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 4776 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 4777 clock-names = "core_iface", 4778 "core_aux", 4779 "ctrl_link", 4780 "ctrl_link_iface", 4781 "stream_pixel"; 4782 4783 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 4784 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 4785 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4786 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4787 4788 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4789 phy-names = "dp"; 4790 4791 #sound-dai-cells = <0>; 4792 4793 operating-points-v2 = <&dp_opp_table>; 4794 power-domains = <&rpmhpd SM8250_MMCX>; 4795 4796 status = "disabled"; 4797 4798 ports { 4799 #address-cells = <1>; 4800 #size-cells = <0>; 4801 4802 port@0 { 4803 reg = <0>; 4804 mdss_dp_in: endpoint { 4805 remote-endpoint = <&dpu_intf0_out>; 4806 }; 4807 }; 4808 4809 port@1 { 4810 reg = <1>; 4811 4812 mdss_dp_out: endpoint { 4813 }; 4814 }; 4815 }; 4816 4817 dp_opp_table: opp-table { 4818 compatible = "operating-points-v2"; 4819 4820 opp-160000000 { 4821 opp-hz = /bits/ 64 <160000000>; 4822 required-opps = <&rpmhpd_opp_low_svs>; 4823 }; 4824 4825 opp-270000000 { 4826 opp-hz = /bits/ 64 <270000000>; 4827 required-opps = <&rpmhpd_opp_svs>; 4828 }; 4829 4830 opp-540000000 { 4831 opp-hz = /bits/ 64 <540000000>; 4832 required-opps = <&rpmhpd_opp_svs_l1>; 4833 }; 4834 4835 opp-810000000 { 4836 opp-hz = /bits/ 64 <810000000>; 4837 required-opps = <&rpmhpd_opp_nom>; 4838 }; 4839 }; 4840 }; 4841 4842 mdss_dsi0: dsi@ae94000 { 4843 compatible = "qcom,sm8250-dsi-ctrl", 4844 "qcom,mdss-dsi-ctrl"; 4845 reg = <0 0x0ae94000 0 0x400>; 4846 reg-names = "dsi_ctrl"; 4847 4848 interrupt-parent = <&mdss>; 4849 interrupts = <4>; 4850 4851 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 4852 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 4853 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 4854 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 4855 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4856 <&gcc GCC_DISP_HF_AXI_CLK>; 4857 clock-names = "byte", 4858 "byte_intf", 4859 "pixel", 4860 "core", 4861 "iface", 4862 "bus"; 4863 4864 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 4865 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; 4866 4867 operating-points-v2 = <&dsi_opp_table>; 4868 power-domains = <&rpmhpd RPMHPD_MMCX>; 4869 4870 phys = <&mdss_dsi0_phy>; 4871 4872 status = "disabled"; 4873 4874 #address-cells = <1>; 4875 #size-cells = <0>; 4876 4877 ports { 4878 #address-cells = <1>; 4879 #size-cells = <0>; 4880 4881 port@0 { 4882 reg = <0>; 4883 mdss_dsi0_in: endpoint { 4884 remote-endpoint = <&dpu_intf1_out>; 4885 }; 4886 }; 4887 4888 port@1 { 4889 reg = <1>; 4890 mdss_dsi0_out: endpoint { 4891 }; 4892 }; 4893 }; 4894 4895 dsi_opp_table: opp-table { 4896 compatible = "operating-points-v2"; 4897 4898 opp-187500000 { 4899 opp-hz = /bits/ 64 <187500000>; 4900 required-opps = <&rpmhpd_opp_low_svs>; 4901 }; 4902 4903 opp-300000000 { 4904 opp-hz = /bits/ 64 <300000000>; 4905 required-opps = <&rpmhpd_opp_svs>; 4906 }; 4907 4908 opp-358000000 { 4909 opp-hz = /bits/ 64 <358000000>; 4910 required-opps = <&rpmhpd_opp_svs_l1>; 4911 }; 4912 }; 4913 }; 4914 4915 mdss_dsi0_phy: phy@ae94400 { 4916 compatible = "qcom,dsi-phy-7nm"; 4917 reg = <0 0x0ae94400 0 0x200>, 4918 <0 0x0ae94600 0 0x280>, 4919 <0 0x0ae94900 0 0x260>; 4920 reg-names = "dsi_phy", 4921 "dsi_phy_lane", 4922 "dsi_pll"; 4923 4924 #clock-cells = <1>; 4925 #phy-cells = <0>; 4926 4927 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 4928 <&rpmhcc RPMH_CXO_CLK>; 4929 clock-names = "iface", "ref"; 4930 4931 status = "disabled"; 4932 }; 4933 4934 mdss_dsi1: dsi@ae96000 { 4935 compatible = "qcom,sm8250-dsi-ctrl", 4936 "qcom,mdss-dsi-ctrl"; 4937 reg = <0 0x0ae96000 0 0x400>; 4938 reg-names = "dsi_ctrl"; 4939 4940 interrupt-parent = <&mdss>; 4941 interrupts = <5>; 4942 4943 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 4944 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 4945 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 4946 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 4947 <&dispcc DISP_CC_MDSS_AHB_CLK>, 4948 <&gcc GCC_DISP_HF_AXI_CLK>; 4949 clock-names = "byte", 4950 "byte_intf", 4951 "pixel", 4952 "core", 4953 "iface", 4954 "bus"; 4955 4956 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 4957 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 4958 4959 operating-points-v2 = <&dsi_opp_table>; 4960 power-domains = <&rpmhpd RPMHPD_MMCX>; 4961 4962 phys = <&mdss_dsi1_phy>; 4963 4964 status = "disabled"; 4965 4966 #address-cells = <1>; 4967 #size-cells = <0>; 4968 4969 ports { 4970 #address-cells = <1>; 4971 #size-cells = <0>; 4972 4973 port@0 { 4974 reg = <0>; 4975 mdss_dsi1_in: endpoint { 4976 remote-endpoint = <&dpu_intf2_out>; 4977 }; 4978 }; 4979 4980 port@1 { 4981 reg = <1>; 4982 mdss_dsi1_out: endpoint { 4983 }; 4984 }; 4985 }; 4986 }; 4987 4988 mdss_dsi1_phy: phy@ae96400 { 4989 compatible = "qcom,dsi-phy-7nm"; 4990 reg = <0 0x0ae96400 0 0x200>, 4991 <0 0x0ae96600 0 0x280>, 4992 <0 0x0ae96900 0 0x260>; 4993 reg-names = "dsi_phy", 4994 "dsi_phy_lane", 4995 "dsi_pll"; 4996 4997 #clock-cells = <1>; 4998 #phy-cells = <0>; 4999 5000 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5001 <&rpmhcc RPMH_CXO_CLK>; 5002 clock-names = "iface", "ref"; 5003 5004 status = "disabled"; 5005 }; 5006 }; 5007 5008 dispcc: clock-controller@af00000 { 5009 compatible = "qcom,sm8250-dispcc"; 5010 reg = <0 0x0af00000 0 0x10000>; 5011 power-domains = <&rpmhpd RPMHPD_MMCX>; 5012 required-opps = <&rpmhpd_opp_low_svs>; 5013 clocks = <&rpmhcc RPMH_CXO_CLK>, 5014 <&mdss_dsi0_phy 0>, 5015 <&mdss_dsi0_phy 1>, 5016 <&mdss_dsi1_phy 0>, 5017 <&mdss_dsi1_phy 1>, 5018 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5019 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5020 clock-names = "bi_tcxo", 5021 "dsi0_phy_pll_out_byteclk", 5022 "dsi0_phy_pll_out_dsiclk", 5023 "dsi1_phy_pll_out_byteclk", 5024 "dsi1_phy_pll_out_dsiclk", 5025 "dp_phy_pll_link_clk", 5026 "dp_phy_pll_vco_div_clk"; 5027 #clock-cells = <1>; 5028 #reset-cells = <1>; 5029 #power-domain-cells = <1>; 5030 }; 5031 5032 pdc: interrupt-controller@b220000 { 5033 compatible = "qcom,sm8250-pdc", "qcom,pdc"; 5034 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 5035 qcom,pdc-ranges = <0 480 94>, <94 609 31>, 5036 <125 63 1>, <126 716 12>; 5037 #interrupt-cells = <2>; 5038 interrupt-parent = <&intc>; 5039 interrupt-controller; 5040 }; 5041 5042 tsens0: thermal-sensor@c263000 { 5043 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5044 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5045 <0 0x0c222000 0 0x1ff>; /* SROT */ 5046 #qcom,sensors = <16>; 5047 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5049 interrupt-names = "uplow", "critical"; 5050 #thermal-sensor-cells = <1>; 5051 }; 5052 5053 tsens1: thermal-sensor@c265000 { 5054 compatible = "qcom,sm8250-tsens", "qcom,tsens-v2"; 5055 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5056 <0 0x0c223000 0 0x1ff>; /* SROT */ 5057 #qcom,sensors = <9>; 5058 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5060 interrupt-names = "uplow", "critical"; 5061 #thermal-sensor-cells = <1>; 5062 }; 5063 5064 aoss_qmp: power-management@c300000 { 5065 compatible = "qcom,sm8250-aoss-qmp", "qcom,aoss-qmp"; 5066 reg = <0 0x0c300000 0 0x400>; 5067 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5068 IPCC_MPROC_SIGNAL_GLINK_QMP 5069 IRQ_TYPE_EDGE_RISING>; 5070 mboxes = <&ipcc IPCC_CLIENT_AOP 5071 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5072 5073 #clock-cells = <0>; 5074 }; 5075 5076 sram@c3f0000 { 5077 compatible = "qcom,rpmh-stats"; 5078 reg = <0 0x0c3f0000 0 0x400>; 5079 }; 5080 5081 spmi_bus: spmi@c440000 { 5082 compatible = "qcom,spmi-pmic-arb"; 5083 reg = <0x0 0x0c440000 0x0 0x0001100>, 5084 <0x0 0x0c600000 0x0 0x2000000>, 5085 <0x0 0x0e600000 0x0 0x0100000>, 5086 <0x0 0x0e700000 0x0 0x00a0000>, 5087 <0x0 0x0c40a000 0x0 0x0026000>; 5088 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5089 interrupt-names = "periph_irq"; 5090 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5091 qcom,ee = <0>; 5092 qcom,channel = <0>; 5093 #address-cells = <2>; 5094 #size-cells = <0>; 5095 interrupt-controller; 5096 #interrupt-cells = <4>; 5097 }; 5098 5099 tlmm: pinctrl@f100000 { 5100 compatible = "qcom,sm8250-pinctrl"; 5101 reg = <0 0x0f100000 0 0x300000>, 5102 <0 0x0f500000 0 0x300000>, 5103 <0 0x0f900000 0 0x300000>; 5104 reg-names = "west", "south", "north"; 5105 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5106 gpio-controller; 5107 #gpio-cells = <2>; 5108 interrupt-controller; 5109 #interrupt-cells = <2>; 5110 gpio-ranges = <&tlmm 0 0 181>; 5111 wakeup-parent = <&pdc>; 5112 5113 cam2_default: cam2-default-state { 5114 rst-pins { 5115 pins = "gpio78"; 5116 function = "gpio"; 5117 drive-strength = <2>; 5118 bias-disable; 5119 }; 5120 5121 mclk-pins { 5122 pins = "gpio96"; 5123 function = "cam_mclk"; 5124 drive-strength = <16>; 5125 bias-disable; 5126 }; 5127 }; 5128 5129 cam2_suspend: cam2-suspend-state { 5130 rst-pins { 5131 pins = "gpio78"; 5132 function = "gpio"; 5133 drive-strength = <2>; 5134 bias-pull-down; 5135 output-low; 5136 }; 5137 5138 mclk-pins { 5139 pins = "gpio96"; 5140 function = "cam_mclk"; 5141 drive-strength = <2>; 5142 bias-disable; 5143 }; 5144 }; 5145 5146 cci0_default: cci0-default-state { 5147 cci0_i2c0_default: cci0-i2c0-default-pins { 5148 /* SDA, SCL */ 5149 pins = "gpio101", "gpio102"; 5150 function = "cci_i2c"; 5151 5152 bias-pull-up; 5153 drive-strength = <2>; /* 2 mA */ 5154 }; 5155 5156 cci0_i2c1_default: cci0-i2c1-default-pins { 5157 /* SDA, SCL */ 5158 pins = "gpio103", "gpio104"; 5159 function = "cci_i2c"; 5160 5161 bias-pull-up; 5162 drive-strength = <2>; /* 2 mA */ 5163 }; 5164 }; 5165 5166 cci0_sleep: cci0-sleep-state { 5167 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 5168 /* SDA, SCL */ 5169 pins = "gpio101", "gpio102"; 5170 function = "cci_i2c"; 5171 5172 drive-strength = <2>; /* 2 mA */ 5173 bias-pull-down; 5174 }; 5175 5176 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 5177 /* SDA, SCL */ 5178 pins = "gpio103", "gpio104"; 5179 function = "cci_i2c"; 5180 5181 drive-strength = <2>; /* 2 mA */ 5182 bias-pull-down; 5183 }; 5184 }; 5185 5186 cci1_default: cci1-default-state { 5187 cci1_i2c0_default: cci1-i2c0-default-pins { 5188 /* SDA, SCL */ 5189 pins = "gpio105","gpio106"; 5190 function = "cci_i2c"; 5191 5192 bias-pull-up; 5193 drive-strength = <2>; /* 2 mA */ 5194 }; 5195 5196 cci1_i2c1_default: cci1-i2c1-default-pins { 5197 /* SDA, SCL */ 5198 pins = "gpio107","gpio108"; 5199 function = "cci_i2c"; 5200 5201 bias-pull-up; 5202 drive-strength = <2>; /* 2 mA */ 5203 }; 5204 }; 5205 5206 cci1_sleep: cci1-sleep-state { 5207 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 5208 /* SDA, SCL */ 5209 pins = "gpio105","gpio106"; 5210 function = "cci_i2c"; 5211 5212 bias-pull-down; 5213 drive-strength = <2>; /* 2 mA */ 5214 }; 5215 5216 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 5217 /* SDA, SCL */ 5218 pins = "gpio107","gpio108"; 5219 function = "cci_i2c"; 5220 5221 bias-pull-down; 5222 drive-strength = <2>; /* 2 mA */ 5223 }; 5224 }; 5225 5226 pri_mi2s_active: pri-mi2s-active-state { 5227 sclk-pins { 5228 pins = "gpio138"; 5229 function = "mi2s0_sck"; 5230 drive-strength = <8>; 5231 bias-disable; 5232 }; 5233 5234 ws-pins { 5235 pins = "gpio141"; 5236 function = "mi2s0_ws"; 5237 drive-strength = <8>; 5238 output-high; 5239 }; 5240 5241 data0-pins { 5242 pins = "gpio139"; 5243 function = "mi2s0_data0"; 5244 drive-strength = <8>; 5245 bias-disable; 5246 output-high; 5247 }; 5248 5249 data1-pins { 5250 pins = "gpio140"; 5251 function = "mi2s0_data1"; 5252 drive-strength = <8>; 5253 output-high; 5254 }; 5255 }; 5256 5257 qup_i2c0_default: qup-i2c0-default-state { 5258 pins = "gpio28", "gpio29"; 5259 function = "qup0"; 5260 drive-strength = <2>; 5261 bias-disable; 5262 }; 5263 5264 qup_i2c1_default: qup-i2c1-default-state { 5265 pins = "gpio4", "gpio5"; 5266 function = "qup1"; 5267 drive-strength = <2>; 5268 bias-disable; 5269 }; 5270 5271 qup_i2c2_default: qup-i2c2-default-state { 5272 pins = "gpio115", "gpio116"; 5273 function = "qup2"; 5274 drive-strength = <2>; 5275 bias-disable; 5276 }; 5277 5278 qup_i2c3_default: qup-i2c3-default-state { 5279 pins = "gpio119", "gpio120"; 5280 function = "qup3"; 5281 drive-strength = <2>; 5282 bias-disable; 5283 }; 5284 5285 qup_i2c4_default: qup-i2c4-default-state { 5286 pins = "gpio8", "gpio9"; 5287 function = "qup4"; 5288 drive-strength = <2>; 5289 bias-disable; 5290 }; 5291 5292 qup_i2c5_default: qup-i2c5-default-state { 5293 pins = "gpio12", "gpio13"; 5294 function = "qup5"; 5295 drive-strength = <2>; 5296 bias-disable; 5297 }; 5298 5299 qup_i2c6_default: qup-i2c6-default-state { 5300 pins = "gpio16", "gpio17"; 5301 function = "qup6"; 5302 drive-strength = <2>; 5303 bias-disable; 5304 }; 5305 5306 qup_i2c7_default: qup-i2c7-default-state { 5307 pins = "gpio20", "gpio21"; 5308 function = "qup7"; 5309 drive-strength = <2>; 5310 bias-disable; 5311 }; 5312 5313 qup_i2c8_default: qup-i2c8-default-state { 5314 pins = "gpio24", "gpio25"; 5315 function = "qup8"; 5316 drive-strength = <2>; 5317 bias-disable; 5318 }; 5319 5320 qup_i2c9_default: qup-i2c9-default-state { 5321 pins = "gpio125", "gpio126"; 5322 function = "qup9"; 5323 drive-strength = <2>; 5324 bias-disable; 5325 }; 5326 5327 qup_i2c10_default: qup-i2c10-default-state { 5328 pins = "gpio129", "gpio130"; 5329 function = "qup10"; 5330 drive-strength = <2>; 5331 bias-disable; 5332 }; 5333 5334 qup_i2c11_default: qup-i2c11-default-state { 5335 pins = "gpio60", "gpio61"; 5336 function = "qup11"; 5337 drive-strength = <2>; 5338 bias-disable; 5339 }; 5340 5341 qup_i2c12_default: qup-i2c12-default-state { 5342 pins = "gpio32", "gpio33"; 5343 function = "qup12"; 5344 drive-strength = <2>; 5345 bias-disable; 5346 }; 5347 5348 qup_i2c13_default: qup-i2c13-default-state { 5349 pins = "gpio36", "gpio37"; 5350 function = "qup13"; 5351 drive-strength = <2>; 5352 bias-disable; 5353 }; 5354 5355 qup_i2c14_default: qup-i2c14-default-state { 5356 pins = "gpio40", "gpio41"; 5357 function = "qup14"; 5358 drive-strength = <2>; 5359 bias-disable; 5360 }; 5361 5362 qup_i2c15_default: qup-i2c15-default-state { 5363 pins = "gpio44", "gpio45"; 5364 function = "qup15"; 5365 drive-strength = <2>; 5366 bias-disable; 5367 }; 5368 5369 qup_i2c16_default: qup-i2c16-default-state { 5370 pins = "gpio48", "gpio49"; 5371 function = "qup16"; 5372 drive-strength = <2>; 5373 bias-disable; 5374 }; 5375 5376 qup_i2c17_default: qup-i2c17-default-state { 5377 pins = "gpio52", "gpio53"; 5378 function = "qup17"; 5379 drive-strength = <2>; 5380 bias-disable; 5381 }; 5382 5383 qup_i2c18_default: qup-i2c18-default-state { 5384 pins = "gpio56", "gpio57"; 5385 function = "qup18"; 5386 drive-strength = <2>; 5387 bias-disable; 5388 }; 5389 5390 qup_i2c19_default: qup-i2c19-default-state { 5391 pins = "gpio0", "gpio1"; 5392 function = "qup19"; 5393 drive-strength = <2>; 5394 bias-disable; 5395 }; 5396 5397 qup_spi0_cs: qup-spi0-cs-state { 5398 pins = "gpio31"; 5399 function = "qup0"; 5400 }; 5401 5402 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5403 pins = "gpio31"; 5404 function = "gpio"; 5405 }; 5406 5407 qup_spi0_data_clk: qup-spi0-data-clk-state { 5408 pins = "gpio28", "gpio29", 5409 "gpio30"; 5410 function = "qup0"; 5411 }; 5412 5413 qup_spi1_cs: qup-spi1-cs-state { 5414 pins = "gpio7"; 5415 function = "qup1"; 5416 }; 5417 5418 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5419 pins = "gpio7"; 5420 function = "gpio"; 5421 }; 5422 5423 qup_spi1_data_clk: qup-spi1-data-clk-state { 5424 pins = "gpio4", "gpio5", 5425 "gpio6"; 5426 function = "qup1"; 5427 }; 5428 5429 qup_spi2_cs: qup-spi2-cs-state { 5430 pins = "gpio118"; 5431 function = "qup2"; 5432 }; 5433 5434 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5435 pins = "gpio118"; 5436 function = "gpio"; 5437 }; 5438 5439 qup_spi2_data_clk: qup-spi2-data-clk-state { 5440 pins = "gpio115", "gpio116", 5441 "gpio117"; 5442 function = "qup2"; 5443 }; 5444 5445 qup_spi3_cs: qup-spi3-cs-state { 5446 pins = "gpio122"; 5447 function = "qup3"; 5448 }; 5449 5450 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5451 pins = "gpio122"; 5452 function = "gpio"; 5453 }; 5454 5455 qup_spi3_data_clk: qup-spi3-data-clk-state { 5456 pins = "gpio119", "gpio120", 5457 "gpio121"; 5458 function = "qup3"; 5459 }; 5460 5461 qup_spi4_cs: qup-spi4-cs-state { 5462 pins = "gpio11"; 5463 function = "qup4"; 5464 }; 5465 5466 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5467 pins = "gpio11"; 5468 function = "gpio"; 5469 }; 5470 5471 qup_spi4_data_clk: qup-spi4-data-clk-state { 5472 pins = "gpio8", "gpio9", 5473 "gpio10"; 5474 function = "qup4"; 5475 }; 5476 5477 qup_spi5_cs: qup-spi5-cs-state { 5478 pins = "gpio15"; 5479 function = "qup5"; 5480 }; 5481 5482 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5483 pins = "gpio15"; 5484 function = "gpio"; 5485 }; 5486 5487 qup_spi5_data_clk: qup-spi5-data-clk-state { 5488 pins = "gpio12", "gpio13", 5489 "gpio14"; 5490 function = "qup5"; 5491 }; 5492 5493 qup_spi6_cs: qup-spi6-cs-state { 5494 pins = "gpio19"; 5495 function = "qup6"; 5496 }; 5497 5498 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5499 pins = "gpio19"; 5500 function = "gpio"; 5501 }; 5502 5503 qup_spi6_data_clk: qup-spi6-data-clk-state { 5504 pins = "gpio16", "gpio17", 5505 "gpio18"; 5506 function = "qup6"; 5507 }; 5508 5509 qup_spi7_cs: qup-spi7-cs-state { 5510 pins = "gpio23"; 5511 function = "qup7"; 5512 }; 5513 5514 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 5515 pins = "gpio23"; 5516 function = "gpio"; 5517 }; 5518 5519 qup_spi7_data_clk: qup-spi7-data-clk-state { 5520 pins = "gpio20", "gpio21", 5521 "gpio22"; 5522 function = "qup7"; 5523 }; 5524 5525 qup_spi8_cs: qup-spi8-cs-state { 5526 pins = "gpio27"; 5527 function = "qup8"; 5528 }; 5529 5530 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5531 pins = "gpio27"; 5532 function = "gpio"; 5533 }; 5534 5535 qup_spi8_data_clk: qup-spi8-data-clk-state { 5536 pins = "gpio24", "gpio25", 5537 "gpio26"; 5538 function = "qup8"; 5539 }; 5540 5541 qup_spi9_cs: qup-spi9-cs-state { 5542 pins = "gpio128"; 5543 function = "qup9"; 5544 }; 5545 5546 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5547 pins = "gpio128"; 5548 function = "gpio"; 5549 }; 5550 5551 qup_spi9_data_clk: qup-spi9-data-clk-state { 5552 pins = "gpio125", "gpio126", 5553 "gpio127"; 5554 function = "qup9"; 5555 }; 5556 5557 qup_spi10_cs: qup-spi10-cs-state { 5558 pins = "gpio132"; 5559 function = "qup10"; 5560 }; 5561 5562 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5563 pins = "gpio132"; 5564 function = "gpio"; 5565 }; 5566 5567 qup_spi10_data_clk: qup-spi10-data-clk-state { 5568 pins = "gpio129", "gpio130", 5569 "gpio131"; 5570 function = "qup10"; 5571 }; 5572 5573 qup_spi11_cs: qup-spi11-cs-state { 5574 pins = "gpio63"; 5575 function = "qup11"; 5576 }; 5577 5578 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 5579 pins = "gpio63"; 5580 function = "gpio"; 5581 }; 5582 5583 qup_spi11_data_clk: qup-spi11-data-clk-state { 5584 pins = "gpio60", "gpio61", 5585 "gpio62"; 5586 function = "qup11"; 5587 }; 5588 5589 qup_spi12_cs: qup-spi12-cs-state { 5590 pins = "gpio35"; 5591 function = "qup12"; 5592 }; 5593 5594 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5595 pins = "gpio35"; 5596 function = "gpio"; 5597 }; 5598 5599 qup_spi12_data_clk: qup-spi12-data-clk-state { 5600 pins = "gpio32", "gpio33", 5601 "gpio34"; 5602 function = "qup12"; 5603 }; 5604 5605 qup_spi13_cs: qup-spi13-cs-state { 5606 pins = "gpio39"; 5607 function = "qup13"; 5608 }; 5609 5610 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5611 pins = "gpio39"; 5612 function = "gpio"; 5613 }; 5614 5615 qup_spi13_data_clk: qup-spi13-data-clk-state { 5616 pins = "gpio36", "gpio37", 5617 "gpio38"; 5618 function = "qup13"; 5619 }; 5620 5621 qup_spi14_cs: qup-spi14-cs-state { 5622 pins = "gpio43"; 5623 function = "qup14"; 5624 }; 5625 5626 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5627 pins = "gpio43"; 5628 function = "gpio"; 5629 }; 5630 5631 qup_spi14_data_clk: qup-spi14-data-clk-state { 5632 pins = "gpio40", "gpio41", 5633 "gpio42"; 5634 function = "qup14"; 5635 }; 5636 5637 qup_spi15_cs: qup-spi15-cs-state { 5638 pins = "gpio47"; 5639 function = "qup15"; 5640 }; 5641 5642 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5643 pins = "gpio47"; 5644 function = "gpio"; 5645 }; 5646 5647 qup_spi15_data_clk: qup-spi15-data-clk-state { 5648 pins = "gpio44", "gpio45", 5649 "gpio46"; 5650 function = "qup15"; 5651 }; 5652 5653 qup_spi16_cs: qup-spi16-cs-state { 5654 pins = "gpio51"; 5655 function = "qup16"; 5656 }; 5657 5658 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5659 pins = "gpio51"; 5660 function = "gpio"; 5661 }; 5662 5663 qup_spi16_data_clk: qup-spi16-data-clk-state { 5664 pins = "gpio48", "gpio49", 5665 "gpio50"; 5666 function = "qup16"; 5667 }; 5668 5669 qup_spi17_cs: qup-spi17-cs-state { 5670 pins = "gpio55"; 5671 function = "qup17"; 5672 }; 5673 5674 qup_spi17_cs_gpio: qup-spi17-cs-gpio-state { 5675 pins = "gpio55"; 5676 function = "gpio"; 5677 }; 5678 5679 qup_spi17_data_clk: qup-spi17-data-clk-state { 5680 pins = "gpio52", "gpio53", 5681 "gpio54"; 5682 function = "qup17"; 5683 }; 5684 5685 qup_spi18_cs: qup-spi18-cs-state { 5686 pins = "gpio59"; 5687 function = "qup18"; 5688 }; 5689 5690 qup_spi18_cs_gpio: qup-spi18-cs-gpio-state { 5691 pins = "gpio59"; 5692 function = "gpio"; 5693 }; 5694 5695 qup_spi18_data_clk: qup-spi18-data-clk-state { 5696 pins = "gpio56", "gpio57", 5697 "gpio58"; 5698 function = "qup18"; 5699 }; 5700 5701 qup_spi19_cs: qup-spi19-cs-state { 5702 pins = "gpio3"; 5703 function = "qup19"; 5704 }; 5705 5706 qup_spi19_cs_gpio: qup-spi19-cs-gpio-state { 5707 pins = "gpio3"; 5708 function = "gpio"; 5709 }; 5710 5711 qup_spi19_data_clk: qup-spi19-data-clk-state { 5712 pins = "gpio0", "gpio1", 5713 "gpio2"; 5714 function = "qup19"; 5715 }; 5716 5717 qup_uart2_default: qup-uart2-default-state { 5718 pins = "gpio117", "gpio118"; 5719 function = "qup2"; 5720 }; 5721 5722 qup_uart6_default: qup-uart6-default-state { 5723 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 5724 function = "qup6"; 5725 }; 5726 5727 qup_uart12_default: qup-uart12-default-state { 5728 pins = "gpio34", "gpio35"; 5729 function = "qup12"; 5730 }; 5731 5732 qup_uart17_default: qup-uart17-default-state { 5733 pins = "gpio52", "gpio53", "gpio54", "gpio55"; 5734 function = "qup17"; 5735 }; 5736 5737 qup_uart18_default: qup-uart18-default-state { 5738 pins = "gpio58", "gpio59"; 5739 function = "qup18"; 5740 }; 5741 5742 tert_mi2s_active: tert-mi2s-active-state { 5743 sck-pins { 5744 pins = "gpio133"; 5745 function = "mi2s2_sck"; 5746 drive-strength = <8>; 5747 bias-disable; 5748 }; 5749 5750 data0-pins { 5751 pins = "gpio134"; 5752 function = "mi2s2_data0"; 5753 drive-strength = <8>; 5754 bias-disable; 5755 output-high; 5756 }; 5757 5758 ws-pins { 5759 pins = "gpio135"; 5760 function = "mi2s2_ws"; 5761 drive-strength = <8>; 5762 output-high; 5763 }; 5764 }; 5765 5766 sdc2_sleep_state: sdc2-sleep-state { 5767 clk-pins { 5768 pins = "sdc2_clk"; 5769 drive-strength = <2>; 5770 bias-disable; 5771 }; 5772 5773 cmd-pins { 5774 pins = "sdc2_cmd"; 5775 drive-strength = <2>; 5776 bias-pull-up; 5777 }; 5778 5779 data-pins { 5780 pins = "sdc2_data"; 5781 drive-strength = <2>; 5782 bias-pull-up; 5783 }; 5784 }; 5785 5786 pcie0_default_state: pcie0-default-state { 5787 perst-pins { 5788 pins = "gpio79"; 5789 function = "gpio"; 5790 drive-strength = <2>; 5791 bias-pull-down; 5792 }; 5793 5794 clkreq-pins { 5795 pins = "gpio80"; 5796 function = "pci_e0"; 5797 drive-strength = <2>; 5798 bias-pull-up; 5799 }; 5800 5801 wake-pins { 5802 pins = "gpio81"; 5803 function = "gpio"; 5804 drive-strength = <2>; 5805 bias-pull-up; 5806 }; 5807 }; 5808 5809 pcie1_default_state: pcie1-default-state { 5810 perst-pins { 5811 pins = "gpio82"; 5812 function = "gpio"; 5813 drive-strength = <2>; 5814 bias-pull-down; 5815 }; 5816 5817 clkreq-pins { 5818 pins = "gpio83"; 5819 function = "pci_e1"; 5820 drive-strength = <2>; 5821 bias-pull-up; 5822 }; 5823 5824 wake-pins { 5825 pins = "gpio84"; 5826 function = "gpio"; 5827 drive-strength = <2>; 5828 bias-pull-up; 5829 }; 5830 }; 5831 5832 pcie2_default_state: pcie2-default-state { 5833 perst-pins { 5834 pins = "gpio85"; 5835 function = "gpio"; 5836 drive-strength = <2>; 5837 bias-pull-down; 5838 }; 5839 5840 clkreq-pins { 5841 pins = "gpio86"; 5842 function = "pci_e2"; 5843 drive-strength = <2>; 5844 bias-pull-up; 5845 }; 5846 5847 wake-pins { 5848 pins = "gpio87"; 5849 function = "gpio"; 5850 drive-strength = <2>; 5851 bias-pull-up; 5852 }; 5853 }; 5854 }; 5855 5856 apps_smmu: iommu@15000000 { 5857 compatible = "qcom,sm8250-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5858 reg = <0 0x15000000 0 0x100000>; 5859 #iommu-cells = <2>; 5860 #global-interrupts = <2>; 5861 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 5862 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5863 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5864 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5865 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5866 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5867 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5868 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5870 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5871 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5872 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5873 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5874 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5875 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5876 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5877 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5878 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5881 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5882 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5883 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5884 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5885 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5886 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5887 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5888 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5889 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5890 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5891 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5892 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5893 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5894 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5895 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5896 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5897 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5898 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5899 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5900 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5901 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5902 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5903 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5904 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5905 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5906 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5907 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5908 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5909 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5910 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5911 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5912 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5913 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5914 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5915 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5917 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5918 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5919 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5920 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5921 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5922 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5923 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5924 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5925 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5926 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5927 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5928 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5929 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5930 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5931 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5932 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5933 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5936 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5937 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5938 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5939 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5940 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5941 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5942 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5943 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5944 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5945 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5946 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5947 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5948 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5949 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5950 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5951 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5952 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5953 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5954 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5955 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5956 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5957 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5958 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>; 5959 dma-coherent; 5960 }; 5961 5962 adsp: remoteproc@17300000 { 5963 compatible = "qcom,sm8250-adsp-pas"; 5964 reg = <0 0x17300000 0 0x100>; 5965 5966 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 5967 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 5968 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 5969 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 5970 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 5971 interrupt-names = "wdog", "fatal", "ready", 5972 "handover", "stop-ack"; 5973 5974 clocks = <&rpmhcc RPMH_CXO_CLK>; 5975 clock-names = "xo"; 5976 5977 power-domains = <&rpmhpd RPMHPD_LCX>, 5978 <&rpmhpd RPMHPD_LMX>; 5979 power-domain-names = "lcx", "lmx"; 5980 5981 memory-region = <&adsp_mem>; 5982 5983 qcom,qmp = <&aoss_qmp>; 5984 5985 qcom,smem-states = <&smp2p_adsp_out 0>; 5986 qcom,smem-state-names = "stop"; 5987 5988 status = "disabled"; 5989 5990 glink-edge { 5991 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 5992 IPCC_MPROC_SIGNAL_GLINK_QMP 5993 IRQ_TYPE_EDGE_RISING>; 5994 mboxes = <&ipcc IPCC_CLIENT_LPASS 5995 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5996 5997 label = "lpass"; 5998 qcom,remote-pid = <2>; 5999 6000 apr { 6001 compatible = "qcom,apr-v2"; 6002 qcom,glink-channels = "apr_audio_svc"; 6003 qcom,domain = <APR_DOMAIN_ADSP>; 6004 #address-cells = <1>; 6005 #size-cells = <0>; 6006 6007 service@3 { 6008 reg = <APR_SVC_ADSP_CORE>; 6009 compatible = "qcom,q6core"; 6010 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6011 }; 6012 6013 q6afe: service@4 { 6014 compatible = "qcom,q6afe"; 6015 reg = <APR_SVC_AFE>; 6016 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6017 q6afedai: dais { 6018 compatible = "qcom,q6afe-dais"; 6019 #address-cells = <1>; 6020 #size-cells = <0>; 6021 #sound-dai-cells = <1>; 6022 }; 6023 6024 q6afecc: clock-controller { 6025 compatible = "qcom,q6afe-clocks"; 6026 #clock-cells = <2>; 6027 }; 6028 }; 6029 6030 q6asm: service@7 { 6031 compatible = "qcom,q6asm"; 6032 reg = <APR_SVC_ASM>; 6033 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6034 q6asmdai: dais { 6035 compatible = "qcom,q6asm-dais"; 6036 #address-cells = <1>; 6037 #size-cells = <0>; 6038 #sound-dai-cells = <1>; 6039 iommus = <&apps_smmu 0x1801 0x0>; 6040 }; 6041 }; 6042 6043 q6adm: service@8 { 6044 compatible = "qcom,q6adm"; 6045 reg = <APR_SVC_ADM>; 6046 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 6047 q6routing: routing { 6048 compatible = "qcom,q6adm-routing"; 6049 #sound-dai-cells = <0>; 6050 }; 6051 }; 6052 }; 6053 6054 fastrpc { 6055 compatible = "qcom,fastrpc"; 6056 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6057 label = "adsp"; 6058 qcom,non-secure-domain; 6059 #address-cells = <1>; 6060 #size-cells = <0>; 6061 6062 compute-cb@3 { 6063 compatible = "qcom,fastrpc-compute-cb"; 6064 reg = <3>; 6065 iommus = <&apps_smmu 0x1803 0x0>; 6066 }; 6067 6068 compute-cb@4 { 6069 compatible = "qcom,fastrpc-compute-cb"; 6070 reg = <4>; 6071 iommus = <&apps_smmu 0x1804 0x0>; 6072 }; 6073 6074 compute-cb@5 { 6075 compatible = "qcom,fastrpc-compute-cb"; 6076 reg = <5>; 6077 iommus = <&apps_smmu 0x1805 0x0>; 6078 }; 6079 }; 6080 }; 6081 }; 6082 6083 intc: interrupt-controller@17a00000 { 6084 compatible = "arm,gic-v3"; 6085 #interrupt-cells = <3>; 6086 interrupt-controller; 6087 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 6088 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 6089 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 6090 }; 6091 6092 watchdog@17c10000 { 6093 compatible = "qcom,apss-wdt-sm8250", "qcom,kpss-wdt"; 6094 reg = <0 0x17c10000 0 0x1000>; 6095 clocks = <&sleep_clk>; 6096 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6097 }; 6098 6099 timer@17c20000 { 6100 #address-cells = <1>; 6101 #size-cells = <1>; 6102 ranges = <0 0 0 0x20000000>; 6103 compatible = "arm,armv7-timer-mem"; 6104 reg = <0x0 0x17c20000 0x0 0x1000>; 6105 clock-frequency = <19200000>; 6106 6107 frame@17c21000 { 6108 frame-number = <0>; 6109 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6110 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6111 reg = <0x17c21000 0x1000>, 6112 <0x17c22000 0x1000>; 6113 }; 6114 6115 frame@17c23000 { 6116 frame-number = <1>; 6117 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6118 reg = <0x17c23000 0x1000>; 6119 status = "disabled"; 6120 }; 6121 6122 frame@17c25000 { 6123 frame-number = <2>; 6124 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6125 reg = <0x17c25000 0x1000>; 6126 status = "disabled"; 6127 }; 6128 6129 frame@17c27000 { 6130 frame-number = <3>; 6131 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6132 reg = <0x17c27000 0x1000>; 6133 status = "disabled"; 6134 }; 6135 6136 frame@17c29000 { 6137 frame-number = <4>; 6138 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6139 reg = <0x17c29000 0x1000>; 6140 status = "disabled"; 6141 }; 6142 6143 frame@17c2b000 { 6144 frame-number = <5>; 6145 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6146 reg = <0x17c2b000 0x1000>; 6147 status = "disabled"; 6148 }; 6149 6150 frame@17c2d000 { 6151 frame-number = <6>; 6152 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6153 reg = <0x17c2d000 0x1000>; 6154 status = "disabled"; 6155 }; 6156 }; 6157 6158 apps_rsc: rsc@18200000 { 6159 label = "apps_rsc"; 6160 compatible = "qcom,rpmh-rsc"; 6161 reg = <0x0 0x18200000 0x0 0x10000>, 6162 <0x0 0x18210000 0x0 0x10000>, 6163 <0x0 0x18220000 0x0 0x10000>; 6164 reg-names = "drv-0", "drv-1", "drv-2"; 6165 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6166 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6167 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6168 qcom,tcs-offset = <0xd00>; 6169 qcom,drv-id = <2>; 6170 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 6171 <WAKE_TCS 3>, <CONTROL_TCS 1>; 6172 power-domains = <&cluster_pd>; 6173 6174 rpmhcc: clock-controller { 6175 compatible = "qcom,sm8250-rpmh-clk"; 6176 #clock-cells = <1>; 6177 clock-names = "xo"; 6178 clocks = <&xo_board>; 6179 }; 6180 6181 rpmhpd: power-controller { 6182 compatible = "qcom,sm8250-rpmhpd"; 6183 #power-domain-cells = <1>; 6184 operating-points-v2 = <&rpmhpd_opp_table>; 6185 6186 rpmhpd_opp_table: opp-table { 6187 compatible = "operating-points-v2"; 6188 6189 rpmhpd_opp_ret: opp1 { 6190 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6191 }; 6192 6193 rpmhpd_opp_min_svs: opp2 { 6194 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 6195 }; 6196 6197 rpmhpd_opp_low_svs: opp3 { 6198 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6199 }; 6200 6201 rpmhpd_opp_svs: opp4 { 6202 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6203 }; 6204 6205 rpmhpd_opp_svs_l1: opp5 { 6206 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6207 }; 6208 6209 rpmhpd_opp_nom: opp6 { 6210 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 6211 }; 6212 6213 rpmhpd_opp_nom_l1: opp7 { 6214 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 6215 }; 6216 6217 rpmhpd_opp_nom_l2: opp8 { 6218 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 6219 }; 6220 6221 rpmhpd_opp_turbo: opp9 { 6222 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6223 }; 6224 6225 rpmhpd_opp_turbo_l1: opp10 { 6226 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6227 }; 6228 }; 6229 }; 6230 6231 apps_bcm_voter: bcm-voter { 6232 compatible = "qcom,bcm-voter"; 6233 }; 6234 }; 6235 6236 epss_l3: interconnect@18590000 { 6237 compatible = "qcom,sm8250-epss-l3", "qcom,epss-l3"; 6238 reg = <0 0x18590000 0 0x1000>; 6239 6240 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6241 clock-names = "xo", "alternate"; 6242 6243 #interconnect-cells = <1>; 6244 }; 6245 6246 cpufreq_hw: cpufreq@18591000 { 6247 compatible = "qcom,sm8250-cpufreq-epss", "qcom,cpufreq-epss"; 6248 reg = <0 0x18591000 0 0x1000>, 6249 <0 0x18592000 0 0x1000>, 6250 <0 0x18593000 0 0x1000>; 6251 reg-names = "freq-domain0", "freq-domain1", 6252 "freq-domain2"; 6253 6254 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 6255 clock-names = "xo", "alternate"; 6256 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 6257 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6258 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 6259 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; 6260 #freq-domain-cells = <1>; 6261 #clock-cells = <1>; 6262 }; 6263 }; 6264 6265 sound: sound { 6266 }; 6267 6268 timer { 6269 compatible = "arm,armv8-timer"; 6270 interrupts = <GIC_PPI 13 6271 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6272 <GIC_PPI 14 6273 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6274 <GIC_PPI 11 6275 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6276 <GIC_PPI 10 6277 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6278 }; 6279 6280 thermal-zones { 6281 cpu0-thermal { 6282 polling-delay-passive = <250>; 6283 6284 thermal-sensors = <&tsens0 1>; 6285 6286 trips { 6287 cpu0_alert0: trip-point0 { 6288 temperature = <90000>; 6289 hysteresis = <2000>; 6290 type = "passive"; 6291 }; 6292 6293 cpu0_alert1: trip-point1 { 6294 temperature = <95000>; 6295 hysteresis = <2000>; 6296 type = "passive"; 6297 }; 6298 6299 cpu0_crit: cpu-crit { 6300 temperature = <110000>; 6301 hysteresis = <1000>; 6302 type = "critical"; 6303 }; 6304 }; 6305 6306 cooling-maps { 6307 map0 { 6308 trip = <&cpu0_alert0>; 6309 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6310 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6311 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6312 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6313 }; 6314 map1 { 6315 trip = <&cpu0_alert1>; 6316 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6317 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6318 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6319 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6320 }; 6321 }; 6322 }; 6323 6324 cpu1-thermal { 6325 polling-delay-passive = <250>; 6326 6327 thermal-sensors = <&tsens0 2>; 6328 6329 trips { 6330 cpu1_alert0: trip-point0 { 6331 temperature = <90000>; 6332 hysteresis = <2000>; 6333 type = "passive"; 6334 }; 6335 6336 cpu1_alert1: trip-point1 { 6337 temperature = <95000>; 6338 hysteresis = <2000>; 6339 type = "passive"; 6340 }; 6341 6342 cpu1_crit: cpu-crit { 6343 temperature = <110000>; 6344 hysteresis = <1000>; 6345 type = "critical"; 6346 }; 6347 }; 6348 6349 cooling-maps { 6350 map0 { 6351 trip = <&cpu1_alert0>; 6352 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6353 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6354 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6355 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6356 }; 6357 map1 { 6358 trip = <&cpu1_alert1>; 6359 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6360 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6361 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6362 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6363 }; 6364 }; 6365 }; 6366 6367 cpu2-thermal { 6368 polling-delay-passive = <250>; 6369 6370 thermal-sensors = <&tsens0 3>; 6371 6372 trips { 6373 cpu2_alert0: trip-point0 { 6374 temperature = <90000>; 6375 hysteresis = <2000>; 6376 type = "passive"; 6377 }; 6378 6379 cpu2_alert1: trip-point1 { 6380 temperature = <95000>; 6381 hysteresis = <2000>; 6382 type = "passive"; 6383 }; 6384 6385 cpu2_crit: cpu-crit { 6386 temperature = <110000>; 6387 hysteresis = <1000>; 6388 type = "critical"; 6389 }; 6390 }; 6391 6392 cooling-maps { 6393 map0 { 6394 trip = <&cpu2_alert0>; 6395 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6396 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6397 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6398 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6399 }; 6400 map1 { 6401 trip = <&cpu2_alert1>; 6402 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6403 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6404 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6405 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6406 }; 6407 }; 6408 }; 6409 6410 cpu3-thermal { 6411 polling-delay-passive = <250>; 6412 6413 thermal-sensors = <&tsens0 4>; 6414 6415 trips { 6416 cpu3_alert0: trip-point0 { 6417 temperature = <90000>; 6418 hysteresis = <2000>; 6419 type = "passive"; 6420 }; 6421 6422 cpu3_alert1: trip-point1 { 6423 temperature = <95000>; 6424 hysteresis = <2000>; 6425 type = "passive"; 6426 }; 6427 6428 cpu3_crit: cpu-crit { 6429 temperature = <110000>; 6430 hysteresis = <1000>; 6431 type = "critical"; 6432 }; 6433 }; 6434 6435 cooling-maps { 6436 map0 { 6437 trip = <&cpu3_alert0>; 6438 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6439 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6440 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6441 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6442 }; 6443 map1 { 6444 trip = <&cpu3_alert1>; 6445 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6446 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6447 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6448 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6449 }; 6450 }; 6451 }; 6452 6453 cpu4-top-thermal { 6454 polling-delay-passive = <250>; 6455 6456 thermal-sensors = <&tsens0 7>; 6457 6458 trips { 6459 cpu4_top_alert0: trip-point0 { 6460 temperature = <90000>; 6461 hysteresis = <2000>; 6462 type = "passive"; 6463 }; 6464 6465 cpu4_top_alert1: trip-point1 { 6466 temperature = <95000>; 6467 hysteresis = <2000>; 6468 type = "passive"; 6469 }; 6470 6471 cpu4_top_crit: cpu-crit { 6472 temperature = <110000>; 6473 hysteresis = <1000>; 6474 type = "critical"; 6475 }; 6476 }; 6477 6478 cooling-maps { 6479 map0 { 6480 trip = <&cpu4_top_alert0>; 6481 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6482 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6483 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6484 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6485 }; 6486 map1 { 6487 trip = <&cpu4_top_alert1>; 6488 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6489 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6490 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6491 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6492 }; 6493 }; 6494 }; 6495 6496 cpu5-top-thermal { 6497 polling-delay-passive = <250>; 6498 6499 thermal-sensors = <&tsens0 8>; 6500 6501 trips { 6502 cpu5_top_alert0: trip-point0 { 6503 temperature = <90000>; 6504 hysteresis = <2000>; 6505 type = "passive"; 6506 }; 6507 6508 cpu5_top_alert1: trip-point1 { 6509 temperature = <95000>; 6510 hysteresis = <2000>; 6511 type = "passive"; 6512 }; 6513 6514 cpu5_top_crit: cpu-crit { 6515 temperature = <110000>; 6516 hysteresis = <1000>; 6517 type = "critical"; 6518 }; 6519 }; 6520 6521 cooling-maps { 6522 map0 { 6523 trip = <&cpu5_top_alert0>; 6524 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6525 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6526 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6527 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6528 }; 6529 map1 { 6530 trip = <&cpu5_top_alert1>; 6531 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6532 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6533 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6534 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6535 }; 6536 }; 6537 }; 6538 6539 cpu6-top-thermal { 6540 polling-delay-passive = <250>; 6541 6542 thermal-sensors = <&tsens0 9>; 6543 6544 trips { 6545 cpu6_top_alert0: trip-point0 { 6546 temperature = <90000>; 6547 hysteresis = <2000>; 6548 type = "passive"; 6549 }; 6550 6551 cpu6_top_alert1: trip-point1 { 6552 temperature = <95000>; 6553 hysteresis = <2000>; 6554 type = "passive"; 6555 }; 6556 6557 cpu6_top_crit: cpu-crit { 6558 temperature = <110000>; 6559 hysteresis = <1000>; 6560 type = "critical"; 6561 }; 6562 }; 6563 6564 cooling-maps { 6565 map0 { 6566 trip = <&cpu6_top_alert0>; 6567 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6568 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6569 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6570 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6571 }; 6572 map1 { 6573 trip = <&cpu6_top_alert1>; 6574 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6575 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6576 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6577 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6578 }; 6579 }; 6580 }; 6581 6582 cpu7-top-thermal { 6583 polling-delay-passive = <250>; 6584 6585 thermal-sensors = <&tsens0 10>; 6586 6587 trips { 6588 cpu7_top_alert0: trip-point0 { 6589 temperature = <90000>; 6590 hysteresis = <2000>; 6591 type = "passive"; 6592 }; 6593 6594 cpu7_top_alert1: trip-point1 { 6595 temperature = <95000>; 6596 hysteresis = <2000>; 6597 type = "passive"; 6598 }; 6599 6600 cpu7_top_crit: cpu-crit { 6601 temperature = <110000>; 6602 hysteresis = <1000>; 6603 type = "critical"; 6604 }; 6605 }; 6606 6607 cooling-maps { 6608 map0 { 6609 trip = <&cpu7_top_alert0>; 6610 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6611 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6612 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6613 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6614 }; 6615 map1 { 6616 trip = <&cpu7_top_alert1>; 6617 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6618 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6619 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6620 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6621 }; 6622 }; 6623 }; 6624 6625 cpu4-bottom-thermal { 6626 polling-delay-passive = <250>; 6627 6628 thermal-sensors = <&tsens0 11>; 6629 6630 trips { 6631 cpu4_bottom_alert0: trip-point0 { 6632 temperature = <90000>; 6633 hysteresis = <2000>; 6634 type = "passive"; 6635 }; 6636 6637 cpu4_bottom_alert1: trip-point1 { 6638 temperature = <95000>; 6639 hysteresis = <2000>; 6640 type = "passive"; 6641 }; 6642 6643 cpu4_bottom_crit: cpu-crit { 6644 temperature = <110000>; 6645 hysteresis = <1000>; 6646 type = "critical"; 6647 }; 6648 }; 6649 6650 cooling-maps { 6651 map0 { 6652 trip = <&cpu4_bottom_alert0>; 6653 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6654 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6655 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6656 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6657 }; 6658 map1 { 6659 trip = <&cpu4_bottom_alert1>; 6660 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6661 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6662 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6663 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6664 }; 6665 }; 6666 }; 6667 6668 cpu5-bottom-thermal { 6669 polling-delay-passive = <250>; 6670 6671 thermal-sensors = <&tsens0 12>; 6672 6673 trips { 6674 cpu5_bottom_alert0: trip-point0 { 6675 temperature = <90000>; 6676 hysteresis = <2000>; 6677 type = "passive"; 6678 }; 6679 6680 cpu5_bottom_alert1: trip-point1 { 6681 temperature = <95000>; 6682 hysteresis = <2000>; 6683 type = "passive"; 6684 }; 6685 6686 cpu5_bottom_crit: cpu-crit { 6687 temperature = <110000>; 6688 hysteresis = <1000>; 6689 type = "critical"; 6690 }; 6691 }; 6692 6693 cooling-maps { 6694 map0 { 6695 trip = <&cpu5_bottom_alert0>; 6696 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6697 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6698 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6699 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6700 }; 6701 map1 { 6702 trip = <&cpu5_bottom_alert1>; 6703 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6704 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6705 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6706 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6707 }; 6708 }; 6709 }; 6710 6711 cpu6-bottom-thermal { 6712 polling-delay-passive = <250>; 6713 6714 thermal-sensors = <&tsens0 13>; 6715 6716 trips { 6717 cpu6_bottom_alert0: trip-point0 { 6718 temperature = <90000>; 6719 hysteresis = <2000>; 6720 type = "passive"; 6721 }; 6722 6723 cpu6_bottom_alert1: trip-point1 { 6724 temperature = <95000>; 6725 hysteresis = <2000>; 6726 type = "passive"; 6727 }; 6728 6729 cpu6_bottom_crit: cpu-crit { 6730 temperature = <110000>; 6731 hysteresis = <1000>; 6732 type = "critical"; 6733 }; 6734 }; 6735 6736 cooling-maps { 6737 map0 { 6738 trip = <&cpu6_bottom_alert0>; 6739 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6740 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6741 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6742 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6743 }; 6744 map1 { 6745 trip = <&cpu6_bottom_alert1>; 6746 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6747 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6748 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6749 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6750 }; 6751 }; 6752 }; 6753 6754 cpu7-bottom-thermal { 6755 polling-delay-passive = <250>; 6756 6757 thermal-sensors = <&tsens0 14>; 6758 6759 trips { 6760 cpu7_bottom_alert0: trip-point0 { 6761 temperature = <90000>; 6762 hysteresis = <2000>; 6763 type = "passive"; 6764 }; 6765 6766 cpu7_bottom_alert1: trip-point1 { 6767 temperature = <95000>; 6768 hysteresis = <2000>; 6769 type = "passive"; 6770 }; 6771 6772 cpu7_bottom_crit: cpu-crit { 6773 temperature = <110000>; 6774 hysteresis = <1000>; 6775 type = "critical"; 6776 }; 6777 }; 6778 6779 cooling-maps { 6780 map0 { 6781 trip = <&cpu7_bottom_alert0>; 6782 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6783 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6784 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6785 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6786 }; 6787 map1 { 6788 trip = <&cpu7_bottom_alert1>; 6789 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6790 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6791 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 6792 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6793 }; 6794 }; 6795 }; 6796 6797 aoss0-thermal { 6798 polling-delay-passive = <250>; 6799 6800 thermal-sensors = <&tsens0 0>; 6801 6802 trips { 6803 aoss0_alert0: trip-point0 { 6804 temperature = <90000>; 6805 hysteresis = <2000>; 6806 type = "hot"; 6807 }; 6808 }; 6809 }; 6810 6811 cluster0-thermal { 6812 polling-delay-passive = <250>; 6813 6814 thermal-sensors = <&tsens0 5>; 6815 6816 trips { 6817 cluster0_alert0: trip-point0 { 6818 temperature = <90000>; 6819 hysteresis = <2000>; 6820 type = "hot"; 6821 }; 6822 cluster0_crit: cluster0-crit { 6823 temperature = <110000>; 6824 hysteresis = <2000>; 6825 type = "critical"; 6826 }; 6827 }; 6828 }; 6829 6830 cluster1-thermal { 6831 polling-delay-passive = <250>; 6832 6833 thermal-sensors = <&tsens0 6>; 6834 6835 trips { 6836 cluster1_alert0: trip-point0 { 6837 temperature = <90000>; 6838 hysteresis = <2000>; 6839 type = "hot"; 6840 }; 6841 cluster1_crit: cluster1-crit { 6842 temperature = <110000>; 6843 hysteresis = <2000>; 6844 type = "critical"; 6845 }; 6846 }; 6847 }; 6848 6849 gpu-top-thermal { 6850 polling-delay-passive = <250>; 6851 6852 thermal-sensors = <&tsens0 15>; 6853 6854 cooling-maps { 6855 map0 { 6856 trip = <&gpu_top_alert0>; 6857 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6858 }; 6859 }; 6860 6861 trips { 6862 gpu_top_alert0: trip-point0 { 6863 temperature = <85000>; 6864 hysteresis = <1000>; 6865 type = "passive"; 6866 }; 6867 6868 trip-point1 { 6869 temperature = <90000>; 6870 hysteresis = <1000>; 6871 type = "hot"; 6872 }; 6873 6874 trip-point2 { 6875 temperature = <110000>; 6876 hysteresis = <1000>; 6877 type = "critical"; 6878 }; 6879 }; 6880 }; 6881 6882 aoss1-thermal { 6883 polling-delay-passive = <250>; 6884 6885 thermal-sensors = <&tsens1 0>; 6886 6887 trips { 6888 aoss1_alert0: trip-point0 { 6889 temperature = <90000>; 6890 hysteresis = <2000>; 6891 type = "hot"; 6892 }; 6893 }; 6894 }; 6895 6896 wlan-thermal { 6897 polling-delay-passive = <250>; 6898 6899 thermal-sensors = <&tsens1 1>; 6900 6901 trips { 6902 wlan_alert0: trip-point0 { 6903 temperature = <90000>; 6904 hysteresis = <2000>; 6905 type = "hot"; 6906 }; 6907 }; 6908 }; 6909 6910 video-thermal { 6911 polling-delay-passive = <250>; 6912 6913 thermal-sensors = <&tsens1 2>; 6914 6915 trips { 6916 video_alert0: trip-point0 { 6917 temperature = <90000>; 6918 hysteresis = <2000>; 6919 type = "hot"; 6920 }; 6921 }; 6922 }; 6923 6924 mem-thermal { 6925 polling-delay-passive = <250>; 6926 6927 thermal-sensors = <&tsens1 3>; 6928 6929 trips { 6930 mem_alert0: trip-point0 { 6931 temperature = <90000>; 6932 hysteresis = <2000>; 6933 type = "hot"; 6934 }; 6935 }; 6936 }; 6937 6938 q6-hvx-thermal { 6939 polling-delay-passive = <250>; 6940 6941 thermal-sensors = <&tsens1 4>; 6942 6943 trips { 6944 q6_hvx_alert0: trip-point0 { 6945 temperature = <90000>; 6946 hysteresis = <2000>; 6947 type = "hot"; 6948 }; 6949 }; 6950 }; 6951 6952 camera-thermal { 6953 polling-delay-passive = <250>; 6954 6955 thermal-sensors = <&tsens1 5>; 6956 6957 trips { 6958 camera_alert0: trip-point0 { 6959 temperature = <90000>; 6960 hysteresis = <2000>; 6961 type = "hot"; 6962 }; 6963 }; 6964 }; 6965 6966 compute-thermal { 6967 polling-delay-passive = <250>; 6968 6969 thermal-sensors = <&tsens1 6>; 6970 6971 trips { 6972 compute_alert0: trip-point0 { 6973 temperature = <90000>; 6974 hysteresis = <2000>; 6975 type = "hot"; 6976 }; 6977 }; 6978 }; 6979 6980 npu-thermal { 6981 polling-delay-passive = <250>; 6982 6983 thermal-sensors = <&tsens1 7>; 6984 6985 trips { 6986 npu_alert0: trip-point0 { 6987 temperature = <90000>; 6988 hysteresis = <2000>; 6989 type = "hot"; 6990 }; 6991 }; 6992 }; 6993 6994 gpu-bottom-thermal { 6995 polling-delay-passive = <250>; 6996 6997 thermal-sensors = <&tsens1 8>; 6998 6999 cooling-maps { 7000 map0 { 7001 trip = <&gpu_bottom_alert0>; 7002 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7003 }; 7004 }; 7005 7006 trips { 7007 gpu_bottom_alert0: trip-point0 { 7008 temperature = <85000>; 7009 hysteresis = <1000>; 7010 type = "passive"; 7011 }; 7012 7013 trip-point1 { 7014 temperature = <90000>; 7015 hysteresis = <1000>; 7016 type = "hot"; 7017 }; 7018 7019 trip-point2 { 7020 temperature = <110000>; 7021 hysteresis = <1000>; 7022 type = "critical"; 7023 }; 7024 }; 7025 }; 7026 }; 7027}; 7028