1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2021, Iskren Chernev <[email protected]>
4 */
5
6#include <dt-bindings/clock/qcom,gcc-sm6115.h>
7#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
8#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
9#include <dt-bindings/clock/qcom,rpmcc.h>
10#include <dt-bindings/dma/qcom-gpi.h>
11#include <dt-bindings/firmware/qcom,scm.h>
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interconnect/qcom,rpm-icc.h>
14#include <dt-bindings/interconnect/qcom,sm6115.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/power/qcom-rpmpd.h>
17#include <dt-bindings/soc/qcom,apr.h>
18#include <dt-bindings/sound/qcom,q6asm.h>
19#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
20#include <dt-bindings/thermal/thermal.h>
21
22/ {
23	interrupt-parent = <&intc>;
24
25	#address-cells = <2>;
26	#size-cells = <2>;
27
28	chosen { };
29
30	clocks {
31		xo_board: xo-board {
32			compatible = "fixed-clock";
33			#clock-cells = <0>;
34		};
35
36		sleep_clk: sleep-clk {
37			compatible = "fixed-clock";
38			#clock-cells = <0>;
39		};
40	};
41
42	cpus {
43		#address-cells = <2>;
44		#size-cells = <0>;
45
46		cpu0: cpu@0 {
47			device_type = "cpu";
48			compatible = "qcom,kryo260";
49			reg = <0x0 0x0>;
50			clocks = <&cpufreq_hw 0>;
51			capacity-dmips-mhz = <1024>;
52			dynamic-power-coefficient = <100>;
53			enable-method = "psci";
54			next-level-cache = <&l2_0>;
55			qcom,freq-domain = <&cpufreq_hw 0>;
56			power-domains = <&cpu_pd0>;
57			power-domain-names = "psci";
58			l2_0: l2-cache {
59				compatible = "cache";
60				cache-level = <2>;
61				cache-unified;
62			};
63		};
64
65		cpu1: cpu@1 {
66			device_type = "cpu";
67			compatible = "qcom,kryo260";
68			reg = <0x0 0x1>;
69			clocks = <&cpufreq_hw 0>;
70			capacity-dmips-mhz = <1024>;
71			dynamic-power-coefficient = <100>;
72			enable-method = "psci";
73			next-level-cache = <&l2_0>;
74			qcom,freq-domain = <&cpufreq_hw 0>;
75			power-domains = <&cpu_pd1>;
76			power-domain-names = "psci";
77		};
78
79		cpu2: cpu@2 {
80			device_type = "cpu";
81			compatible = "qcom,kryo260";
82			reg = <0x0 0x2>;
83			clocks = <&cpufreq_hw 0>;
84			capacity-dmips-mhz = <1024>;
85			dynamic-power-coefficient = <100>;
86			enable-method = "psci";
87			next-level-cache = <&l2_0>;
88			qcom,freq-domain = <&cpufreq_hw 0>;
89			power-domains = <&cpu_pd2>;
90			power-domain-names = "psci";
91		};
92
93		cpu3: cpu@3 {
94			device_type = "cpu";
95			compatible = "qcom,kryo260";
96			reg = <0x0 0x3>;
97			clocks = <&cpufreq_hw 0>;
98			capacity-dmips-mhz = <1024>;
99			dynamic-power-coefficient = <100>;
100			enable-method = "psci";
101			next-level-cache = <&l2_0>;
102			qcom,freq-domain = <&cpufreq_hw 0>;
103			power-domains = <&cpu_pd3>;
104			power-domain-names = "psci";
105		};
106
107		cpu4: cpu@100 {
108			device_type = "cpu";
109			compatible = "qcom,kryo260";
110			reg = <0x0 0x100>;
111			clocks = <&cpufreq_hw 1>;
112			enable-method = "psci";
113			capacity-dmips-mhz = <1638>;
114			dynamic-power-coefficient = <282>;
115			next-level-cache = <&l2_1>;
116			qcom,freq-domain = <&cpufreq_hw 1>;
117			power-domains = <&cpu_pd4>;
118			power-domain-names = "psci";
119			l2_1: l2-cache {
120				compatible = "cache";
121				cache-level = <2>;
122				cache-unified;
123			};
124		};
125
126		cpu5: cpu@101 {
127			device_type = "cpu";
128			compatible = "qcom,kryo260";
129			reg = <0x0 0x101>;
130			clocks = <&cpufreq_hw 1>;
131			capacity-dmips-mhz = <1638>;
132			dynamic-power-coefficient = <282>;
133			enable-method = "psci";
134			next-level-cache = <&l2_1>;
135			qcom,freq-domain = <&cpufreq_hw 1>;
136			power-domains = <&cpu_pd5>;
137			power-domain-names = "psci";
138		};
139
140		cpu6: cpu@102 {
141			device_type = "cpu";
142			compatible = "qcom,kryo260";
143			reg = <0x0 0x102>;
144			clocks = <&cpufreq_hw 1>;
145			capacity-dmips-mhz = <1638>;
146			dynamic-power-coefficient = <282>;
147			enable-method = "psci";
148			next-level-cache = <&l2_1>;
149			qcom,freq-domain = <&cpufreq_hw 1>;
150			power-domains = <&cpu_pd6>;
151			power-domain-names = "psci";
152		};
153
154		cpu7: cpu@103 {
155			device_type = "cpu";
156			compatible = "qcom,kryo260";
157			reg = <0x0 0x103>;
158			clocks = <&cpufreq_hw 1>;
159			capacity-dmips-mhz = <1638>;
160			dynamic-power-coefficient = <282>;
161			enable-method = "psci";
162			next-level-cache = <&l2_1>;
163			qcom,freq-domain = <&cpufreq_hw 1>;
164			power-domains = <&cpu_pd7>;
165			power-domain-names = "psci";
166		};
167
168		cpu-map {
169			cluster0 {
170				core0 {
171					cpu = <&cpu0>;
172				};
173
174				core1 {
175					cpu = <&cpu1>;
176				};
177
178				core2 {
179					cpu = <&cpu2>;
180				};
181
182				core3 {
183					cpu = <&cpu3>;
184				};
185			};
186
187			cluster1 {
188				core0 {
189					cpu = <&cpu4>;
190				};
191
192				core1 {
193					cpu = <&cpu5>;
194				};
195
196				core2 {
197					cpu = <&cpu6>;
198				};
199
200				core3 {
201					cpu = <&cpu7>;
202				};
203			};
204		};
205
206		idle-states {
207			entry-method = "psci";
208
209			little_cpu_sleep_0: cpu-sleep-0-0 {
210				compatible = "arm,idle-state";
211				idle-state-name = "silver-rail-power-collapse";
212				arm,psci-suspend-param = <0x40000003>;
213				entry-latency-us = <290>;
214				exit-latency-us = <376>;
215				min-residency-us = <1182>;
216				local-timer-stop;
217			};
218
219			big_cpu_sleep_0: cpu-sleep-1-0 {
220				compatible = "arm,idle-state";
221				idle-state-name = "gold-rail-power-collapse";
222				arm,psci-suspend-param = <0x40000003>;
223				entry-latency-us = <297>;
224				exit-latency-us = <324>;
225				min-residency-us = <1110>;
226				local-timer-stop;
227			};
228		};
229
230		domain-idle-states {
231			cluster_0_sleep_0: cluster-sleep-0-0 {
232				/* GDHS */
233				compatible = "domain-idle-state";
234				arm,psci-suspend-param = <0x40000022>;
235				entry-latency-us = <360>;
236				exit-latency-us = <421>;
237				min-residency-us = <782>;
238			};
239
240			cluster_0_sleep_1: cluster-sleep-0-1 {
241				/* Power Collapse */
242				compatible = "domain-idle-state";
243				arm,psci-suspend-param = <0x41000044>;
244				entry-latency-us = <800>;
245				exit-latency-us = <2118>;
246				min-residency-us = <7376>;
247			};
248
249			cluster_1_sleep_0: cluster-sleep-1-0 {
250				/* GDHS */
251				compatible = "domain-idle-state";
252				arm,psci-suspend-param = <0x40000042>;
253				entry-latency-us = <314>;
254				exit-latency-us = <345>;
255				min-residency-us = <660>;
256			};
257
258			cluster_1_sleep_1: cluster-sleep-1-1 {
259				/* Power Collapse */
260				compatible = "domain-idle-state";
261				arm,psci-suspend-param = <0x41000044>;
262				entry-latency-us = <640>;
263				exit-latency-us = <1654>;
264				min-residency-us = <8094>;
265			};
266		};
267	};
268
269	firmware {
270		scm: scm {
271			compatible = "qcom,scm-sm6115", "qcom,scm";
272			#reset-cells = <1>;
273			interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
274					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
275		};
276	};
277
278	memory@80000000 {
279		device_type = "memory";
280		/* We expect the bootloader to fill in the size */
281		reg = <0 0x80000000 0 0>;
282	};
283
284	qup_opp_table: opp-table-qup {
285		compatible = "operating-points-v2";
286
287		opp-75000000 {
288			opp-hz = /bits/ 64 <75000000>;
289			required-opps = <&rpmpd_opp_low_svs>;
290		};
291
292		opp-100000000 {
293			opp-hz = /bits/ 64 <100000000>;
294			required-opps = <&rpmpd_opp_svs>;
295		};
296
297		opp-128000000 {
298			opp-hz = /bits/ 64 <128000000>;
299			required-opps = <&rpmpd_opp_nom>;
300		};
301	};
302
303	pmu {
304		compatible = "arm,armv8-pmuv3";
305		interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
306	};
307
308	psci {
309		compatible = "arm,psci-1.0";
310		method = "smc";
311
312		cpu_pd0: power-domain-cpu0 {
313			#power-domain-cells = <0>;
314			power-domains = <&cluster_0_pd>;
315			domain-idle-states = <&little_cpu_sleep_0>;
316		};
317
318		cpu_pd1: power-domain-cpu1 {
319			#power-domain-cells = <0>;
320			power-domains = <&cluster_0_pd>;
321			domain-idle-states = <&little_cpu_sleep_0>;
322		};
323
324		cpu_pd2: power-domain-cpu2 {
325			#power-domain-cells = <0>;
326			power-domains = <&cluster_0_pd>;
327			domain-idle-states = <&little_cpu_sleep_0>;
328		};
329
330		cpu_pd3: power-domain-cpu3 {
331			#power-domain-cells = <0>;
332			power-domains = <&cluster_0_pd>;
333			domain-idle-states = <&little_cpu_sleep_0>;
334		};
335
336		cpu_pd4: power-domain-cpu4 {
337			#power-domain-cells = <0>;
338			power-domains = <&cluster_1_pd>;
339			domain-idle-states = <&big_cpu_sleep_0>;
340		};
341
342		cpu_pd5: power-domain-cpu5 {
343			#power-domain-cells = <0>;
344			power-domains = <&cluster_1_pd>;
345			domain-idle-states = <&big_cpu_sleep_0>;
346		};
347
348		cpu_pd6: power-domain-cpu6 {
349			#power-domain-cells = <0>;
350			power-domains = <&cluster_1_pd>;
351			domain-idle-states = <&big_cpu_sleep_0>;
352		};
353
354		cpu_pd7: power-domain-cpu7 {
355			#power-domain-cells = <0>;
356			power-domains = <&cluster_1_pd>;
357			domain-idle-states = <&big_cpu_sleep_0>;
358		};
359
360		cluster_0_pd: power-domain-cpu-cluster0 {
361			#power-domain-cells = <0>;
362			domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>;
363		};
364
365		cluster_1_pd: power-domain-cpu-cluster1 {
366			#power-domain-cells = <0>;
367			domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>;
368		};
369	};
370
371	rpm: remoteproc {
372		compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
373
374		glink-edge {
375			compatible = "qcom,glink-rpm";
376
377			interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
378			qcom,rpm-msg-ram = <&rpm_msg_ram>;
379			mboxes = <&apcs_glb 0>;
380
381			rpm_requests: rpm-requests {
382				compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm";
383				qcom,glink-channels = "rpm_requests";
384
385				rpmcc: clock-controller {
386					compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
387					clocks = <&xo_board>;
388					clock-names = "xo";
389					#clock-cells = <1>;
390				};
391
392				rpmpd: power-controller {
393					compatible = "qcom,sm6115-rpmpd";
394					#power-domain-cells = <1>;
395					operating-points-v2 = <&rpmpd_opp_table>;
396
397					rpmpd_opp_table: opp-table {
398						compatible = "operating-points-v2";
399
400						rpmpd_opp_min_svs: opp1 {
401							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
402						};
403
404						rpmpd_opp_low_svs: opp2 {
405							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
406						};
407
408						rpmpd_opp_svs: opp3 {
409							opp-level = <RPM_SMD_LEVEL_SVS>;
410						};
411
412						rpmpd_opp_svs_plus: opp4 {
413							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
414						};
415
416						rpmpd_opp_nom: opp5 {
417							opp-level = <RPM_SMD_LEVEL_NOM>;
418						};
419
420						rpmpd_opp_nom_plus: opp6 {
421							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
422						};
423
424						rpmpd_opp_turbo: opp7 {
425							opp-level = <RPM_SMD_LEVEL_TURBO>;
426						};
427
428						rpmpd_opp_turbo_plus: opp8 {
429							opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
430						};
431					};
432				};
433			};
434		};
435	};
436
437	reserved_memory: reserved-memory {
438		#address-cells = <2>;
439		#size-cells = <2>;
440		ranges;
441
442		hyp_mem: memory@45700000 {
443			reg = <0x0 0x45700000 0x0 0x600000>;
444			no-map;
445		};
446
447		xbl_aop_mem: memory@45e00000 {
448			reg = <0x0 0x45e00000 0x0 0x140000>;
449			no-map;
450		};
451
452		sec_apps_mem: memory@45fff000 {
453			reg = <0x0 0x45fff000 0x0 0x1000>;
454			no-map;
455		};
456
457		smem_mem: memory@46000000 {
458			compatible = "qcom,smem";
459			reg = <0x0 0x46000000 0x0 0x200000>;
460			no-map;
461
462			hwlocks = <&tcsr_mutex 3>;
463			qcom,rpm-msg-ram = <&rpm_msg_ram>;
464		};
465
466		cdsp_sec_mem: memory@46200000 {
467			reg = <0x0 0x46200000 0x0 0x1e00000>;
468			no-map;
469		};
470
471		pil_modem_mem: memory@4ab00000 {
472			reg = <0x0 0x4ab00000 0x0 0x6900000>;
473			no-map;
474		};
475
476		pil_video_mem: memory@51400000 {
477			reg = <0x0 0x51400000 0x0 0x500000>;
478			no-map;
479		};
480
481		wlan_msa_mem: memory@51900000 {
482			reg = <0x0 0x51900000 0x0 0x100000>;
483			no-map;
484		};
485
486		pil_cdsp_mem: memory@51a00000 {
487			reg = <0x0 0x51a00000 0x0 0x1e00000>;
488			no-map;
489		};
490
491		pil_adsp_mem: memory@53800000 {
492			reg = <0x0 0x53800000 0x0 0x2800000>;
493			no-map;
494		};
495
496		pil_ipa_fw_mem: memory@56100000 {
497			reg = <0x0 0x56100000 0x0 0x10000>;
498			no-map;
499		};
500
501		pil_ipa_gsi_mem: memory@56110000 {
502			reg = <0x0 0x56110000 0x0 0x5000>;
503			no-map;
504		};
505
506		pil_gpu_mem: memory@56115000 {
507			reg = <0x0 0x56115000 0x0 0x2000>;
508			no-map;
509		};
510
511		cont_splash_memory: memory@5c000000 {
512			reg = <0x0 0x5c000000 0x0 0x00f00000>;
513			no-map;
514		};
515
516		dfps_data_memory: memory@5cf00000 {
517			reg = <0x0 0x5cf00000 0x0 0x0100000>;
518			no-map;
519		};
520
521		removed_mem: memory@60000000 {
522			reg = <0x0 0x60000000 0x0 0x3900000>;
523			no-map;
524		};
525
526		rmtfs_mem: memory@89b01000 {
527			compatible = "qcom,rmtfs-mem";
528			reg = <0x0 0x89b01000 0x0 0x200000>;
529			no-map;
530
531			qcom,client-id = <1>;
532			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
533		};
534	};
535
536	smp2p-adsp {
537		compatible = "qcom,smp2p";
538		qcom,smem = <443>, <429>;
539
540		interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
541
542		mboxes = <&apcs_glb 10>;
543
544		qcom,local-pid = <0>;
545		qcom,remote-pid = <2>;
546
547		adsp_smp2p_out: master-kernel {
548			qcom,entry-name = "master-kernel";
549			#qcom,smem-state-cells = <1>;
550		};
551
552		adsp_smp2p_in: slave-kernel {
553			qcom,entry-name = "slave-kernel";
554
555			interrupt-controller;
556			#interrupt-cells = <2>;
557		};
558	};
559
560	smp2p-cdsp {
561		compatible = "qcom,smp2p";
562		qcom,smem = <94>, <432>;
563
564		interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
565
566		mboxes = <&apcs_glb 30>;
567
568		qcom,local-pid = <0>;
569		qcom,remote-pid = <5>;
570
571		cdsp_smp2p_out: master-kernel {
572			qcom,entry-name = "master-kernel";
573			#qcom,smem-state-cells = <1>;
574		};
575
576		cdsp_smp2p_in: slave-kernel {
577			qcom,entry-name = "slave-kernel";
578
579			interrupt-controller;
580			#interrupt-cells = <2>;
581		};
582	};
583
584	smp2p-mpss {
585		compatible = "qcom,smp2p";
586		qcom,smem = <435>, <428>;
587
588		interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
589
590		mboxes = <&apcs_glb 14>;
591
592		qcom,local-pid = <0>;
593		qcom,remote-pid = <1>;
594
595		modem_smp2p_out: master-kernel {
596			qcom,entry-name = "master-kernel";
597			#qcom,smem-state-cells = <1>;
598		};
599
600		modem_smp2p_in: slave-kernel {
601			qcom,entry-name = "slave-kernel";
602
603			interrupt-controller;
604			#interrupt-cells = <2>;
605		};
606	};
607
608	soc: soc@0 {
609		compatible = "simple-bus";
610		#address-cells = <2>;
611		#size-cells = <2>;
612		ranges = <0 0 0 0 0x10 0>;
613		dma-ranges = <0 0 0 0 0x10 0>;
614
615		tcsr_mutex: hwlock@340000 {
616			compatible = "qcom,tcsr-mutex";
617			reg = <0x0 0x00340000 0x0 0x20000>;
618			#hwlock-cells = <1>;
619		};
620
621		tcsr_regs: syscon@3c0000 {
622			compatible = "qcom,sm6115-tcsr", "syscon";
623			reg = <0x0 0x003c0000 0x0 0x40000>;
624		};
625
626		tlmm: pinctrl@500000 {
627			compatible = "qcom,sm6115-tlmm";
628			reg = <0x0 0x00500000 0x0 0x400000>,
629			      <0x0 0x00900000 0x0 0x400000>,
630			      <0x0 0x00d00000 0x0 0x400000>;
631			reg-names = "west", "south", "east";
632			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
633			gpio-controller;
634			gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
635			#gpio-cells = <2>;
636			interrupt-controller;
637			#interrupt-cells = <2>;
638
639			qup_i2c0_default: qup-i2c0-default-state {
640				pins = "gpio0", "gpio1";
641				function = "qup0";
642				drive-strength = <2>;
643				bias-pull-up;
644			};
645
646			qup_i2c1_default: qup-i2c1-default-state {
647				pins = "gpio4", "gpio5";
648				function = "qup1";
649				drive-strength = <2>;
650				bias-pull-up;
651			};
652
653			qup_i2c2_default: qup-i2c2-default-state {
654				pins = "gpio6", "gpio7";
655				function = "qup2";
656				drive-strength = <2>;
657				bias-pull-up;
658			};
659
660			qup_i2c3_default: qup-i2c3-default-state {
661				pins = "gpio8", "gpio9";
662				function = "qup3";
663				drive-strength = <2>;
664				bias-pull-up;
665			};
666
667			qup_i2c4_default: qup-i2c4-default-state {
668				pins = "gpio12", "gpio13";
669				function = "qup4";
670				drive-strength = <2>;
671				bias-pull-up;
672			};
673
674			qup_i2c5_default: qup-i2c5-default-state {
675				pins = "gpio14", "gpio15";
676				function = "qup5";
677				drive-strength = <2>;
678				bias-pull-up;
679			};
680
681			qup_spi0_default: qup-spi0-default-state {
682				pins = "gpio0", "gpio1","gpio2", "gpio3";
683				function = "qup0";
684				drive-strength = <2>;
685				bias-pull-up;
686			};
687
688			qup_spi1_default: qup-spi1-default-state {
689				pins = "gpio4", "gpio5", "gpio69", "gpio70";
690				function = "qup1";
691				drive-strength = <2>;
692				bias-pull-up;
693			};
694
695			qup_spi2_default: qup-spi2-default-state {
696				pins = "gpio6", "gpio7", "gpio71", "gpio80";
697				function = "qup2";
698				drive-strength = <2>;
699				bias-pull-up;
700			};
701
702			qup_spi3_default: qup-spi3-default-state {
703				pins = "gpio8", "gpio9", "gpio10", "gpio11";
704				function = "qup3";
705				drive-strength = <2>;
706				bias-pull-up;
707			};
708
709			qup_spi4_default: qup-spi4-default-state {
710				pins = "gpio12", "gpio13", "gpio96", "gpio97";
711				function = "qup4";
712				drive-strength = <2>;
713				bias-pull-up;
714			};
715
716			qup_spi5_default: qup-spi5-default-state {
717				pins = "gpio14", "gpio15", "gpio16", "gpio17";
718				function = "qup5";
719				drive-strength = <2>;
720				bias-pull-up;
721			};
722
723			sdc1_state_on: sdc1-on-state {
724				clk-pins {
725					pins = "sdc1_clk";
726					bias-disable;
727					drive-strength = <16>;
728				};
729
730				cmd-pins {
731					pins = "sdc1_cmd";
732					bias-pull-up;
733					drive-strength = <10>;
734				};
735
736				data-pins {
737					pins = "sdc1_data";
738					bias-pull-up;
739					drive-strength = <10>;
740				};
741
742				rclk-pins {
743					pins = "sdc1_rclk";
744					bias-pull-down;
745				};
746			};
747
748			sdc1_state_off: sdc1-off-state {
749				clk-pins {
750					pins = "sdc1_clk";
751					bias-disable;
752					drive-strength = <2>;
753				};
754
755				cmd-pins {
756					pins = "sdc1_cmd";
757					bias-pull-up;
758					drive-strength = <2>;
759				};
760
761				data-pins {
762					pins = "sdc1_data";
763					bias-pull-up;
764					drive-strength = <2>;
765				};
766
767				rclk-pins {
768					pins = "sdc1_rclk";
769					bias-pull-down;
770				};
771			};
772
773			sdc2_state_on: sdc2-on-state {
774				clk-pins {
775					pins = "sdc2_clk";
776					bias-disable;
777					drive-strength = <16>;
778				};
779
780				cmd-pins {
781					pins = "sdc2_cmd";
782					bias-pull-up;
783					drive-strength = <10>;
784				};
785
786				data-pins {
787					pins = "sdc2_data";
788					bias-pull-up;
789					drive-strength = <10>;
790				};
791			};
792
793			sdc2_state_off: sdc2-off-state {
794				clk-pins {
795					pins = "sdc2_clk";
796					bias-disable;
797					drive-strength = <2>;
798				};
799
800				cmd-pins {
801					pins = "sdc2_cmd";
802					bias-pull-up;
803					drive-strength = <2>;
804				};
805
806				data-pins {
807					pins = "sdc2_data";
808					bias-pull-up;
809					drive-strength = <2>;
810				};
811			};
812		};
813
814		lpass_tlmm: pinctrl@a7c0000 {
815			compatible = "qcom,sm6115-lpass-lpi-pinctrl";
816			reg = <0x0 0x0a7c0000 0x0 0x20000>,
817			      <0x0 0x0a950000 0x0 0x10000>;
818
819			clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
820			clock-names = "audio";
821
822			gpio-controller;
823			#gpio-cells = <2>;
824			gpio-ranges = <&lpass_tlmm 0 0 19>;
825
826		};
827
828		gcc: clock-controller@1400000 {
829			compatible = "qcom,gcc-sm6115";
830			reg = <0x0 0x01400000 0x0 0x1f0000>;
831			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
832			clock-names = "bi_tcxo", "sleep_clk";
833			#clock-cells = <1>;
834			#reset-cells = <1>;
835			#power-domain-cells = <1>;
836		};
837
838		usb_hsphy: phy@1613000 {
839			compatible = "qcom,sm6115-qusb2-phy";
840			reg = <0x0 0x01613000 0x0 0x180>;
841			#phy-cells = <0>;
842
843			clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
844			clock-names = "cfg_ahb", "ref";
845
846			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
847			nvmem-cells = <&qusb2_hstx_trim>;
848
849			status = "disabled";
850		};
851
852		cryptobam: dma-controller@1b04000 {
853			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
854			reg = <0x0 0x01b04000 0x0 0x24000>;
855			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
856			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
857			clock-names = "bam_clk";
858			#dma-cells = <1>;
859			qcom,ee = <0>;
860			qcom,controlled-remotely;
861			iommus = <&apps_smmu 0x92 0>,
862				 <&apps_smmu 0x94 0x11>,
863				 <&apps_smmu 0x96 0x11>,
864				 <&apps_smmu 0x98 0x1>,
865				 <&apps_smmu 0x9F 0>;
866		};
867
868		crypto: crypto@1b3a000 {
869			compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
870			reg = <0x0 0x01b3a000 0x0 0x6000>;
871			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
872			clock-names = "core";
873
874			dmas = <&cryptobam 6>, <&cryptobam 7>;
875			dma-names = "rx", "tx";
876			iommus = <&apps_smmu 0x92 0>,
877				 <&apps_smmu 0x94 0x11>,
878				 <&apps_smmu 0x96 0x11>,
879				 <&apps_smmu 0x98 0x1>,
880				 <&apps_smmu 0x9F 0>;
881		};
882
883		usb_qmpphy: phy@1615000 {
884			compatible = "qcom,sm6115-qmp-usb3-phy";
885			reg = <0x0 0x01615000 0x0 0x1000>;
886
887			clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
888				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
889				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
890				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
891			clock-names = "cfg_ahb",
892				      "ref",
893				      "com_aux",
894				      "pipe";
895
896			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
897				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
898			reset-names = "phy", "phy_phy";
899
900			#clock-cells = <0>;
901			clock-output-names = "usb3_phy_pipe_clk_src";
902
903			#phy-cells = <0>;
904			orientation-switch;
905
906			qcom,tcsr-reg = <&tcsr_regs 0xb244>;
907
908			status = "disabled";
909
910			ports {
911				#address-cells = <1>;
912				#size-cells = <0>;
913
914				port@0 {
915					reg = <0>;
916
917					usb_qmpphy_out: endpoint {
918					};
919				};
920
921				port@1 {
922					reg = <1>;
923
924					usb_qmpphy_usb_ss_in: endpoint {
925						remote-endpoint = <&usb_dwc3_ss>;
926					};
927				};
928			};
929		};
930
931		system_noc: interconnect@1880000 {
932			compatible = "qcom,sm6115-snoc";
933			reg = <0x0 0x01880000 0x0 0x5f080>;
934			clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
935				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
936				 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
937				 <&rpmcc RPM_SMD_IPA_CLK>;
938			clock-names = "cpu_axi",
939				      "ufs_axi",
940				      "usb_axi",
941				      "ipa";
942			#interconnect-cells = <2>;
943
944			clk_virt: interconnect-clk {
945				compatible = "qcom,sm6115-clk-virt";
946				#interconnect-cells = <2>;
947			};
948
949			mmrt_virt: interconnect-mmrt {
950				compatible = "qcom,sm6115-mmrt-virt";
951				#interconnect-cells = <2>;
952			};
953
954			mmnrt_virt: interconnect-mmnrt {
955				compatible = "qcom,sm6115-mmnrt-virt";
956				#interconnect-cells = <2>;
957			};
958		};
959
960		config_noc: interconnect@1900000 {
961			compatible = "qcom,sm6115-cnoc";
962			reg = <0x0 0x01900000 0x0 0x6200>;
963			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
964			clock-names = "usb_axi";
965			#interconnect-cells = <2>;
966		};
967
968		qfprom@1b40000 {
969			compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
970			reg = <0x0 0x01b40000 0x0 0x7000>;
971			#address-cells = <1>;
972			#size-cells = <1>;
973
974			qusb2_hstx_trim: hstx-trim@25b {
975				reg = <0x25b 0x1>;
976				bits = <1 4>;
977			};
978
979			gpu_speed_bin: gpu-speed-bin@6006 {
980				reg = <0x6006 0x2>;
981				bits = <5 8>;
982			};
983		};
984
985		rng: rng@1b53000 {
986			compatible = "qcom,prng-ee";
987			reg = <0x0 0x01b53000 0x0 0x1000>;
988			clocks = <&gcc GCC_PRNG_AHB_CLK>;
989			clock-names = "core";
990		};
991
992		pmu@1b8e300 {
993			compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
994			reg = <0x0 0x01b8e300 0x0 0x600>;
995			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
996
997			operating-points-v2 = <&cpu_bwmon_opp_table>;
998			interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
999					 &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
1000
1001			cpu_bwmon_opp_table: opp-table {
1002				compatible = "operating-points-v2";
1003
1004				opp-0 {
1005					opp-peak-kBps = <(200 * 4 * 1000)>;
1006				};
1007
1008				opp-1 {
1009					opp-peak-kBps = <(300 * 4 * 1000)>;
1010				};
1011
1012				opp-2 {
1013					opp-peak-kBps = <(451 * 4 * 1000)>;
1014				};
1015
1016				opp-3 {
1017					opp-peak-kBps = <(547 * 4 * 1000)>;
1018				};
1019
1020				opp-4 {
1021					opp-peak-kBps = <(681 * 4 * 1000)>;
1022				};
1023
1024				opp-5 {
1025					opp-peak-kBps = <(768 * 4 * 1000)>;
1026				};
1027
1028				opp-6 {
1029					opp-peak-kBps = <(1017 * 4 * 1000)>;
1030				};
1031
1032				opp-7 {
1033					opp-peak-kBps = <(1353 * 4 * 1000)>;
1034				};
1035
1036				opp-8 {
1037					opp-peak-kBps = <(1555 * 4 * 1000)>;
1038				};
1039
1040				opp-9 {
1041					opp-peak-kBps = <(1804 * 4 * 1000)>;
1042				};
1043			};
1044		};
1045
1046		spmi_bus: spmi@1c40000 {
1047			compatible = "qcom,spmi-pmic-arb";
1048			reg = <0x0 0x01c40000 0x0 0x1100>,
1049			      <0x0 0x01e00000 0x0 0x2000000>,
1050			      <0x0 0x03e00000 0x0 0x100000>,
1051			      <0x0 0x03f00000 0x0 0xa0000>,
1052			      <0x0 0x01c0a000 0x0 0x26000>;
1053			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1054			interrupt-names = "periph_irq";
1055			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1056			qcom,ee = <0>;
1057			qcom,channel = <0>;
1058			#address-cells = <2>;
1059			#size-cells = <0>;
1060			interrupt-controller;
1061			#interrupt-cells = <4>;
1062		};
1063
1064		tsens0: thermal-sensor@4411000 {
1065			compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1066			reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
1067			      <0x0 0x04410000 0x0 0x8>; /* SROT */
1068			#qcom,sensors = <16>;
1069			interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1070				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1071			interrupt-names = "uplow", "critical";
1072			#thermal-sensor-cells = <1>;
1073		};
1074
1075		bimc: interconnect@4480000 {
1076			compatible = "qcom,sm6115-bimc";
1077			reg = <0x0 0x04480000 0x0 0x80000>;
1078			#interconnect-cells = <2>;
1079		};
1080
1081		rpm_msg_ram: sram@45f0000 {
1082			compatible = "qcom,rpm-msg-ram";
1083			reg = <0x0 0x045f0000 0x0 0x7000>;
1084		};
1085
1086		sram@4690000 {
1087			compatible = "qcom,rpm-stats";
1088			reg = <0x0 0x04690000 0x0 0x10000>;
1089		};
1090
1091		sdhc_1: mmc@4744000 {
1092			compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1093			reg = <0x0 0x04744000 0x0 0x1000>,
1094			      <0x0 0x04745000 0x0 0x1000>,
1095			      <0x0 0x04748000 0x0 0x8000>;
1096			reg-names = "hc", "cqhci", "ice";
1097
1098			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
1099				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1100			interrupt-names = "hc_irq", "pwr_irq";
1101
1102			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1103				 <&gcc GCC_SDCC1_APPS_CLK>,
1104				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
1105				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1106			clock-names = "iface", "core", "xo", "ice";
1107
1108			resets = <&gcc GCC_SDCC1_BCR>;
1109
1110			power-domains = <&rpmpd SM6115_VDDCX>;
1111			operating-points-v2 = <&sdhc1_opp_table>;
1112			iommus = <&apps_smmu 0x00c0 0x0>;
1113			interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
1114					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1115					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1116					 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
1117			interconnect-names = "sdhc-ddr",
1118					     "cpu-sdhc";
1119
1120			bus-width = <8>;
1121			status = "disabled";
1122
1123			sdhc1_opp_table: opp-table {
1124				compatible = "operating-points-v2";
1125
1126				opp-100000000 {
1127					opp-hz = /bits/ 64 <100000000>;
1128					required-opps = <&rpmpd_opp_low_svs>;
1129					opp-peak-kBps = <250000 133320>;
1130					opp-avg-kBps = <102400 65000>;
1131				};
1132
1133				opp-192000000 {
1134					opp-hz = /bits/ 64 <192000000>;
1135					required-opps = <&rpmpd_opp_low_svs>;
1136					opp-peak-kBps = <800000 300000>;
1137					opp-avg-kBps = <204800 200000>;
1138				};
1139
1140				opp-384000000 {
1141					opp-hz = /bits/ 64 <384000000>;
1142					required-opps = <&rpmpd_opp_svs_plus>;
1143					opp-peak-kBps = <800000 300000>;
1144					opp-avg-kBps = <204800 200000>;
1145				};
1146			};
1147		};
1148
1149		sdhc_2: mmc@4784000 {
1150			compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1151			reg = <0x0 0x04784000 0x0 0x1000>;
1152			reg-names = "hc";
1153
1154			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1155				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1156			interrupt-names = "hc_irq", "pwr_irq";
1157
1158			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1159				 <&gcc GCC_SDCC2_APPS_CLK>,
1160				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1161			clock-names = "iface", "core", "xo";
1162
1163			power-domains = <&rpmpd SM6115_VDDCX>;
1164			operating-points-v2 = <&sdhc2_opp_table>;
1165			iommus = <&apps_smmu 0x00a0 0x0>;
1166			resets = <&gcc GCC_SDCC2_BCR>;
1167			interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
1168					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1169					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1170					 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
1171			interconnect-names = "sdhc-ddr",
1172					     "cpu-sdhc";
1173
1174			bus-width = <4>;
1175			qcom,dll-config = <0x0007642c>;
1176			qcom,ddr-config = <0x80040868>;
1177			status = "disabled";
1178
1179			sdhc2_opp_table: opp-table {
1180				compatible = "operating-points-v2";
1181
1182				opp-100000000 {
1183					opp-hz = /bits/ 64 <100000000>;
1184					required-opps = <&rpmpd_opp_low_svs>;
1185					opp-peak-kBps = <250000 133320>;
1186					opp-avg-kBps = <261438 150000>;
1187				};
1188
1189				opp-202000000 {
1190					opp-hz = /bits/ 64 <202000000>;
1191					required-opps = <&rpmpd_opp_nom>;
1192					opp-peak-kBps = <800000 300000>;
1193					opp-avg-kBps = <261438 300000>;
1194				};
1195			};
1196		};
1197
1198		ufs_mem_hc: ufshc@4804000 {
1199			compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1200			reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1201			reg-names = "std", "ice";
1202			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1203			phys = <&ufs_mem_phy>;
1204			phy-names = "ufsphy";
1205			lanes-per-direction = <1>;
1206			#reset-cells = <1>;
1207			resets = <&gcc GCC_UFS_PHY_BCR>;
1208			reset-names = "rst";
1209
1210			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1211			iommus = <&apps_smmu 0x100 0>;
1212
1213			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1214				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
1215				 <&gcc GCC_UFS_PHY_AHB_CLK>,
1216				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1217				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
1218				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1219				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1220				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1221			clock-names = "core_clk",
1222				      "bus_aggr_clk",
1223				      "iface_clk",
1224				      "core_clk_unipro",
1225				      "ref_clk",
1226				      "tx_lane0_sync_clk",
1227				      "rx_lane0_sync_clk",
1228				      "ice_core_clk";
1229
1230			freq-table-hz = <50000000 200000000>,
1231					<0 0>,
1232					<0 0>,
1233					<37500000 150000000>,
1234					<0 0>,
1235					<0 0>,
1236					<0 0>,
1237					<75000000 300000000>;
1238
1239			status = "disabled";
1240		};
1241
1242		ufs_mem_phy: phy@4807000 {
1243			compatible = "qcom,sm6115-qmp-ufs-phy";
1244			reg = <0x0 0x04807000 0x0 0x1000>;
1245
1246			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1247				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1248				 <&gcc GCC_UFS_CLKREF_CLK>;
1249			clock-names = "ref",
1250				      "ref_aux",
1251				      "qref";
1252
1253			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1254
1255			resets = <&ufs_mem_hc 0>;
1256			reset-names = "ufsphy";
1257
1258			#phy-cells = <0>;
1259
1260			status = "disabled";
1261		};
1262
1263		gpi_dma0: dma-controller@4a00000 {
1264			compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1265			reg = <0x0 0x04a00000 0x0 0x60000>;
1266			interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1267				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1268				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1269				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1270				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1271				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1272				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1273				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1274				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1275				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1276			dma-channels = <10>;
1277			dma-channel-mask = <0xf>;
1278			iommus = <&apps_smmu 0xf6 0x0>;
1279			#dma-cells = <3>;
1280			status = "disabled";
1281		};
1282
1283		qupv3_id_0: geniqup@4ac0000 {
1284			compatible = "qcom,geni-se-qup";
1285			reg = <0x0 0x04ac0000 0x0 0x2000>;
1286			clock-names = "m-ahb", "s-ahb";
1287			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1288				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1289			#address-cells = <2>;
1290			#size-cells = <2>;
1291			iommus = <&apps_smmu 0xe3 0x0>;
1292			ranges;
1293			status = "disabled";
1294
1295			i2c0: i2c@4a80000 {
1296				compatible = "qcom,geni-i2c";
1297				reg = <0x0 0x04a80000 0x0 0x4000>;
1298				clock-names = "se";
1299				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1300				pinctrl-names = "default";
1301				pinctrl-0 = <&qup_i2c0_default>;
1302				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1303				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1304				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1305				dma-names = "tx", "rx";
1306				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1307						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1308						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1309						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1310						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1311						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1312				interconnect-names = "qup-core",
1313						     "qup-config",
1314						     "qup-memory";
1315				#address-cells = <1>;
1316				#size-cells = <0>;
1317				status = "disabled";
1318			};
1319
1320			spi0: spi@4a80000 {
1321				compatible = "qcom,geni-spi";
1322				reg = <0x0 0x04a80000 0x0 0x4000>;
1323				clock-names = "se";
1324				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1325				pinctrl-names = "default";
1326				pinctrl-0 = <&qup_spi0_default>;
1327				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1328				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1329				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1330				dma-names = "tx", "rx";
1331				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1332						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1333						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1334						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1335						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1336						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1337				interconnect-names = "qup-core",
1338						     "qup-config",
1339						     "qup-memory";
1340				#address-cells = <1>;
1341				#size-cells = <0>;
1342				status = "disabled";
1343			};
1344
1345			i2c1: i2c@4a84000 {
1346				compatible = "qcom,geni-i2c";
1347				reg = <0x0 0x04a84000 0x0 0x4000>;
1348				clock-names = "se";
1349				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1350				pinctrl-names = "default";
1351				pinctrl-0 = <&qup_i2c1_default>;
1352				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1353				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1354				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1355				dma-names = "tx", "rx";
1356				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1357						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1358						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1359						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1360						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1361						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1362				interconnect-names = "qup-core",
1363						     "qup-config",
1364						     "qup-memory";
1365				#address-cells = <1>;
1366				#size-cells = <0>;
1367				status = "disabled";
1368			};
1369
1370			spi1: spi@4a84000 {
1371				compatible = "qcom,geni-spi";
1372				reg = <0x0 0x04a84000 0x0 0x4000>;
1373				clock-names = "se";
1374				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1375				pinctrl-names = "default";
1376				pinctrl-0 = <&qup_spi1_default>;
1377				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1378				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1379				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1380				dma-names = "tx", "rx";
1381				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1382						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1383						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1384						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1385						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1386						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1387				interconnect-names = "qup-core",
1388						     "qup-config",
1389						     "qup-memory";
1390				#address-cells = <1>;
1391				#size-cells = <0>;
1392				status = "disabled";
1393			};
1394
1395			i2c2: i2c@4a88000 {
1396				compatible = "qcom,geni-i2c";
1397				reg = <0x0 0x04a88000 0x0 0x4000>;
1398				clock-names = "se";
1399				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1400				pinctrl-names = "default";
1401				pinctrl-0 = <&qup_i2c2_default>;
1402				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1403				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1404				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1405				dma-names = "tx", "rx";
1406				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1407						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1408						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1409						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1410						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1411						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1412				interconnect-names = "qup-core",
1413						     "qup-config",
1414						     "qup-memory";
1415				#address-cells = <1>;
1416				#size-cells = <0>;
1417				status = "disabled";
1418			};
1419
1420			spi2: spi@4a88000 {
1421				compatible = "qcom,geni-spi";
1422				reg = <0x0 0x04a88000 0x0 0x4000>;
1423				clock-names = "se";
1424				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1425				pinctrl-names = "default";
1426				pinctrl-0 = <&qup_spi2_default>;
1427				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1428				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1429				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1430				dma-names = "tx", "rx";
1431				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1432						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1433						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1434						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1435						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1436						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1437				interconnect-names = "qup-core",
1438						     "qup-config",
1439						     "qup-memory";
1440				#address-cells = <1>;
1441				#size-cells = <0>;
1442				status = "disabled";
1443			};
1444
1445			i2c3: i2c@4a8c000 {
1446				compatible = "qcom,geni-i2c";
1447				reg = <0x0 0x04a8c000 0x0 0x4000>;
1448				clock-names = "se";
1449				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1450				pinctrl-names = "default";
1451				pinctrl-0 = <&qup_i2c3_default>;
1452				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1453				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1454				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1455				dma-names = "tx", "rx";
1456				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1457						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1458						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1459						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1460						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1461						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1462				interconnect-names = "qup-core",
1463						     "qup-config",
1464						     "qup-memory";
1465				#address-cells = <1>;
1466				#size-cells = <0>;
1467				status = "disabled";
1468			};
1469
1470			spi3: spi@4a8c000 {
1471				compatible = "qcom,geni-spi";
1472				reg = <0x0 0x04a8c000 0x0 0x4000>;
1473				clock-names = "se";
1474				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1475				pinctrl-names = "default";
1476				pinctrl-0 = <&qup_spi3_default>;
1477				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1478				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1479				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1480				dma-names = "tx", "rx";
1481				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1482						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1483						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1484						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1485						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1486						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1487				interconnect-names = "qup-core",
1488						     "qup-config",
1489						     "qup-memory";
1490				#address-cells = <1>;
1491				#size-cells = <0>;
1492				status = "disabled";
1493			};
1494
1495			uart3: serial@4a8c000 {
1496				compatible = "qcom,geni-uart";
1497				reg = <0x0 0x04a8c000 0x0 0x4000>;
1498				interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1499				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1500				clock-names = "se";
1501				power-domains = <&rpmpd SM6115_VDDCX>;
1502				operating-points-v2 = <&qup_opp_table>;
1503				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1504						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1505						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1506						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1507				interconnect-names = "qup-core",
1508						     "qup-config";
1509				status = "disabled";
1510			};
1511
1512			i2c4: i2c@4a90000 {
1513				compatible = "qcom,geni-i2c";
1514				reg = <0x0 0x04a90000 0x0 0x4000>;
1515				clock-names = "se";
1516				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1517				pinctrl-names = "default";
1518				pinctrl-0 = <&qup_i2c4_default>;
1519				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1520				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1521				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1522				dma-names = "tx", "rx";
1523				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1524						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1525						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1526						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1527						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1528						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1529				interconnect-names = "qup-core",
1530						     "qup-config",
1531						     "qup-memory";
1532				#address-cells = <1>;
1533				#size-cells = <0>;
1534				status = "disabled";
1535			};
1536
1537			spi4: spi@4a90000 {
1538				compatible = "qcom,geni-spi";
1539				reg = <0x0 0x04a90000 0x0 0x4000>;
1540				clock-names = "se";
1541				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1542				pinctrl-names = "default";
1543				pinctrl-0 = <&qup_spi4_default>;
1544				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1545				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1546				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1547				dma-names = "tx", "rx";
1548				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1549						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1550						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1551						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1552						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1553						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1554				interconnect-names = "qup-core",
1555						     "qup-config",
1556						     "qup-memory";
1557				#address-cells = <1>;
1558				#size-cells = <0>;
1559				status = "disabled";
1560			};
1561
1562			uart4: serial@4a90000 {
1563				compatible = "qcom,geni-debug-uart";
1564				reg = <0x0 0x04a90000 0x0 0x4000>;
1565				clock-names = "se";
1566				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1567				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1568				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1569						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1570						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1571						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1572				interconnect-names = "qup-core",
1573						     "qup-config";
1574				status = "disabled";
1575			};
1576
1577			i2c5: i2c@4a94000 {
1578				compatible = "qcom,geni-i2c";
1579				reg = <0x0 0x04a94000 0x0 0x4000>;
1580				clock-names = "se";
1581				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1582				pinctrl-names = "default";
1583				pinctrl-0 = <&qup_i2c5_default>;
1584				interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1585				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1586				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1587				dma-names = "tx", "rx";
1588				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1589						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1590						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1591						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1592						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1593						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1594				interconnect-names = "qup-core",
1595						     "qup-config",
1596						     "qup-memory";
1597				#address-cells = <1>;
1598				#size-cells = <0>;
1599				status = "disabled";
1600			};
1601
1602			spi5: spi@4a94000 {
1603				compatible = "qcom,geni-spi";
1604				reg = <0x0 0x04a94000 0x0 0x4000>;
1605				clock-names = "se";
1606				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1607				pinctrl-names = "default";
1608				pinctrl-0 = <&qup_spi5_default>;
1609				interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1610				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1611				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1612				dma-names = "tx", "rx";
1613				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1614						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1615						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1616						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1617						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1618						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1619				interconnect-names = "qup-core",
1620						     "qup-config",
1621						     "qup-memory";
1622				#address-cells = <1>;
1623				#size-cells = <0>;
1624				status = "disabled";
1625			};
1626		};
1627
1628		usb: usb@4ef8800 {
1629			compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1630			reg = <0x0 0x04ef8800 0x0 0x400>;
1631			#address-cells = <2>;
1632			#size-cells = <2>;
1633			ranges;
1634
1635			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1636				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1637				 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1638				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1639				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1640				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1641			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1642
1643			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1644					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1645			assigned-clock-rates = <19200000>, <66666667>;
1646
1647			interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1648				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1649				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1650				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1651			interrupt-names = "pwr_event",
1652					  "qusb2_phy",
1653					  "hs_phy_irq",
1654					  "ss_phy_irq";
1655
1656			resets = <&gcc GCC_USB30_PRIM_BCR>;
1657			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1658			 /* TODO: USB<->IPA path */
1659			interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG
1660					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1661					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1662					 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
1663			interconnect-names = "usb-ddr",
1664					     "apps-usb";
1665
1666			status = "disabled";
1667
1668			usb_dwc3: usb@4e00000 {
1669				compatible = "snps,dwc3";
1670				reg = <0x0 0x04e00000 0x0 0xcd00>;
1671				interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1672				phys = <&usb_hsphy>, <&usb_qmpphy>;
1673				phy-names = "usb2-phy", "usb3-phy";
1674				iommus = <&apps_smmu 0x120 0x0>;
1675				snps,dis_u2_susphy_quirk;
1676				snps,dis_enblslpm_quirk;
1677				snps,has-lpm-erratum;
1678				snps,hird-threshold = /bits/ 8 <0x10>;
1679				snps,usb3_lpm_capable;
1680				snps,parkmode-disable-ss-quirk;
1681
1682				usb-role-switch;
1683
1684				ports {
1685					#address-cells = <1>;
1686					#size-cells = <0>;
1687
1688					port@0 {
1689						reg = <0>;
1690
1691						usb_dwc3_hs: endpoint {
1692						};
1693					};
1694
1695					port@1 {
1696						reg = <1>;
1697
1698						usb_dwc3_ss: endpoint {
1699							remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1700						};
1701					};
1702				};
1703			};
1704		};
1705
1706		gpu: gpu@5900000 {
1707			compatible = "qcom,adreno-610.0", "qcom,adreno";
1708			reg = <0x0 0x05900000 0x0 0x40000>;
1709			reg-names = "kgsl_3d0_reg_memory";
1710
1711			/* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1712			clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
1713				 <&gpucc GPU_CC_AHB_CLK>,
1714				 <&gcc GCC_BIMC_GPU_AXI_CLK>,
1715				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1716				 <&gpucc GPU_CC_CX_GMU_CLK>,
1717				 <&gpucc GPU_CC_CXO_CLK>;
1718			clock-names = "core",
1719				      "iface",
1720				      "mem_iface",
1721				      "alt_mem_iface",
1722				      "gmu",
1723				      "xo";
1724
1725			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1726
1727			iommus = <&adreno_smmu 0 1>;
1728			operating-points-v2 = <&gpu_opp_table>;
1729			power-domains = <&rpmpd SM6115_VDDCX>;
1730			qcom,gmu = <&gmu_wrapper>;
1731
1732			nvmem-cells = <&gpu_speed_bin>;
1733			nvmem-cell-names = "speed_bin";
1734			#cooling-cells = <2>;
1735
1736			status = "disabled";
1737
1738			zap-shader {
1739				memory-region = <&pil_gpu_mem>;
1740			};
1741
1742			gpu_opp_table: opp-table {
1743				compatible = "operating-points-v2";
1744
1745				opp-320000000 {
1746					opp-hz = /bits/ 64 <320000000>;
1747					required-opps = <&rpmpd_opp_low_svs>;
1748					opp-supported-hw = <0x1f>;
1749				};
1750
1751				opp-465000000 {
1752					opp-hz = /bits/ 64 <465000000>;
1753					required-opps = <&rpmpd_opp_svs>;
1754					opp-supported-hw = <0x1f>;
1755				};
1756
1757				opp-600000000 {
1758					opp-hz = /bits/ 64 <600000000>;
1759					required-opps = <&rpmpd_opp_svs_plus>;
1760					opp-supported-hw = <0x1f>;
1761				};
1762
1763				opp-745000000 {
1764					opp-hz = /bits/ 64 <745000000>;
1765					required-opps = <&rpmpd_opp_nom>;
1766					opp-supported-hw = <0xf>;
1767				};
1768
1769				opp-820000000 {
1770					opp-hz = /bits/ 64 <820000000>;
1771					required-opps = <&rpmpd_opp_nom_plus>;
1772					opp-supported-hw = <0x7>;
1773				};
1774
1775				opp-900000000 {
1776					opp-hz = /bits/ 64 <900000000>;
1777					required-opps = <&rpmpd_opp_turbo>;
1778					opp-supported-hw = <0x7>;
1779				};
1780
1781				/* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
1782				opp-950000000 {
1783					opp-hz = /bits/ 64 <950000000>;
1784					required-opps = <&rpmpd_opp_turbo_plus>;
1785					opp-supported-hw = <0x4>;
1786				};
1787
1788				opp-980000000 {
1789					opp-hz = /bits/ 64 <980000000>;
1790					required-opps = <&rpmpd_opp_turbo_plus>;
1791					opp-supported-hw = <0x3>;
1792				};
1793			};
1794		};
1795
1796		gmu_wrapper: gmu@596a000 {
1797			compatible = "qcom,adreno-gmu-wrapper";
1798			reg = <0x0 0x0596a000 0x0 0x30000>;
1799			reg-names = "gmu";
1800			power-domains = <&gpucc GPU_CX_GDSC>,
1801					<&gpucc GPU_GX_GDSC>;
1802			power-domain-names = "cx", "gx";
1803		};
1804
1805		gpucc: clock-controller@5990000 {
1806			compatible = "qcom,sm6115-gpucc";
1807			reg = <0x0 0x05990000 0x0 0x9000>;
1808			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1809				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1810				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1811			#clock-cells = <1>;
1812			#reset-cells = <1>;
1813			#power-domain-cells = <1>;
1814		};
1815
1816		adreno_smmu: iommu@59a0000 {
1817			compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1818				     "qcom,smmu-500", "arm,mmu-500";
1819			reg = <0x0 0x059a0000 0x0 0x10000>;
1820			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1821				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1822				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1823				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1824				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1825				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1826				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1827				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1828				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1829
1830			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1831				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1832				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1833			clock-names = "mem",
1834				      "hlos",
1835				      "iface";
1836			power-domains = <&gpucc GPU_CX_GDSC>;
1837
1838			#global-interrupts = <1>;
1839			#iommu-cells = <2>;
1840		};
1841
1842		mdss: display-subsystem@5e00000 {
1843			compatible = "qcom,sm6115-mdss";
1844			reg = <0x0 0x05e00000 0x0 0x1000>;
1845			reg-names = "mdss";
1846
1847			power-domains = <&dispcc MDSS_GDSC>;
1848
1849			clocks = <&gcc GCC_DISP_AHB_CLK>,
1850				 <&gcc GCC_DISP_HF_AXI_CLK>,
1851				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1852
1853			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1854			interrupt-controller;
1855			#interrupt-cells = <1>;
1856
1857			iommus = <&apps_smmu 0x420 0x2>,
1858				 <&apps_smmu 0x421 0x0>;
1859
1860			interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG
1861					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1862					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1863					 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
1864			interconnect-names = "mdp0-mem",
1865					     "cpu-cfg";
1866
1867			#address-cells = <2>;
1868			#size-cells = <2>;
1869			ranges;
1870
1871			status = "disabled";
1872
1873			mdp: display-controller@5e01000 {
1874				compatible = "qcom,sm6115-dpu";
1875				reg = <0x0 0x05e01000 0x0 0x8f000>,
1876				      <0x0 0x05eb0000 0x0 0x2008>;
1877				reg-names = "mdp", "vbif";
1878
1879				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1880					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1881					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1882					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1883					 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1884					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1885				clock-names = "bus",
1886					      "iface",
1887					      "core",
1888					      "lut",
1889					      "rot",
1890					      "vsync";
1891
1892				operating-points-v2 = <&mdp_opp_table>;
1893				power-domains = <&rpmpd SM6115_VDDCX>;
1894
1895				interrupt-parent = <&mdss>;
1896				interrupts = <0>;
1897
1898				ports {
1899					#address-cells = <1>;
1900					#size-cells = <0>;
1901
1902					port@0 {
1903						reg = <0>;
1904						dpu_intf1_out: endpoint {
1905							remote-endpoint = <&mdss_dsi0_in>;
1906						};
1907					};
1908				};
1909
1910				mdp_opp_table: opp-table {
1911					compatible = "operating-points-v2";
1912
1913					opp-19200000 {
1914						opp-hz = /bits/ 64 <19200000>;
1915						required-opps = <&rpmpd_opp_min_svs>;
1916					};
1917
1918					opp-192000000 {
1919						opp-hz = /bits/ 64 <192000000>;
1920						required-opps = <&rpmpd_opp_low_svs>;
1921					};
1922
1923					opp-256000000 {
1924						opp-hz = /bits/ 64 <256000000>;
1925						required-opps = <&rpmpd_opp_svs>;
1926					};
1927
1928					opp-307200000 {
1929						opp-hz = /bits/ 64 <307200000>;
1930						required-opps = <&rpmpd_opp_svs_plus>;
1931					};
1932
1933					opp-384000000 {
1934						opp-hz = /bits/ 64 <384000000>;
1935						required-opps = <&rpmpd_opp_nom>;
1936					};
1937				};
1938			};
1939
1940			mdss_dsi0: dsi@5e94000 {
1941				compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1942				reg = <0x0 0x05e94000 0x0 0x400>;
1943				reg-names = "dsi_ctrl";
1944
1945				interrupt-parent = <&mdss>;
1946				interrupts = <4>;
1947
1948				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1949					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1950					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1951					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1952					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1953					 <&gcc GCC_DISP_HF_AXI_CLK>;
1954				clock-names = "byte",
1955					      "byte_intf",
1956					      "pixel",
1957					      "core",
1958					      "iface",
1959					      "bus";
1960
1961				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1962						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1963				assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1964
1965				operating-points-v2 = <&dsi_opp_table>;
1966				power-domains = <&rpmpd SM6115_VDDCX>;
1967				phys = <&mdss_dsi0_phy>;
1968
1969				#address-cells = <1>;
1970				#size-cells = <0>;
1971
1972				status = "disabled";
1973
1974				ports {
1975					#address-cells = <1>;
1976					#size-cells = <0>;
1977
1978					port@0 {
1979						reg = <0>;
1980						mdss_dsi0_in: endpoint {
1981							remote-endpoint = <&dpu_intf1_out>;
1982						};
1983					};
1984
1985					port@1 {
1986						reg = <1>;
1987						mdss_dsi0_out: endpoint {
1988						};
1989					};
1990				};
1991
1992				dsi_opp_table: opp-table {
1993					compatible = "operating-points-v2";
1994
1995					opp-19200000 {
1996						opp-hz = /bits/ 64 <19200000>;
1997						required-opps = <&rpmpd_opp_min_svs>;
1998					};
1999
2000					opp-164000000 {
2001						opp-hz = /bits/ 64 <164000000>;
2002						required-opps = <&rpmpd_opp_low_svs>;
2003					};
2004
2005					opp-187500000 {
2006						opp-hz = /bits/ 64 <187500000>;
2007						required-opps = <&rpmpd_opp_svs>;
2008					};
2009				};
2010			};
2011
2012			mdss_dsi0_phy: phy@5e94400 {
2013				compatible = "qcom,dsi-phy-14nm-2290";
2014				reg = <0x0 0x05e94400 0x0 0x100>,
2015				      <0x0 0x05e94500 0x0 0x300>,
2016				      <0x0 0x05e94800 0x0 0x188>;
2017				reg-names = "dsi_phy",
2018					    "dsi_phy_lane",
2019					    "dsi_pll";
2020
2021				#clock-cells = <1>;
2022				#phy-cells = <0>;
2023
2024				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2025					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2026				clock-names = "iface", "ref";
2027
2028				status = "disabled";
2029			};
2030		};
2031
2032		dispcc: clock-controller@5f00000 {
2033			compatible = "qcom,sm6115-dispcc";
2034			reg = <0x0 0x05f00000 0 0x20000>;
2035			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2036				 <&sleep_clk>,
2037				 <&mdss_dsi0_phy 0>,
2038				 <&mdss_dsi0_phy 1>,
2039				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
2040			#clock-cells = <1>;
2041			#reset-cells = <1>;
2042			#power-domain-cells = <1>;
2043		};
2044
2045		remoteproc_mpss: remoteproc@6080000 {
2046			compatible = "qcom,sm6115-mpss-pas";
2047			reg = <0x0 0x06080000 0x0 0x10000>;
2048
2049			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
2050					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2051					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2052					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2053					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2054					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2055			interrupt-names = "wdog", "fatal", "ready", "handover",
2056					  "stop-ack", "shutdown-ack";
2057
2058			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2059			clock-names = "xo";
2060
2061			power-domains = <&rpmpd SM6115_VDDCX>;
2062
2063			memory-region = <&pil_modem_mem>;
2064
2065			qcom,smem-states = <&modem_smp2p_out 0>;
2066			qcom,smem-state-names = "stop";
2067
2068			status = "disabled";
2069
2070			glink-edge {
2071				interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
2072				label = "mpss";
2073				qcom,remote-pid = <1>;
2074				mboxes = <&apcs_glb 12>;
2075			};
2076		};
2077
2078		stm@8002000 {
2079			compatible = "arm,coresight-stm", "arm,primecell";
2080			reg = <0x0 0x08002000 0x0 0x1000>,
2081			      <0x0 0x0e280000 0x0 0x180000>;
2082			reg-names = "stm-base", "stm-stimulus-base";
2083
2084			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2085			clock-names = "apb_pclk";
2086
2087			status = "disabled";
2088
2089			out-ports {
2090				port {
2091					stm_out: endpoint {
2092						remote-endpoint = <&funnel_in0_in>;
2093					};
2094				};
2095			};
2096		};
2097
2098		cti0: cti@8010000 {
2099			compatible = "arm,coresight-cti", "arm,primecell";
2100			reg = <0x0 0x08010000 0x0 0x1000>;
2101
2102			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2103			clock-names = "apb_pclk";
2104
2105			status = "disabled";
2106		};
2107
2108		cti1: cti@8011000 {
2109			compatible = "arm,coresight-cti", "arm,primecell";
2110			reg = <0x0 0x08011000 0x0 0x1000>;
2111
2112			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2113			clock-names = "apb_pclk";
2114
2115			status = "disabled";
2116		};
2117
2118		cti2: cti@8012000 {
2119			compatible = "arm,coresight-cti", "arm,primecell";
2120			reg = <0x0 0x08012000 0x0 0x1000>;
2121
2122			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2123			clock-names = "apb_pclk";
2124
2125			status = "disabled";
2126		};
2127
2128		cti3: cti@8013000 {
2129			compatible = "arm,coresight-cti", "arm,primecell";
2130			reg = <0x0 0x08013000 0x0 0x1000>;
2131
2132			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2133			clock-names = "apb_pclk";
2134
2135			status = "disabled";
2136		};
2137
2138		cti4: cti@8014000 {
2139			compatible = "arm,coresight-cti", "arm,primecell";
2140			reg = <0x0 0x08014000 0x0 0x1000>;
2141
2142			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2143			clock-names = "apb_pclk";
2144
2145			status = "disabled";
2146		};
2147
2148		cti5: cti@8015000 {
2149			compatible = "arm,coresight-cti", "arm,primecell";
2150			reg = <0x0 0x08015000 0x0 0x1000>;
2151
2152			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2153			clock-names = "apb_pclk";
2154
2155			status = "disabled";
2156		};
2157
2158		cti6: cti@8016000 {
2159			compatible = "arm,coresight-cti", "arm,primecell";
2160			reg = <0x0 0x08016000 0x0 0x1000>;
2161
2162			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2163			clock-names = "apb_pclk";
2164
2165			status = "disabled";
2166		};
2167
2168		cti7: cti@8017000 {
2169			compatible = "arm,coresight-cti", "arm,primecell";
2170			reg = <0x0 0x08017000 0x0 0x1000>;
2171
2172			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2173			clock-names = "apb_pclk";
2174
2175			status = "disabled";
2176		};
2177
2178		cti8: cti@8018000 {
2179			compatible = "arm,coresight-cti", "arm,primecell";
2180			reg = <0x0 0x08018000 0x0 0x1000>;
2181
2182			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2183			clock-names = "apb_pclk";
2184
2185			status = "disabled";
2186		};
2187
2188		cti9: cti@8019000 {
2189			compatible = "arm,coresight-cti", "arm,primecell";
2190			reg = <0x0 0x08019000 0x0 0x1000>;
2191
2192			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2193			clock-names = "apb_pclk";
2194
2195			status = "disabled";
2196		};
2197
2198		cti10: cti@801a000 {
2199			compatible = "arm,coresight-cti", "arm,primecell";
2200			reg = <0x0 0x0801a000 0x0 0x1000>;
2201
2202			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2203			clock-names = "apb_pclk";
2204
2205			status = "disabled";
2206		};
2207
2208		cti11: cti@801b000 {
2209			compatible = "arm,coresight-cti", "arm,primecell";
2210			reg = <0x0 0x0801b000 0x0 0x1000>;
2211
2212			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2213			clock-names = "apb_pclk";
2214
2215			status = "disabled";
2216		};
2217
2218		cti12: cti@801c000 {
2219			compatible = "arm,coresight-cti", "arm,primecell";
2220			reg = <0x0 0x0801c000 0x0 0x1000>;
2221
2222			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2223			clock-names = "apb_pclk";
2224
2225			status = "disabled";
2226		};
2227
2228		cti13: cti@801d000 {
2229			compatible = "arm,coresight-cti", "arm,primecell";
2230			reg = <0x0 0x0801d000 0x0 0x1000>;
2231
2232			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2233			clock-names = "apb_pclk";
2234
2235			status = "disabled";
2236		};
2237
2238		cti14: cti@801e000 {
2239			compatible = "arm,coresight-cti", "arm,primecell";
2240			reg = <0x0 0x0801e000 0x0 0x1000>;
2241
2242			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2243			clock-names = "apb_pclk";
2244
2245			status = "disabled";
2246		};
2247
2248		cti15: cti@801f000 {
2249			compatible = "arm,coresight-cti", "arm,primecell";
2250			reg = <0x0 0x0801f000 0x0 0x1000>;
2251
2252			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2253			clock-names = "apb_pclk";
2254
2255			status = "disabled";
2256		};
2257
2258		replicator@8046000 {
2259			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2260			reg = <0x0 0x08046000 0x0 0x1000>;
2261
2262			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2263			clock-names = "apb_pclk";
2264
2265			status = "disabled";
2266
2267			out-ports {
2268				port {
2269					replicator_out: endpoint {
2270						remote-endpoint = <&etr_in>;
2271					};
2272				};
2273			};
2274
2275			in-ports {
2276				port {
2277					replicator_in: endpoint {
2278						remote-endpoint = <&etf_out>;
2279					};
2280				};
2281			};
2282		};
2283
2284		etf@8047000 {
2285			compatible = "arm,coresight-tmc", "arm,primecell";
2286			reg = <0x0 0x08047000 0x0 0x1000>;
2287
2288			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2289			clock-names = "apb_pclk";
2290
2291			status = "disabled";
2292
2293			in-ports {
2294				port {
2295					etf_in: endpoint {
2296						remote-endpoint = <&merge_funnel_out>;
2297					};
2298				};
2299			};
2300
2301			out-ports {
2302				port {
2303					etf_out: endpoint {
2304						remote-endpoint = <&replicator_in>;
2305					};
2306				};
2307			};
2308		};
2309
2310		etr@8048000 {
2311			compatible = "arm,coresight-tmc", "arm,primecell";
2312			reg = <0x0 0x08048000 0x0 0x1000>;
2313
2314			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2315			clock-names = "apb_pclk";
2316
2317			status = "disabled";
2318
2319			in-ports {
2320				port {
2321					etr_in: endpoint {
2322						remote-endpoint = <&replicator_out>;
2323					};
2324				};
2325			};
2326		};
2327
2328		funnel@8041000 {
2329			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2330			reg = <0x0 0x08041000 0x0 0x1000>;
2331
2332			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2333			clock-names = "apb_pclk";
2334
2335			status = "disabled";
2336
2337			out-ports {
2338				port {
2339					funnel_in0_out: endpoint {
2340						remote-endpoint = <&merge_funnel_in0>;
2341					};
2342				};
2343			};
2344
2345			in-ports {
2346				port {
2347					funnel_in0_in: endpoint {
2348						remote-endpoint = <&stm_out>;
2349					};
2350				};
2351			};
2352		};
2353
2354		funnel@8042000 {
2355			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2356			reg = <0x0 0x08042000 0x0 0x1000>;
2357
2358			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2359			clock-names = "apb_pclk";
2360
2361			status = "disabled";
2362
2363			out-ports {
2364				port {
2365					funnel_in1_out: endpoint {
2366						remote-endpoint = <&merge_funnel_in1>;
2367					};
2368				};
2369			};
2370
2371			in-ports {
2372				port {
2373					funnel_in1_in: endpoint {
2374						remote-endpoint = <&funnel_apss1_out>;
2375					};
2376				};
2377			};
2378		};
2379
2380		funnel@8045000 {
2381			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2382			reg = <0x0 0x08045000 0x0 0x1000>;
2383
2384			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2385			clock-names = "apb_pclk";
2386
2387			status = "disabled";
2388
2389			out-ports {
2390				port {
2391					merge_funnel_out: endpoint {
2392						remote-endpoint = <&etf_in>;
2393					};
2394				};
2395			};
2396
2397			in-ports {
2398				#address-cells = <1>;
2399				#size-cells = <0>;
2400
2401				port@0 {
2402					reg = <0>;
2403					merge_funnel_in0: endpoint {
2404						remote-endpoint = <&funnel_in0_out>;
2405					};
2406				};
2407
2408				port@1 {
2409					reg = <1>;
2410					merge_funnel_in1: endpoint {
2411						remote-endpoint = <&funnel_in1_out>;
2412					};
2413				};
2414			};
2415		};
2416
2417		etm@9040000 {
2418			compatible = "arm,coresight-etm4x", "arm,primecell";
2419			reg = <0x0 0x09040000 0x0 0x1000>;
2420
2421			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2422			clock-names = "apb_pclk";
2423			arm,coresight-loses-context-with-cpu;
2424
2425			cpu = <&cpu0>;
2426
2427			status = "disabled";
2428
2429			out-ports {
2430				port {
2431					etm0_out: endpoint {
2432						remote-endpoint = <&funnel_apss0_in0>;
2433					};
2434				};
2435			};
2436		};
2437
2438		etm@9140000 {
2439			compatible = "arm,coresight-etm4x", "arm,primecell";
2440			reg = <0x0 0x09140000 0x0 0x1000>;
2441
2442			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2443			clock-names = "apb_pclk";
2444			arm,coresight-loses-context-with-cpu;
2445
2446			cpu = <&cpu1>;
2447
2448			status = "disabled";
2449
2450			out-ports {
2451				port {
2452					etm1_out: endpoint {
2453						remote-endpoint = <&funnel_apss0_in1>;
2454					};
2455				};
2456			};
2457		};
2458
2459		etm@9240000 {
2460			compatible = "arm,coresight-etm4x", "arm,primecell";
2461			reg = <0x0 0x09240000 0x0 0x1000>;
2462
2463			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2464			clock-names = "apb_pclk";
2465			arm,coresight-loses-context-with-cpu;
2466
2467			cpu = <&cpu2>;
2468
2469			status = "disabled";
2470
2471			out-ports {
2472				port {
2473					etm2_out: endpoint {
2474						remote-endpoint = <&funnel_apss0_in2>;
2475					};
2476				};
2477			};
2478		};
2479
2480		etm@9340000 {
2481			compatible = "arm,coresight-etm4x", "arm,primecell";
2482			reg = <0x0 0x09340000 0x0 0x1000>;
2483
2484			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2485			clock-names = "apb_pclk";
2486			arm,coresight-loses-context-with-cpu;
2487
2488			cpu = <&cpu3>;
2489
2490			status = "disabled";
2491
2492			out-ports {
2493				port {
2494					etm3_out: endpoint {
2495						remote-endpoint = <&funnel_apss0_in3>;
2496					};
2497				};
2498			};
2499		};
2500
2501		etm@9440000 {
2502			compatible = "arm,coresight-etm4x", "arm,primecell";
2503			reg = <0x0 0x09440000 0x0 0x1000>;
2504
2505			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2506			clock-names = "apb_pclk";
2507			arm,coresight-loses-context-with-cpu;
2508
2509			cpu = <&cpu4>;
2510
2511			status = "disabled";
2512
2513			out-ports {
2514				port {
2515					etm4_out: endpoint {
2516						remote-endpoint = <&funnel_apss0_in4>;
2517					};
2518				};
2519			};
2520		};
2521
2522		etm@9540000 {
2523			compatible = "arm,coresight-etm4x", "arm,primecell";
2524			reg = <0x0 0x09540000 0x0 0x1000>;
2525
2526			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2527			clock-names = "apb_pclk";
2528			arm,coresight-loses-context-with-cpu;
2529
2530			cpu = <&cpu5>;
2531
2532			status = "disabled";
2533
2534			out-ports {
2535				port {
2536					etm5_out: endpoint {
2537						remote-endpoint = <&funnel_apss0_in5>;
2538					};
2539				};
2540			};
2541		};
2542
2543		etm@9640000 {
2544			compatible = "arm,coresight-etm4x", "arm,primecell";
2545			reg = <0x0 0x09640000 0x0 0x1000>;
2546
2547			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2548			clock-names = "apb_pclk";
2549			arm,coresight-loses-context-with-cpu;
2550
2551			cpu = <&cpu6>;
2552
2553			status = "disabled";
2554
2555			out-ports {
2556				port {
2557					etm6_out: endpoint {
2558						remote-endpoint = <&funnel_apss0_in6>;
2559					};
2560				};
2561			};
2562		};
2563
2564		etm@9740000 {
2565			compatible = "arm,coresight-etm4x", "arm,primecell";
2566			reg = <0x0 0x09740000 0x0 0x1000>;
2567
2568			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2569			clock-names = "apb_pclk";
2570			arm,coresight-loses-context-with-cpu;
2571
2572			cpu = <&cpu7>;
2573
2574			status = "disabled";
2575
2576			out-ports {
2577				port {
2578					etm7_out: endpoint {
2579						remote-endpoint = <&funnel_apss0_in7>;
2580					};
2581				};
2582			};
2583		};
2584
2585		funnel@9800000 {
2586			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2587			reg = <0x0 0x09800000 0x0 0x1000>;
2588
2589			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2590			clock-names = "apb_pclk";
2591
2592			status = "disabled";
2593
2594			out-ports {
2595				port {
2596					funnel_apss0_out: endpoint {
2597						remote-endpoint = <&funnel_apss1_in>;
2598					};
2599				};
2600			};
2601
2602			in-ports {
2603				#address-cells = <1>;
2604				#size-cells = <0>;
2605
2606				port@0 {
2607					reg = <0>;
2608					funnel_apss0_in0: endpoint {
2609						remote-endpoint = <&etm0_out>;
2610					};
2611				};
2612
2613				port@1 {
2614					reg = <1>;
2615					funnel_apss0_in1: endpoint {
2616						remote-endpoint = <&etm1_out>;
2617					};
2618				};
2619
2620				port@2 {
2621					reg = <2>;
2622					funnel_apss0_in2: endpoint {
2623						remote-endpoint = <&etm2_out>;
2624					};
2625				};
2626
2627				port@3 {
2628					reg = <3>;
2629					funnel_apss0_in3: endpoint {
2630						remote-endpoint = <&etm3_out>;
2631					};
2632				};
2633
2634				port@4 {
2635					reg = <4>;
2636					funnel_apss0_in4: endpoint {
2637						remote-endpoint = <&etm4_out>;
2638					};
2639				};
2640
2641				port@5 {
2642					reg = <5>;
2643					funnel_apss0_in5: endpoint {
2644						remote-endpoint = <&etm5_out>;
2645					};
2646				};
2647
2648				port@6 {
2649					reg = <6>;
2650					funnel_apss0_in6: endpoint {
2651						remote-endpoint = <&etm6_out>;
2652					};
2653				};
2654
2655				port@7 {
2656					reg = <7>;
2657					funnel_apss0_in7: endpoint {
2658						remote-endpoint = <&etm7_out>;
2659					};
2660				};
2661			};
2662		};
2663
2664		funnel@9810000 {
2665			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2666			reg = <0x0 0x09810000 0x0 0x1000>;
2667
2668			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2669			clock-names = "apb_pclk";
2670
2671			status = "disabled";
2672
2673			out-ports {
2674				port {
2675					funnel_apss1_out: endpoint {
2676						remote-endpoint = <&funnel_in1_in>;
2677					};
2678				};
2679			};
2680
2681			in-ports {
2682				port {
2683					funnel_apss1_in: endpoint {
2684						remote-endpoint = <&funnel_apss0_out>;
2685					};
2686				};
2687			};
2688		};
2689
2690		remoteproc_adsp: remoteproc@a400000 {
2691			compatible = "qcom,sm6115-adsp-pas";
2692			reg = <0x0 0x0a400000 0x0 0x4040>;
2693
2694			interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2695					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2696					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2697					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2698					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2699			interrupt-names = "wdog", "fatal", "ready",
2700					  "handover", "stop-ack";
2701
2702			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2703			clock-names = "xo";
2704
2705			power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2706					<&rpmpd SM6115_VDD_LPI_MX>;
2707
2708			memory-region = <&pil_adsp_mem>;
2709
2710			qcom,smem-states = <&adsp_smp2p_out 0>;
2711			qcom,smem-state-names = "stop";
2712
2713			status = "disabled";
2714
2715			glink-edge {
2716				interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
2717				label = "lpass";
2718				qcom,remote-pid = <2>;
2719				mboxes = <&apcs_glb 8>;
2720
2721				apr {
2722					compatible = "qcom,apr-v2";
2723					qcom,glink-channels = "apr_audio_svc";
2724					qcom,domain = <APR_DOMAIN_ADSP>;
2725					#address-cells = <1>;
2726					#size-cells = <0>;
2727
2728					service@3 {
2729						reg = <APR_SVC_ADSP_CORE>;
2730						compatible = "qcom,q6core";
2731						qcom,protection-domain = "avs/audio",
2732									 "msm/adsp/audio_pd";
2733					};
2734
2735					q6afe: service@4 {
2736						compatible = "qcom,q6afe";
2737						reg = <APR_SVC_AFE>;
2738						qcom,protection-domain = "avs/audio",
2739									 "msm/adsp/audio_pd";
2740						q6afedai: dais {
2741							compatible = "qcom,q6afe-dais";
2742							#address-cells = <1>;
2743							#size-cells = <0>;
2744							#sound-dai-cells = <1>;
2745						};
2746
2747						q6afecc: clock-controller {
2748							compatible = "qcom,q6afe-clocks";
2749							#clock-cells = <2>;
2750						};
2751					};
2752
2753					q6asm: service@7 {
2754						compatible = "qcom,q6asm";
2755						reg = <APR_SVC_ASM>;
2756						qcom,protection-domain = "avs/audio",
2757									 "msm/adsp/audio_pd";
2758						q6asmdai: dais {
2759							compatible = "qcom,q6asm-dais";
2760							#address-cells = <1>;
2761							#size-cells = <0>;
2762							#sound-dai-cells = <1>;
2763							iommus = <&apps_smmu 0x1c1 0x0>;
2764
2765							dai@0 {
2766								reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>;
2767							};
2768
2769							dai@1 {
2770								reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>;
2771							};
2772
2773							dai@2 {
2774								reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>;
2775							};
2776						};
2777					};
2778
2779					q6adm: service@8 {
2780						compatible = "qcom,q6adm";
2781						reg = <APR_SVC_ADM>;
2782						qcom,protection-domain = "avs/audio",
2783									 "msm/adsp/audio_pd";
2784						q6routing: routing {
2785							compatible = "qcom,q6adm-routing";
2786							#sound-dai-cells = <0>;
2787						};
2788					};
2789				};
2790
2791				fastrpc {
2792					compatible = "qcom,fastrpc";
2793					qcom,glink-channels = "fastrpcglink-apps-dsp";
2794					label = "adsp";
2795					qcom,non-secure-domain;
2796					#address-cells = <1>;
2797					#size-cells = <0>;
2798
2799					compute-cb@3 {
2800						compatible = "qcom,fastrpc-compute-cb";
2801						reg = <3>;
2802						iommus = <&apps_smmu 0x01c3 0x0>;
2803					};
2804
2805					compute-cb@4 {
2806						compatible = "qcom,fastrpc-compute-cb";
2807						reg = <4>;
2808						iommus = <&apps_smmu 0x01c4 0x0>;
2809					};
2810
2811					compute-cb@5 {
2812						compatible = "qcom,fastrpc-compute-cb";
2813						reg = <5>;
2814						iommus = <&apps_smmu 0x01c5 0x0>;
2815					};
2816
2817					compute-cb@6 {
2818						compatible = "qcom,fastrpc-compute-cb";
2819						reg = <6>;
2820						iommus = <&apps_smmu 0x01c6 0x0>;
2821					};
2822
2823					compute-cb@7 {
2824						compatible = "qcom,fastrpc-compute-cb";
2825						reg = <7>;
2826						iommus = <&apps_smmu 0x01c7 0x0>;
2827					};
2828				};
2829			};
2830		};
2831
2832		remoteproc_cdsp: remoteproc@b300000 {
2833			compatible = "qcom,sm6115-cdsp-pas";
2834			reg = <0x0 0x0b300000 0x0 0x4040>;
2835
2836			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2837					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2838					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2839					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2840					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2841			interrupt-names = "wdog", "fatal", "ready",
2842					  "handover", "stop-ack";
2843
2844			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2845			clock-names = "xo";
2846
2847			power-domains = <&rpmpd SM6115_VDDCX>;
2848
2849			memory-region = <&pil_cdsp_mem>;
2850
2851			qcom,smem-states = <&cdsp_smp2p_out 0>;
2852			qcom,smem-state-names = "stop";
2853
2854			status = "disabled";
2855
2856			glink-edge {
2857				interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2858				label = "cdsp";
2859				qcom,remote-pid = <5>;
2860				mboxes = <&apcs_glb 28>;
2861
2862				fastrpc {
2863					compatible = "qcom,fastrpc";
2864					qcom,glink-channels = "fastrpcglink-apps-dsp";
2865					label = "cdsp";
2866					qcom,non-secure-domain;
2867					#address-cells = <1>;
2868					#size-cells = <0>;
2869
2870					compute-cb@1 {
2871						compatible = "qcom,fastrpc-compute-cb";
2872						reg = <1>;
2873						iommus = <&apps_smmu 0x0c01 0x0>;
2874					};
2875
2876					compute-cb@2 {
2877						compatible = "qcom,fastrpc-compute-cb";
2878						reg = <2>;
2879						iommus = <&apps_smmu 0x0c02 0x0>;
2880					};
2881
2882					compute-cb@3 {
2883						compatible = "qcom,fastrpc-compute-cb";
2884						reg = <3>;
2885						iommus = <&apps_smmu 0x0c03 0x0>;
2886					};
2887
2888					compute-cb@4 {
2889						compatible = "qcom,fastrpc-compute-cb";
2890						reg = <4>;
2891						iommus = <&apps_smmu 0x0c04 0x0>;
2892					};
2893
2894					compute-cb@5 {
2895						compatible = "qcom,fastrpc-compute-cb";
2896						reg = <5>;
2897						iommus = <&apps_smmu 0x0c05 0x0>;
2898					};
2899
2900					compute-cb@6 {
2901						compatible = "qcom,fastrpc-compute-cb";
2902						reg = <6>;
2903						iommus = <&apps_smmu 0x0c06 0x0>;
2904					};
2905
2906					/* note: secure cb9 in downstream */
2907				};
2908			};
2909		};
2910
2911		apps_smmu: iommu@c600000 {
2912			compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2913			reg = <0x0 0x0c600000 0x0 0x80000>;
2914			#iommu-cells = <2>;
2915			#global-interrupts = <1>;
2916
2917			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
2918				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
2919				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
2920				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
2921				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
2922				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
2923				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
2924				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
2925				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2926				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2927				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2928				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2929				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2930				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2931				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2932				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2933				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2934				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2935				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2936				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2937				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2938				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2939				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2940				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2941				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2942				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2943				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2944				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2945				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2946				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2947				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2948				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2949				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
2950				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
2951				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
2952				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
2953				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2954				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2955				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2956				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2957				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2958				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
2959				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
2960				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2961				     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2962				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2963				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2964				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2965				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2966				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2967				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
2968				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
2969				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2970				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2971				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2972				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2973				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2974				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2975				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2976				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2977				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2978				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2979				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2980				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2981				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2982		};
2983
2984		wifi: wifi@c800000 {
2985			compatible = "qcom,wcn3990-wifi";
2986			reg = <0x0 0x0c800000 0x0 0x800000>;
2987			reg-names = "membase";
2988			memory-region = <&wlan_msa_mem>;
2989			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
2990				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
2991				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
2992				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
2993				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
2994				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
2995				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
2996				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
2997				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
2998				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
2999				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
3000				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
3001			iommus = <&apps_smmu 0x1a0 0x1>;
3002			qcom,msa-fixed-perm;
3003			status = "disabled";
3004		};
3005
3006		watchdog@f017000 {
3007			compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
3008			reg = <0x0 0x0f017000 0x0 0x1000>;
3009			clocks = <&sleep_clk>;
3010			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
3011		};
3012
3013		apcs_glb: mailbox@f111000 {
3014			compatible = "qcom,sm6115-apcs-hmss-global",
3015				     "qcom,msm8994-apcs-kpss-global";
3016			reg = <0x0 0x0f111000 0x0 0x1000>;
3017
3018			#mbox-cells = <1>;
3019		};
3020
3021		timer@f120000 {
3022			compatible = "arm,armv7-timer-mem";
3023			reg = <0x0 0x0f120000 0x0 0x1000>;
3024			#address-cells = <2>;
3025			#size-cells = <1>;
3026			ranges = <0x0 0x0 0x0 0x0 0x20000000>;
3027			clock-frequency = <19200000>;
3028
3029			frame@f121000 {
3030				reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
3031				frame-number = <0>;
3032				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3033					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3034			};
3035
3036			frame@f123000 {
3037				reg = <0x0 0x0f123000 0x1000>;
3038				frame-number = <1>;
3039				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3040				status = "disabled";
3041			};
3042
3043			frame@f124000 {
3044				reg = <0x0 0x0f124000 0x1000>;
3045				frame-number = <2>;
3046				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3047				status = "disabled";
3048			};
3049
3050			frame@f125000 {
3051				reg = <0x0 0x0f125000 0x1000>;
3052				frame-number = <3>;
3053				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3054				status = "disabled";
3055			};
3056
3057			frame@f126000 {
3058				reg = <0x0 0x0f126000 0x1000>;
3059				frame-number = <4>;
3060				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3061				status = "disabled";
3062			};
3063
3064			frame@f127000 {
3065				reg = <0x0 0x0f127000 0x1000>;
3066				frame-number = <5>;
3067				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3068				status = "disabled";
3069			};
3070
3071			frame@f128000 {
3072				reg = <0x0 0x0f128000 0x1000>;
3073				frame-number = <6>;
3074				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3075				status = "disabled";
3076			};
3077		};
3078
3079		intc: interrupt-controller@f200000 {
3080			compatible = "arm,gic-v3";
3081			reg = <0x0 0x0f200000 0x0 0x10000>,
3082			      <0x0 0x0f300000 0x0 0x100000>;
3083			#interrupt-cells = <3>;
3084			interrupt-controller;
3085			interrupt-parent = <&intc>;
3086			#redistributor-regions = <1>;
3087			redistributor-stride = <0x0 0x20000>;
3088			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3089		};
3090
3091		cpufreq_hw: cpufreq@f521000 {
3092			compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
3093			reg = <0x0 0x0f521000 0x0 0x1000>,
3094			      <0x0 0x0f523000 0x0 0x1000>;
3095
3096			reg-names = "freq-domain0", "freq-domain1";
3097			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
3098			clock-names = "xo", "alternate";
3099
3100			#freq-domain-cells = <1>;
3101			#clock-cells = <1>;
3102		};
3103	};
3104
3105	thermal-zones {
3106		mapss-thermal {
3107			thermal-sensors = <&tsens0 0>;
3108
3109			trips {
3110				trip-point0 {
3111					temperature = <115000>;
3112					hysteresis = <5000>;
3113					type = "passive";
3114				};
3115
3116				trip-point1 {
3117					temperature = <125000>;
3118					hysteresis = <1000>;
3119					type = "passive";
3120				};
3121			};
3122		};
3123
3124		cdsp-hvx-thermal {
3125			thermal-sensors = <&tsens0 1>;
3126
3127			trips {
3128				trip-point0 {
3129					temperature = <115000>;
3130					hysteresis = <5000>;
3131					type = "passive";
3132				};
3133
3134				trip-point1 {
3135					temperature = <125000>;
3136					hysteresis = <1000>;
3137					type = "passive";
3138				};
3139			};
3140		};
3141
3142		wlan-thermal {
3143			thermal-sensors = <&tsens0 2>;
3144
3145			trips {
3146				trip-point0 {
3147					temperature = <115000>;
3148					hysteresis = <5000>;
3149					type = "passive";
3150				};
3151
3152				trip-point1 {
3153					temperature = <125000>;
3154					hysteresis = <1000>;
3155					type = "passive";
3156				};
3157			};
3158		};
3159
3160		camera-thermal {
3161			thermal-sensors = <&tsens0 3>;
3162
3163			trips {
3164				trip-point0 {
3165					temperature = <115000>;
3166					hysteresis = <5000>;
3167					type = "passive";
3168				};
3169
3170				trip-point1 {
3171					temperature = <125000>;
3172					hysteresis = <1000>;
3173					type = "passive";
3174				};
3175			};
3176		};
3177
3178		video-thermal {
3179			thermal-sensors = <&tsens0 4>;
3180
3181			trips {
3182				trip-point0 {
3183					temperature = <115000>;
3184					hysteresis = <5000>;
3185					type = "passive";
3186				};
3187
3188				trip-point1 {
3189					temperature = <125000>;
3190					hysteresis = <1000>;
3191					type = "passive";
3192				};
3193			};
3194		};
3195
3196		modem1-thermal {
3197			thermal-sensors = <&tsens0 5>;
3198
3199			trips {
3200				trip-point0 {
3201					temperature = <115000>;
3202					hysteresis = <5000>;
3203					type = "passive";
3204				};
3205
3206				trip-point1 {
3207					temperature = <125000>;
3208					hysteresis = <1000>;
3209					type = "passive";
3210				};
3211			};
3212		};
3213
3214		cpu4-thermal {
3215			thermal-sensors = <&tsens0 6>;
3216
3217			trips {
3218				cpu4_alert0: trip-point0 {
3219					temperature = <90000>;
3220					hysteresis = <2000>;
3221					type = "passive";
3222				};
3223
3224				cpu4_alert1: trip-point1 {
3225					temperature = <95000>;
3226					hysteresis = <2000>;
3227					type = "passive";
3228				};
3229
3230				cpu4_crit: cpu-crit {
3231					temperature = <110000>;
3232					hysteresis = <1000>;
3233					type = "critical";
3234				};
3235			};
3236		};
3237
3238		cpu5-thermal {
3239			thermal-sensors = <&tsens0 7>;
3240
3241			trips {
3242				cpu5_alert0: trip-point0 {
3243					temperature = <90000>;
3244					hysteresis = <2000>;
3245					type = "passive";
3246				};
3247
3248				cpu5_alert1: trip-point1 {
3249					temperature = <95000>;
3250					hysteresis = <2000>;
3251					type = "passive";
3252				};
3253
3254				cpu5_crit: cpu-crit {
3255					temperature = <110000>;
3256					hysteresis = <1000>;
3257					type = "critical";
3258				};
3259			};
3260		};
3261
3262		cpu6-thermal {
3263			thermal-sensors = <&tsens0 8>;
3264
3265			trips {
3266				cpu6_alert0: trip-point0 {
3267					temperature = <90000>;
3268					hysteresis = <2000>;
3269					type = "passive";
3270				};
3271
3272				cpu6_alert1: trip-point1 {
3273					temperature = <95000>;
3274					hysteresis = <2000>;
3275					type = "passive";
3276				};
3277
3278				cpu6_crit: cpu-crit {
3279					temperature = <110000>;
3280					hysteresis = <1000>;
3281					type = "critical";
3282				};
3283			};
3284		};
3285
3286		cpu7-thermal {
3287			thermal-sensors = <&tsens0 9>;
3288
3289			trips {
3290				cpu7_alert0: trip-point0 {
3291					temperature = <90000>;
3292					hysteresis = <2000>;
3293					type = "passive";
3294				};
3295
3296				cpu7_alert1: trip-point1 {
3297					temperature = <95000>;
3298					hysteresis = <2000>;
3299					type = "passive";
3300				};
3301
3302				cpu7_crit: cpu-crit {
3303					temperature = <110000>;
3304					hysteresis = <1000>;
3305					type = "critical";
3306				};
3307			};
3308		};
3309
3310		cpu45-thermal {
3311			thermal-sensors = <&tsens0 10>;
3312
3313			trips {
3314				cpu45_alert0: trip-point0 {
3315					temperature = <90000>;
3316					hysteresis = <2000>;
3317					type = "passive";
3318				};
3319
3320				cpu45_alert1: trip-point1 {
3321					temperature = <95000>;
3322					hysteresis = <2000>;
3323					type = "passive";
3324				};
3325
3326				cpu45_crit: cpu-crit {
3327					temperature = <110000>;
3328					hysteresis = <1000>;
3329					type = "critical";
3330				};
3331			};
3332		};
3333
3334		cpu67-thermal {
3335			thermal-sensors = <&tsens0 11>;
3336
3337			trips {
3338				cpu67_alert0: trip-point0 {
3339					temperature = <90000>;
3340					hysteresis = <2000>;
3341					type = "passive";
3342				};
3343
3344				cpu67_alert1: trip-point1 {
3345					temperature = <95000>;
3346					hysteresis = <2000>;
3347					type = "passive";
3348				};
3349
3350				cpu67_crit: cpu-crit {
3351					temperature = <110000>;
3352					hysteresis = <1000>;
3353					type = "critical";
3354				};
3355			};
3356		};
3357
3358		cpu0123-thermal {
3359			thermal-sensors = <&tsens0 12>;
3360
3361			trips {
3362				cpu0123_alert0: trip-point0 {
3363					temperature = <90000>;
3364					hysteresis = <2000>;
3365					type = "passive";
3366				};
3367
3368				cpu0123_alert1: trip-point1 {
3369					temperature = <95000>;
3370					hysteresis = <2000>;
3371					type = "passive";
3372				};
3373
3374				cpu0123_crit: cpu-crit {
3375					temperature = <110000>;
3376					hysteresis = <1000>;
3377					type = "critical";
3378				};
3379			};
3380		};
3381
3382		modem0-thermal {
3383			thermal-sensors = <&tsens0 13>;
3384
3385			trips {
3386				trip-point0 {
3387					temperature = <115000>;
3388					hysteresis = <5000>;
3389					type = "passive";
3390				};
3391
3392				trip-point1 {
3393					temperature = <125000>;
3394					hysteresis = <1000>;
3395					type = "passive";
3396				};
3397			};
3398		};
3399
3400		display-thermal {
3401			thermal-sensors = <&tsens0 14>;
3402
3403			trips {
3404				trip-point0 {
3405					temperature = <115000>;
3406					hysteresis = <5000>;
3407					type = "passive";
3408				};
3409
3410				trip-point1 {
3411					temperature = <125000>;
3412					hysteresis = <1000>;
3413					type = "passive";
3414				};
3415			};
3416		};
3417
3418		gpu-thermal {
3419			polling-delay-passive = <250>;
3420
3421			thermal-sensors = <&tsens0 15>;
3422
3423			cooling-maps {
3424				map0 {
3425					trip = <&gpu_alert0>;
3426					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3427				};
3428			};
3429
3430			trips {
3431				gpu_alert0: trip-point0 {
3432					temperature = <85000>;
3433					hysteresis = <1000>;
3434					type = "passive";
3435				};
3436
3437				trip-point1 {
3438					temperature = <110000>;
3439					hysteresis = <1000>;
3440					type = "critical";
3441				};
3442			};
3443		};
3444	};
3445
3446	timer {
3447		compatible = "arm,armv8-timer";
3448		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3449			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3450			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3451			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3452	};
3453};
3454