1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Richard Acayan. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gcc-sdm845.h> 11#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/phy/phy-qcom-qusb2.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 aliases { }; 29 30 chosen { }; 31 32 clocks { 33 sleep_clk: sleep-clk { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <32764>; 37 }; 38 39 xo_board: xo-board { 40 compatible = "fixed-clock"; 41 #clock-cells = <0>; 42 clock-frequency = <38400000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <2>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "qcom,kryo360"; 53 reg = <0x0 0x0>; 54 enable-method = "psci"; 55 capacity-dmips-mhz = <610>; 56 dynamic-power-coefficient = <203>; 57 qcom,freq-domain = <&cpufreq_hw 0>; 58 operating-points-v2 = <&cpu0_opp_table>; 59 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 60 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 61 power-domains = <&cpu_pd0>; 62 power-domain-names = "psci"; 63 next-level-cache = <&l2_0>; 64 l2_0: l2-cache { 65 compatible = "cache"; 66 next-level-cache = <&l3_0>; 67 cache-level = <2>; 68 cache-unified; 69 l3_0: l3-cache { 70 compatible = "cache"; 71 cache-level = <3>; 72 cache-unified; 73 }; 74 }; 75 }; 76 77 cpu1: cpu@100 { 78 device_type = "cpu"; 79 compatible = "qcom,kryo360"; 80 reg = <0x0 0x100>; 81 enable-method = "psci"; 82 capacity-dmips-mhz = <610>; 83 dynamic-power-coefficient = <203>; 84 qcom,freq-domain = <&cpufreq_hw 0>; 85 operating-points-v2 = <&cpu0_opp_table>; 86 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 87 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 88 power-domains = <&cpu_pd1>; 89 power-domain-names = "psci"; 90 next-level-cache = <&l2_100>; 91 l2_100: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-unified; 95 next-level-cache = <&l3_0>; 96 }; 97 }; 98 99 cpu2: cpu@200 { 100 device_type = "cpu"; 101 compatible = "qcom,kryo360"; 102 reg = <0x0 0x200>; 103 enable-method = "psci"; 104 capacity-dmips-mhz = <610>; 105 dynamic-power-coefficient = <203>; 106 qcom,freq-domain = <&cpufreq_hw 0>; 107 operating-points-v2 = <&cpu0_opp_table>; 108 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 109 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 110 power-domains = <&cpu_pd2>; 111 power-domain-names = "psci"; 112 next-level-cache = <&l2_200>; 113 l2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&l3_0>; 118 }; 119 }; 120 121 cpu3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "qcom,kryo360"; 124 reg = <0x0 0x300>; 125 enable-method = "psci"; 126 capacity-dmips-mhz = <610>; 127 dynamic-power-coefficient = <203>; 128 qcom,freq-domain = <&cpufreq_hw 0>; 129 operating-points-v2 = <&cpu0_opp_table>; 130 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 131 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 132 power-domains = <&cpu_pd3>; 133 power-domain-names = "psci"; 134 next-level-cache = <&l2_300>; 135 l2_300: l2-cache { 136 compatible = "cache"; 137 cache-level = <2>; 138 cache-unified; 139 next-level-cache = <&l3_0>; 140 }; 141 }; 142 143 cpu4: cpu@400 { 144 device_type = "cpu"; 145 compatible = "qcom,kryo360"; 146 reg = <0x0 0x400>; 147 enable-method = "psci"; 148 capacity-dmips-mhz = <610>; 149 dynamic-power-coefficient = <203>; 150 qcom,freq-domain = <&cpufreq_hw 0>; 151 operating-points-v2 = <&cpu0_opp_table>; 152 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 153 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 154 power-domains = <&cpu_pd4>; 155 power-domain-names = "psci"; 156 next-level-cache = <&l2_400>; 157 l2_400: l2-cache { 158 compatible = "cache"; 159 cache-level = <2>; 160 cache-unified; 161 next-level-cache = <&l3_0>; 162 }; 163 }; 164 165 cpu5: cpu@500 { 166 device_type = "cpu"; 167 compatible = "qcom,kryo360"; 168 reg = <0x0 0x500>; 169 enable-method = "psci"; 170 capacity-dmips-mhz = <610>; 171 dynamic-power-coefficient = <203>; 172 qcom,freq-domain = <&cpufreq_hw 0>; 173 operating-points-v2 = <&cpu0_opp_table>; 174 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 175 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 176 power-domains = <&cpu_pd5>; 177 power-domain-names = "psci"; 178 next-level-cache = <&l2_500>; 179 l2_500: l2-cache { 180 compatible = "cache"; 181 cache-level = <2>; 182 cache-unified; 183 next-level-cache = <&l3_0>; 184 }; 185 }; 186 187 cpu6: cpu@600 { 188 device_type = "cpu"; 189 compatible = "qcom,kryo360"; 190 reg = <0x0 0x600>; 191 enable-method = "psci"; 192 capacity-dmips-mhz = <1024>; 193 dynamic-power-coefficient = <393>; 194 qcom,freq-domain = <&cpufreq_hw 1>; 195 operating-points-v2 = <&cpu6_opp_table>; 196 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 197 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 198 power-domains = <&cpu_pd6>; 199 power-domain-names = "psci"; 200 next-level-cache = <&l2_600>; 201 l2_600: l2-cache { 202 compatible = "cache"; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_0>; 206 }; 207 }; 208 209 cpu7: cpu@700 { 210 device_type = "cpu"; 211 compatible = "qcom,kryo360"; 212 reg = <0x0 0x700>; 213 enable-method = "psci"; 214 capacity-dmips-mhz = <1024>; 215 dynamic-power-coefficient = <393>; 216 qcom,freq-domain = <&cpufreq_hw 1>; 217 operating-points-v2 = <&cpu6_opp_table>; 218 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 219 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 220 power-domains = <&cpu_pd7>; 221 power-domain-names = "psci"; 222 next-level-cache = <&l2_700>; 223 l2_700: l2-cache { 224 compatible = "cache"; 225 cache-level = <2>; 226 cache-unified; 227 next-level-cache = <&l3_0>; 228 }; 229 }; 230 231 cpu-map { 232 cluster0 { 233 core0 { 234 cpu = <&cpu0>; 235 }; 236 237 core1 { 238 cpu = <&cpu1>; 239 }; 240 241 core2 { 242 cpu = <&cpu2>; 243 }; 244 245 core3 { 246 cpu = <&cpu3>; 247 }; 248 249 core4 { 250 cpu = <&cpu4>; 251 }; 252 253 core5 { 254 cpu = <&cpu5>; 255 }; 256 257 core6 { 258 cpu = <&cpu6>; 259 }; 260 261 core7 { 262 cpu = <&cpu7>; 263 }; 264 }; 265 }; 266 267 idle-states { 268 entry-method = "psci"; 269 270 little_cpu_sleep_0: cpu-sleep-0-0 { 271 compatible = "arm,idle-state"; 272 idle-state-name = "little-rail-power-collapse"; 273 arm,psci-suspend-param = <0x40000004>; 274 entry-latency-us = <702>; 275 exit-latency-us = <915>; 276 min-residency-us = <1617>; 277 local-timer-stop; 278 }; 279 280 big_cpu_sleep_0: cpu-sleep-1-0 { 281 compatible = "arm,idle-state"; 282 idle-state-name = "big-rail-power-collapse"; 283 arm,psci-suspend-param = <0x40000004>; 284 entry-latency-us = <526>; 285 exit-latency-us = <1854>; 286 min-residency-us = <2380>; 287 local-timer-stop; 288 }; 289 }; 290 291 domain-idle-states { 292 cluster_sleep_0: cluster-sleep-0 { 293 compatible = "domain-idle-state"; 294 arm,psci-suspend-param = <0x4100c244>; 295 entry-latency-us = <3263>; 296 exit-latency-us = <6562>; 297 min-residency-us = <9825>; 298 }; 299 }; 300 }; 301 302 firmware { 303 scm { 304 compatible = "qcom,scm-sdm670", "qcom,scm"; 305 }; 306 }; 307 308 memory@80000000 { 309 device_type = "memory"; 310 /* We expect the bootloader to fill in the size */ 311 reg = <0x0 0x80000000 0x0 0x0>; 312 }; 313 314 cpu0_opp_table: opp-table-cpu0 { 315 compatible = "operating-points-v2"; 316 opp-shared; 317 318 cpu0_opp1: opp-300000000 { 319 opp-hz = /bits/ 64 <300000000>; 320 opp-peak-kBps = <400000 4800000>; 321 }; 322 323 cpu0_opp2: opp-576000000 { 324 opp-hz = /bits/ 64 <576000000>; 325 opp-peak-kBps = <400000 4800000>; 326 }; 327 328 cpu0_opp3: opp-748800000 { 329 opp-hz = /bits/ 64 <748800000>; 330 opp-peak-kBps = <1200000 4800000>; 331 }; 332 333 cpu0_opp4: opp-998400000 { 334 opp-hz = /bits/ 64 <998400000>; 335 opp-peak-kBps = <1804000 8908800>; 336 }; 337 338 cpu0_opp5: opp-1209600000 { 339 opp-hz = /bits/ 64 <1209600000>; 340 opp-peak-kBps = <2188000 8908800>; 341 }; 342 343 cpu0_opp6: opp-1324800000 { 344 opp-hz = /bits/ 64 <1324800000>; 345 opp-peak-kBps = <2188000 13516800>; 346 }; 347 348 cpu0_opp7: opp-1516800000 { 349 opp-hz = /bits/ 64 <1516800000>; 350 opp-peak-kBps = <3072000 15052800>; 351 }; 352 353 cpu0_opp8: opp-1612800000 { 354 opp-hz = /bits/ 64 <1612800000>; 355 opp-peak-kBps = <3072000 22118400>; 356 }; 357 358 cpu0_opp9: opp-1708800000 { 359 opp-hz = /bits/ 64 <1708800000>; 360 opp-peak-kBps = <4068000 23040000>; 361 }; 362 }; 363 364 cpu6_opp_table: opp-table-cpu6 { 365 compatible = "operating-points-v2"; 366 opp-shared; 367 368 cpu6_opp1: opp-300000000 { 369 opp-hz = /bits/ 64 <300000000>; 370 opp-peak-kBps = <400000 4800000>; 371 }; 372 373 cpu6_opp2: opp-652800000 { 374 opp-hz = /bits/ 64 <652800000>; 375 opp-peak-kBps = <400000 4800000>; 376 }; 377 378 cpu6_opp3: opp-825600000 { 379 opp-hz = /bits/ 64 <825600000>; 380 opp-peak-kBps = <1200000 4800000>; 381 }; 382 383 cpu6_opp4: opp-979200000 { 384 opp-hz = /bits/ 64 <979200000>; 385 opp-peak-kBps = <1200000 4800000>; 386 }; 387 388 cpu6_opp5: opp-1132800000 { 389 opp-hz = /bits/ 64 <1132800000>; 390 opp-peak-kBps = <2188000 8908800>; 391 }; 392 393 cpu6_opp6: opp-1363200000 { 394 opp-hz = /bits/ 64 <1363200000>; 395 opp-peak-kBps = <4068000 12902400>; 396 }; 397 398 cpu6_opp7: opp-1536000000 { 399 opp-hz = /bits/ 64 <1536000000>; 400 opp-peak-kBps = <4068000 12902400>; 401 }; 402 403 cpu6_opp8: opp-1747200000 { 404 opp-hz = /bits/ 64 <1747200000>; 405 opp-peak-kBps = <4068000 15052800>; 406 }; 407 408 cpu6_opp9: opp-1843200000 { 409 opp-hz = /bits/ 64 <1843200000>; 410 opp-peak-kBps = <4068000 15052800>; 411 }; 412 413 cpu6_opp10: opp-1996800000 { 414 opp-hz = /bits/ 64 <1996800000>; 415 opp-peak-kBps = <6220000 19046400>; 416 }; 417 }; 418 419 dsi_opp_table: opp-table-dsi { 420 compatible = "operating-points-v2"; 421 422 opp-19200000 { 423 opp-hz = /bits/ 64 <19200000>; 424 required-opps = <&rpmhpd_opp_min_svs>; 425 }; 426 427 opp-180000000 { 428 opp-hz = /bits/ 64 <180000000>; 429 required-opps = <&rpmhpd_opp_low_svs>; 430 }; 431 432 opp-275000000 { 433 opp-hz = /bits/ 64 <275000000>; 434 required-opps = <&rpmhpd_opp_svs>; 435 }; 436 437 opp-358000000 { 438 opp-hz = /bits/ 64 <358000000>; 439 required-opps = <&rpmhpd_opp_svs_l1>; 440 }; 441 }; 442 443 psci { 444 compatible = "arm,psci-1.0"; 445 method = "smc"; 446 447 cpu_pd0: power-domain-cpu0 { 448 #power-domain-cells = <0>; 449 power-domains = <&cluster_pd>; 450 domain-idle-states = <&little_cpu_sleep_0>; 451 }; 452 453 cpu_pd1: power-domain-cpu1 { 454 #power-domain-cells = <0>; 455 power-domains = <&cluster_pd>; 456 domain-idle-states = <&little_cpu_sleep_0>; 457 }; 458 459 cpu_pd2: power-domain-cpu2 { 460 #power-domain-cells = <0>; 461 power-domains = <&cluster_pd>; 462 domain-idle-states = <&little_cpu_sleep_0>; 463 }; 464 465 cpu_pd3: power-domain-cpu3 { 466 #power-domain-cells = <0>; 467 power-domains = <&cluster_pd>; 468 domain-idle-states = <&little_cpu_sleep_0>; 469 }; 470 471 cpu_pd4: power-domain-cpu4 { 472 #power-domain-cells = <0>; 473 power-domains = <&cluster_pd>; 474 domain-idle-states = <&little_cpu_sleep_0>; 475 }; 476 477 cpu_pd5: power-domain-cpu5 { 478 #power-domain-cells = <0>; 479 power-domains = <&cluster_pd>; 480 domain-idle-states = <&little_cpu_sleep_0>; 481 }; 482 483 cpu_pd6: power-domain-cpu6 { 484 #power-domain-cells = <0>; 485 power-domains = <&cluster_pd>; 486 domain-idle-states = <&big_cpu_sleep_0>; 487 }; 488 489 cpu_pd7: power-domain-cpu7 { 490 #power-domain-cells = <0>; 491 power-domains = <&cluster_pd>; 492 domain-idle-states = <&big_cpu_sleep_0>; 493 }; 494 495 cluster_pd: power-domain-cluster { 496 #power-domain-cells = <0>; 497 domain-idle-states = <&cluster_sleep_0>; 498 }; 499 }; 500 501 reserved-memory { 502 #address-cells = <2>; 503 #size-cells = <2>; 504 ranges; 505 506 hyp_mem: hyp-mem@85700000 { 507 reg = <0 0x85700000 0 0x600000>; 508 no-map; 509 }; 510 511 xbl_mem: xbl-mem@85e00000 { 512 reg = <0 0x85e00000 0 0x100000>; 513 no-map; 514 }; 515 516 aop_mem: aop-mem@85fc0000 { 517 reg = <0 0x85fc0000 0 0x20000>; 518 no-map; 519 }; 520 521 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 522 compatible = "qcom,cmd-db"; 523 reg = <0 0x85fe0000 0 0x20000>; 524 no-map; 525 }; 526 527 smem@86000000 { 528 compatible = "qcom,smem"; 529 reg = <0 0x86000000 0 0x200000>; 530 no-map; 531 hwlocks = <&tcsr_mutex 3>; 532 }; 533 534 tz_mem: tz@86200000 { 535 reg = <0 0x86200000 0 0x2d00000>; 536 no-map; 537 }; 538 539 camera_mem: camera-mem@8ab00000 { 540 reg = <0 0x8ab00000 0 0x500000>; 541 no-map; 542 }; 543 544 mpss_region: mpss@8b000000 { 545 reg = <0 0x8b000000 0 0x7e00000>; 546 no-map; 547 }; 548 549 venus_mem: venus@92e00000 { 550 reg = <0 0x92e00000 0 0x500000>; 551 no-map; 552 }; 553 554 wlan_msa_mem: wlan-msa@93300000 { 555 reg = <0 0x93300000 0 0x100000>; 556 no-map; 557 }; 558 559 cdsp_mem: cdsp@93400000 { 560 reg = <0 0x93400000 0 0x800000>; 561 no-map; 562 }; 563 564 mba_region: mba@93c00000 { 565 reg = <0 0x93c00000 0 0x200000>; 566 no-map; 567 }; 568 569 adsp_mem: adsp@93e00000 { 570 reg = <0 0x93e00000 0 0x1e00000>; 571 no-map; 572 }; 573 574 ipa_fw_mem: ipa-fw@95c00000 { 575 reg = <0 0x95c00000 0 0x10000>; 576 no-map; 577 }; 578 579 ipa_gsi_mem: ipa-gsi@95c10000 { 580 reg = <0 0x95c10000 0 0x5000>; 581 no-map; 582 }; 583 584 gpu_mem: gpu@95c15000 { 585 reg = <0 0x95c15000 0 0x2000>; 586 no-map; 587 }; 588 589 spss_mem: spss@97b00000 { 590 reg = <0 0x97b00000 0 0x100000>; 591 no-map; 592 }; 593 594 qseecom_mem: qseecom@9e400000 { 595 reg = <0 0x9e400000 0 0x1400000>; 596 no-map; 597 }; 598 }; 599 600 timer { 601 compatible = "arm,armv8-timer"; 602 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 603 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 604 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 605 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 606 }; 607 608 soc: soc@0 { 609 #address-cells = <2>; 610 #size-cells = <2>; 611 ranges = <0 0 0 0 0x10 0>; 612 dma-ranges = <0 0 0 0 0x10 0>; 613 compatible = "simple-bus"; 614 615 gcc: clock-controller@100000 { 616 compatible = "qcom,gcc-sdm670"; 617 reg = <0 0x00100000 0 0x1f0000>; 618 clocks = <&rpmhcc RPMH_CXO_CLK>, 619 <&rpmhcc RPMH_CXO_CLK_A>, 620 <&sleep_clk>; 621 clock-names = "bi_tcxo", 622 "bi_tcxo_ao", 623 "sleep_clk"; 624 #clock-cells = <1>; 625 #reset-cells = <1>; 626 #power-domain-cells = <1>; 627 }; 628 629 qfprom: qfprom@784000 { 630 compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; 631 reg = <0 0x00784000 0 0x1000>; 632 #address-cells = <1>; 633 #size-cells = <1>; 634 635 gpu_speed_bin: gpu_speed_bin@1a2 { 636 reg = <0x1a2 0x2>; 637 bits = <5 8>; 638 }; 639 640 qusb2_hstx_trim: hstx-trim@1eb { 641 reg = <0x1eb 0x1>; 642 bits = <1 4>; 643 }; 644 }; 645 646 sdhc_1: mmc@7c4000 { 647 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; 648 reg = <0 0x007c4000 0 0x1000>, 649 <0 0x007c5000 0 0x1000>, 650 <0 0x007c8000 0 0x8000>; 651 reg-names = "hc", "cqhci", "ice"; 652 653 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 655 interrupt-names = "hc_irq", "pwr_irq"; 656 657 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 658 <&gcc GCC_SDCC1_APPS_CLK>, 659 <&rpmhcc RPMH_CXO_CLK>, 660 <&gcc GCC_SDCC1_ICE_CORE_CLK>, 661 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 662 clock-names = "iface", "core", "xo", "ice", "bus"; 663 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, 664 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; 665 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 666 operating-points-v2 = <&sdhc1_opp_table>; 667 668 iommus = <&apps_smmu 0x140 0xf>; 669 670 pinctrl-names = "default", "sleep"; 671 pinctrl-0 = <&sdc1_state_on>; 672 pinctrl-1 = <&sdc1_state_off>; 673 power-domains = <&rpmhpd SDM670_CX>; 674 675 bus-width = <8>; 676 non-removable; 677 678 status = "disabled"; 679 680 sdhc1_opp_table: opp-table { 681 compatible = "operating-points-v2"; 682 683 opp-20000000 { 684 opp-hz = /bits/ 64 <20000000>; 685 required-opps = <&rpmhpd_opp_min_svs>; 686 opp-peak-kBps = <80000 80000>; 687 opp-avg-kBps = <52286 80000>; 688 }; 689 690 opp-50000000 { 691 opp-hz = /bits/ 64 <50000000>; 692 required-opps = <&rpmhpd_opp_low_svs>; 693 opp-peak-kBps = <200000 100000>; 694 opp-avg-kBps = <130718 100000>; 695 }; 696 697 opp-100000000 { 698 opp-hz = /bits/ 64 <100000000>; 699 required-opps = <&rpmhpd_opp_svs>; 700 opp-peak-kBps = <200000 130000>; 701 opp-avg-kBps = <130718 130000>; 702 }; 703 704 opp-384000000 { 705 opp-hz = /bits/ 64 <384000000>; 706 required-opps = <&rpmhpd_opp_nom>; 707 opp-peak-kBps = <4096000 4096000>; 708 opp-avg-kBps = <1338562 1338562>; 709 }; 710 }; 711 }; 712 713 gpi_dma0: dma-controller@800000 { 714 #dma-cells = <3>; 715 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 716 reg = <0 0x00800000 0 0x60000>; 717 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 730 dma-channels = <13>; 731 dma-channel-mask = <0xfa>; 732 iommus = <&apps_smmu 0x16 0x0>; 733 status = "disabled"; 734 }; 735 736 qupv3_id_0: geniqup@8c0000 { 737 compatible = "qcom,geni-se-qup"; 738 reg = <0 0x008c0000 0 0x6000>; 739 clock-names = "m-ahb", "s-ahb"; 740 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 741 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 742 iommus = <&apps_smmu 0x3 0x0>; 743 #address-cells = <2>; 744 #size-cells = <2>; 745 ranges; 746 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; 747 interconnect-names = "qup-core"; 748 status = "disabled"; 749 750 i2c0: i2c@880000 { 751 compatible = "qcom,geni-i2c"; 752 reg = <0 0x00880000 0 0x4000>; 753 clock-names = "se"; 754 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&qup_i2c0_default>; 757 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 power-domains = <&rpmhpd SDM670_CX>; 761 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 762 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 763 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 764 interconnect-names = "qup-core", "qup-config", "qup-memory"; 765 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 766 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 767 dma-names = "tx", "rx"; 768 status = "disabled"; 769 }; 770 771 i2c1: i2c@884000 { 772 compatible = "qcom,geni-i2c"; 773 reg = <0 0x00884000 0 0x4000>; 774 clock-names = "se"; 775 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&qup_i2c1_default>; 778 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 power-domains = <&rpmhpd SDM670_CX>; 782 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 783 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 784 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 785 interconnect-names = "qup-core", "qup-config", "qup-memory"; 786 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 787 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 788 dma-names = "tx", "rx"; 789 status = "disabled"; 790 }; 791 792 i2c2: i2c@888000 { 793 compatible = "qcom,geni-i2c"; 794 reg = <0 0x00888000 0 0x4000>; 795 clock-names = "se"; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&qup_i2c2_default>; 799 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 power-domains = <&rpmhpd SDM670_CX>; 803 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 804 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 805 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 806 interconnect-names = "qup-core", "qup-config", "qup-memory"; 807 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 808 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 809 dma-names = "tx", "rx"; 810 status = "disabled"; 811 }; 812 813 i2c3: i2c@88c000 { 814 compatible = "qcom,geni-i2c"; 815 reg = <0 0x0088c000 0 0x4000>; 816 clock-names = "se"; 817 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 818 pinctrl-names = "default"; 819 pinctrl-0 = <&qup_i2c3_default>; 820 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 power-domains = <&rpmhpd SDM670_CX>; 824 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 825 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 826 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 827 interconnect-names = "qup-core", "qup-config", "qup-memory"; 828 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 829 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 830 dma-names = "tx", "rx"; 831 status = "disabled"; 832 }; 833 834 i2c4: i2c@890000 { 835 compatible = "qcom,geni-i2c"; 836 reg = <0 0x00890000 0 0x4000>; 837 clock-names = "se"; 838 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 839 pinctrl-names = "default"; 840 pinctrl-0 = <&qup_i2c4_default>; 841 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 842 #address-cells = <1>; 843 #size-cells = <0>; 844 power-domains = <&rpmhpd SDM670_CX>; 845 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 846 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 847 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 848 interconnect-names = "qup-core", "qup-config", "qup-memory"; 849 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 850 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 851 dma-names = "tx", "rx"; 852 status = "disabled"; 853 }; 854 855 i2c5: i2c@894000 { 856 compatible = "qcom,geni-i2c"; 857 reg = <0 0x00894000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_i2c5_default>; 862 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 863 #address-cells = <1>; 864 #size-cells = <0>; 865 power-domains = <&rpmhpd SDM670_CX>; 866 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 867 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 868 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 869 interconnect-names = "qup-core", "qup-config", "qup-memory"; 870 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 871 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 872 dma-names = "tx", "rx"; 873 status = "disabled"; 874 }; 875 876 i2c6: i2c@898000 { 877 compatible = "qcom,geni-i2c"; 878 reg = <0 0x00898000 0 0x4000>; 879 clock-names = "se"; 880 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 881 pinctrl-names = "default"; 882 pinctrl-0 = <&qup_i2c6_default>; 883 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 884 #address-cells = <1>; 885 #size-cells = <0>; 886 power-domains = <&rpmhpd SDM670_CX>; 887 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 888 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 889 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 890 interconnect-names = "qup-core", "qup-config", "qup-memory"; 891 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 892 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 893 dma-names = "tx", "rx"; 894 status = "disabled"; 895 }; 896 897 i2c7: i2c@89c000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0 0x0089c000 0 0x4000>; 900 clock-names = "se"; 901 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 902 pinctrl-names = "default"; 903 pinctrl-0 = <&qup_i2c7_default>; 904 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 905 #address-cells = <1>; 906 #size-cells = <0>; 907 power-domains = <&rpmhpd SDM670_CX>; 908 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 909 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 910 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 911 interconnect-names = "qup-core", "qup-config", "qup-memory"; 912 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 913 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 914 dma-names = "tx", "rx"; 915 status = "disabled"; 916 }; 917 }; 918 919 gpi_dma1: dma-controller@a00000 { 920 #dma-cells = <3>; 921 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 922 reg = <0 0x00a00000 0 0x60000>; 923 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 936 dma-channels = <13>; 937 dma-channel-mask = <0xfa>; 938 iommus = <&apps_smmu 0x6d6 0x0>; 939 status = "disabled"; 940 }; 941 942 qupv3_id_1: geniqup@ac0000 { 943 compatible = "qcom,geni-se-qup"; 944 reg = <0 0x00ac0000 0 0x6000>; 945 clock-names = "m-ahb", "s-ahb"; 946 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 947 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 948 iommus = <&apps_smmu 0x6c3 0x0>; 949 #address-cells = <2>; 950 #size-cells = <2>; 951 ranges; 952 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; 953 interconnect-names = "qup-core"; 954 status = "disabled"; 955 956 i2c8: i2c@a80000 { 957 compatible = "qcom,geni-i2c"; 958 reg = <0 0x00a80000 0 0x4000>; 959 clock-names = "se"; 960 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 961 pinctrl-names = "default"; 962 pinctrl-0 = <&qup_i2c8_default>; 963 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 power-domains = <&rpmhpd SDM670_CX>; 967 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 968 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 969 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 970 interconnect-names = "qup-core", "qup-config", "qup-memory"; 971 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 972 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 973 dma-names = "tx", "rx"; 974 status = "disabled"; 975 }; 976 977 i2c9: i2c@a84000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00a84000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_i2c9_default>; 984 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 power-domains = <&rpmhpd SDM670_CX>; 988 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 989 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 990 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 991 interconnect-names = "qup-core", "qup-config", "qup-memory"; 992 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 993 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 994 dma-names = "tx", "rx"; 995 status = "disabled"; 996 }; 997 998 i2c10: i2c@a88000 { 999 compatible = "qcom,geni-i2c"; 1000 reg = <0 0x00a88000 0 0x4000>; 1001 clock-names = "se"; 1002 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&qup_i2c10_default>; 1005 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 power-domains = <&rpmhpd SDM670_CX>; 1009 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1010 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1011 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1012 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1013 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1014 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1015 dma-names = "tx", "rx"; 1016 status = "disabled"; 1017 }; 1018 1019 i2c11: i2c@a8c000 { 1020 compatible = "qcom,geni-i2c"; 1021 reg = <0 0x00a8c000 0 0x4000>; 1022 clock-names = "se"; 1023 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&qup_i2c11_default>; 1026 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 power-domains = <&rpmhpd SDM670_CX>; 1030 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1031 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1032 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1033 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1034 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1035 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1036 dma-names = "tx", "rx"; 1037 status = "disabled"; 1038 }; 1039 1040 i2c12: i2c@a90000 { 1041 compatible = "qcom,geni-i2c"; 1042 reg = <0 0x00a90000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_i2c12_default>; 1047 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 power-domains = <&rpmhpd SDM670_CX>; 1051 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1052 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1053 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1054 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1055 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1056 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1057 dma-names = "tx", "rx"; 1058 status = "disabled"; 1059 }; 1060 1061 i2c13: i2c@a94000 { 1062 compatible = "qcom,geni-i2c"; 1063 reg = <0 0x00a94000 0 0x4000>; 1064 clock-names = "se"; 1065 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1066 pinctrl-names = "default"; 1067 pinctrl-0 = <&qup_i2c13_default>; 1068 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 power-domains = <&rpmhpd SDM670_CX>; 1072 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1073 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1074 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1075 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1076 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1077 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1078 dma-names = "tx", "rx"; 1079 status = "disabled"; 1080 }; 1081 1082 i2c14: i2c@a98000 { 1083 compatible = "qcom,geni-i2c"; 1084 reg = <0 0x00a98000 0 0x4000>; 1085 clock-names = "se"; 1086 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1087 pinctrl-names = "default"; 1088 pinctrl-0 = <&qup_i2c14_default>; 1089 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 power-domains = <&rpmhpd SDM670_CX>; 1093 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1094 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1095 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1096 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1097 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1098 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1099 dma-names = "tx", "rx"; 1100 status = "disabled"; 1101 }; 1102 1103 i2c15: i2c@a9c000 { 1104 compatible = "qcom,geni-i2c"; 1105 reg = <0 0x00a9c000 0 0x4000>; 1106 clock-names = "se"; 1107 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1108 pinctrl-names = "default"; 1109 pinctrl-0 = <&qup_i2c15_default>; 1110 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 power-domains = <&rpmhpd SDM670_CX>; 1114 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1115 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1116 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1117 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1118 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1119 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1120 dma-names = "tx", "rx"; 1121 status = "disabled"; 1122 }; 1123 }; 1124 1125 mem_noc: interconnect@1380000 { 1126 compatible = "qcom,sdm670-mem-noc"; 1127 reg = <0 0x01380000 0 0x27200>; 1128 #interconnect-cells = <2>; 1129 qcom,bcm-voters = <&apps_bcm_voter>; 1130 }; 1131 1132 dc_noc: interconnect@14e0000 { 1133 compatible = "qcom,sdm670-dc-noc"; 1134 reg = <0 0x014e0000 0 0x400>; 1135 #interconnect-cells = <2>; 1136 qcom,bcm-voters = <&apps_bcm_voter>; 1137 }; 1138 1139 config_noc: interconnect@1500000 { 1140 compatible = "qcom,sdm670-config-noc"; 1141 reg = <0 0x01500000 0 0x5080>; 1142 #interconnect-cells = <2>; 1143 qcom,bcm-voters = <&apps_bcm_voter>; 1144 }; 1145 1146 system_noc: interconnect@1620000 { 1147 compatible = "qcom,sdm670-system-noc"; 1148 reg = <0 0x01620000 0 0x18080>; 1149 #interconnect-cells = <2>; 1150 qcom,bcm-voters = <&apps_bcm_voter>; 1151 }; 1152 1153 aggre1_noc: interconnect@16e0000 { 1154 compatible = "qcom,sdm670-aggre1-noc"; 1155 reg = <0 0x016e0000 0 0x15080>; 1156 #interconnect-cells = <2>; 1157 qcom,bcm-voters = <&apps_bcm_voter>; 1158 }; 1159 1160 aggre2_noc: interconnect@1700000 { 1161 compatible = "qcom,sdm670-aggre2-noc"; 1162 reg = <0 0x01700000 0 0x1f300>; 1163 #interconnect-cells = <2>; 1164 qcom,bcm-voters = <&apps_bcm_voter>; 1165 }; 1166 1167 mmss_noc: interconnect@1740000 { 1168 compatible = "qcom,sdm670-mmss-noc"; 1169 reg = <0 0x01740000 0 0x1c100>; 1170 #interconnect-cells = <2>; 1171 qcom,bcm-voters = <&apps_bcm_voter>; 1172 }; 1173 1174 tcsr_mutex: hwlock@1f40000 { 1175 compatible = "qcom,tcsr-mutex"; 1176 reg = <0 0x01f40000 0 0x20000>; 1177 #hwlock-cells = <1>; 1178 }; 1179 1180 tlmm: pinctrl@3400000 { 1181 compatible = "qcom,sdm670-tlmm"; 1182 reg = <0 0x03400000 0 0xc00000>; 1183 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1184 gpio-controller; 1185 #gpio-cells = <2>; 1186 interrupt-controller; 1187 #interrupt-cells = <2>; 1188 gpio-ranges = <&tlmm 0 0 151>; 1189 wakeup-parent = <&pdc>; 1190 1191 qup_i2c0_default: qup-i2c0-default-state { 1192 pins = "gpio0", "gpio1"; 1193 function = "qup0"; 1194 }; 1195 1196 qup_i2c1_default: qup-i2c1-default-state { 1197 pins = "gpio17", "gpio18"; 1198 function = "qup1"; 1199 }; 1200 1201 qup_i2c2_default: qup-i2c2-default-state { 1202 pins = "gpio27", "gpio28"; 1203 function = "qup2"; 1204 }; 1205 1206 qup_i2c3_default: qup-i2c3-default-state { 1207 pins = "gpio41", "gpio42"; 1208 function = "qup3"; 1209 }; 1210 1211 qup_i2c4_default: qup-i2c4-default-state { 1212 pins = "gpio89", "gpio90"; 1213 function = "qup4"; 1214 }; 1215 1216 qup_i2c5_default: qup-i2c5-default-state { 1217 pins = "gpio85", "gpio86"; 1218 function = "qup5"; 1219 }; 1220 1221 qup_i2c6_default: qup-i2c6-default-state { 1222 pins = "gpio45", "gpio46"; 1223 function = "qup6"; 1224 }; 1225 1226 qup_i2c7_default: qup-i2c7-default-state { 1227 pins = "gpio93", "gpio94"; 1228 function = "qup7"; 1229 }; 1230 1231 qup_i2c8_default: qup-i2c8-default-state { 1232 pins = "gpio65", "gpio66"; 1233 function = "qup8"; 1234 }; 1235 1236 qup_i2c9_default: qup-i2c9-default-state { 1237 pins = "gpio6", "gpio7"; 1238 function = "qup9"; 1239 }; 1240 1241 qup_i2c10_default: qup-i2c10-default-state { 1242 pins = "gpio55", "gpio56"; 1243 function = "qup10"; 1244 }; 1245 1246 qup_i2c11_default: qup-i2c11-default-state { 1247 pins = "gpio31", "gpio32"; 1248 function = "qup11"; 1249 }; 1250 1251 qup_i2c12_default: qup-i2c12-default-state { 1252 pins = "gpio49", "gpio50"; 1253 function = "qup12"; 1254 }; 1255 1256 qup_i2c13_default: qup-i2c13-default-state { 1257 pins = "gpio105", "gpio106"; 1258 function = "qup13"; 1259 }; 1260 1261 qup_i2c14_default: qup-i2c14-default-state { 1262 pins = "gpio33", "gpio34"; 1263 function = "qup14"; 1264 }; 1265 1266 qup_i2c15_default: qup-i2c15-default-state { 1267 pins = "gpio81", "gpio82"; 1268 function = "qup15"; 1269 }; 1270 1271 sdc1_state_on: sdc1-on-state { 1272 clk-pins { 1273 pins = "sdc1_clk"; 1274 bias-disable; 1275 drive-strength = <16>; 1276 }; 1277 1278 cmd-pins { 1279 pins = "sdc1_cmd"; 1280 bias-pull-up; 1281 drive-strength = <10>; 1282 }; 1283 1284 data-pins { 1285 pins = "sdc1_data"; 1286 bias-pull-up; 1287 drive-strength = <10>; 1288 }; 1289 1290 rclk-pins { 1291 pins = "sdc1_rclk"; 1292 bias-pull-down; 1293 }; 1294 }; 1295 1296 sdc1_state_off: sdc1-off-state { 1297 clk-pins { 1298 pins = "sdc1_clk"; 1299 bias-disable; 1300 drive-strength = <2>; 1301 }; 1302 1303 cmd-pins { 1304 pins = "sdc1_cmd"; 1305 bias-pull-up; 1306 drive-strength = <2>; 1307 }; 1308 1309 data-pins { 1310 pins = "sdc1_data"; 1311 bias-pull-up; 1312 drive-strength = <2>; 1313 }; 1314 1315 rclk-pins { 1316 pins = "sdc1_rclk"; 1317 bias-pull-down; 1318 }; 1319 }; 1320 }; 1321 1322 gpu: gpu@5000000 { 1323 compatible = "qcom,adreno-615.0", "qcom,adreno"; 1324 1325 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>; 1326 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 1327 1328 /* 1329 * Look ma, no clocks! The GPU clocks and power are 1330 * controlled entirely by the GMU 1331 */ 1332 1333 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1334 1335 iommus = <&adreno_smmu 0>; 1336 1337 operating-points-v2 = <&gpu_opp_table>; 1338 1339 qcom,gmu = <&gmu>; 1340 1341 interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>; 1342 interconnect-names = "gfx-mem"; 1343 1344 nvmem-cells = <&gpu_speed_bin>; 1345 nvmem-cell-names = "speed_bin"; 1346 1347 status = "disabled"; 1348 1349 gpu_opp_table: opp-table { 1350 compatible = "operating-points-v2"; 1351 1352 opp-780000000 { 1353 opp-hz = /bits/ 64 <780000000>; 1354 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1355 opp-peak-kBps = <7216000>; 1356 opp-supported-hw = <0x8>; 1357 }; 1358 1359 opp-750000000 { 1360 opp-hz = /bits/ 64 <750000000>; 1361 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1362 opp-peak-kBps = <7216000>; 1363 opp-supported-hw = <0x8>; 1364 }; 1365 1366 opp-700000000 { 1367 opp-hz = /bits/ 64 <700000000>; 1368 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1369 opp-peak-kBps = <7216000>; 1370 opp-supported-hw = <0x4>; 1371 }; 1372 1373 opp-650000000 { 1374 opp-hz = /bits/ 64 <650000000>; 1375 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1376 opp-peak-kBps = <7216000>; 1377 opp-supported-hw = <0xc>; 1378 }; 1379 1380 opp-565000000 { 1381 opp-hz = /bits/ 64 <565000000>; 1382 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1383 opp-peak-kBps = <7216000>; 1384 opp-supported-hw = <0xc>; 1385 }; 1386 1387 opp-504000000 { 1388 opp-hz = /bits/ 64 <504000000>; 1389 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1390 opp-peak-kBps = <7216000>; 1391 opp-supported-hw = <0x2>; 1392 }; 1393 1394 opp-430000000 { 1395 opp-hz = /bits/ 64 <430000000>; 1396 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1397 opp-peak-kBps = <7216000>; 1398 opp-supported-hw = <0xf>; 1399 }; 1400 1401 opp-355000000 { 1402 opp-hz = /bits/ 64 <355000000>; 1403 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1404 opp-peak-kBps = <6220000>; 1405 opp-supported-hw = <0xf>; 1406 }; 1407 1408 opp-267000000 { 1409 opp-hz = /bits/ 64 <267000000>; 1410 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1411 opp-peak-kBps = <4068000>; 1412 opp-supported-hw = <0xf>; 1413 }; 1414 1415 opp-180000000 { 1416 opp-hz = /bits/ 64 <180000000>; 1417 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1418 opp-peak-kBps = <1804000>; 1419 opp-supported-hw = <0xf>; 1420 }; 1421 }; 1422 }; 1423 1424 adreno_smmu: iommu@5040000 { 1425 compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1426 reg = <0 0x05040000 0 0x10000>; 1427 #iommu-cells = <1>; 1428 #global-interrupts = <2>; 1429 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1431 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1432 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1433 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1434 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1435 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1436 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1437 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1438 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1439 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1440 <&gcc GCC_GPU_CFG_AHB_CLK>; 1441 clock-names = "bus", "iface"; 1442 1443 power-domains = <&gpucc GPU_CX_GDSC>; 1444 }; 1445 1446 gmu: gmu@506a000 { 1447 compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu"; 1448 1449 reg = <0 0x0506a000 0 0x30000>, 1450 <0 0x0b280000 0 0x10000>, 1451 <0 0x0b480000 0 0x10000>; 1452 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1453 1454 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1456 interrupt-names = "hfi", "gmu"; 1457 1458 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1459 <&gpucc GPU_CC_CXO_CLK>, 1460 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1461 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1462 clock-names = "gmu", "cxo", "axi", "memnoc"; 1463 1464 power-domains = <&gpucc GPU_CX_GDSC>, 1465 <&gpucc GPU_GX_GDSC>; 1466 power-domain-names = "cx", "gx"; 1467 1468 iommus = <&adreno_smmu 5>; 1469 1470 operating-points-v2 = <&gmu_opp_table>; 1471 1472 gmu_opp_table: opp-table { 1473 compatible = "operating-points-v2"; 1474 1475 opp-200000000 { 1476 opp-hz = /bits/ 64 <200000000>; 1477 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1478 }; 1479 }; 1480 }; 1481 1482 gpucc: clock-controller@5090000 { 1483 compatible = "qcom,sdm845-gpucc"; 1484 reg = <0 0x05090000 0 0x9000>; 1485 #clock-cells = <1>; 1486 #reset-cells = <1>; 1487 #power-domain-cells = <1>; 1488 clocks = <&rpmhcc RPMH_CXO_CLK>, 1489 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1490 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1491 clock-names = "bi_tcxo", 1492 "gcc_gpu_gpll0_clk_src", 1493 "gcc_gpu_gpll0_div_clk_src"; 1494 }; 1495 1496 usb_1_hsphy: phy@88e2000 { 1497 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; 1498 reg = <0 0x088e2000 0 0x400>; 1499 #phy-cells = <0>; 1500 1501 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1502 <&rpmhcc RPMH_CXO_CLK>; 1503 clock-names = "cfg_ahb", "ref"; 1504 1505 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1506 1507 nvmem-cells = <&qusb2_hstx_trim>; 1508 1509 status = "disabled"; 1510 }; 1511 1512 usb_1: usb@a6f8800 { 1513 compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; 1514 reg = <0 0x0a6f8800 0 0x400>; 1515 #address-cells = <2>; 1516 #size-cells = <2>; 1517 ranges; 1518 dma-ranges; 1519 1520 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1521 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1522 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1523 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1524 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1525 clock-names = "cfg_noc", 1526 "core", 1527 "iface", 1528 "sleep", 1529 "mock_utmi"; 1530 1531 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1532 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1533 assigned-clock-rates = <19200000>, <150000000>; 1534 1535 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1536 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1537 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 1538 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 1539 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 1540 interrupt-names = "pwr_event", 1541 "hs_phy_irq", 1542 "dp_hs_phy_irq", 1543 "dm_hs_phy_irq", 1544 "ss_phy_irq"; 1545 1546 power-domains = <&gcc USB30_PRIM_GDSC>; 1547 1548 resets = <&gcc GCC_USB30_PRIM_BCR>; 1549 1550 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, 1551 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1552 interconnect-names = "usb-ddr", "apps-usb"; 1553 1554 status = "disabled"; 1555 1556 usb_1_dwc3: usb@a600000 { 1557 compatible = "snps,dwc3"; 1558 reg = <0 0x0a600000 0 0xcd00>; 1559 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1560 iommus = <&apps_smmu 0x740 0>; 1561 snps,dis_u2_susphy_quirk; 1562 snps,dis_enblslpm_quirk; 1563 phys = <&usb_1_hsphy>; 1564 phy-names = "usb2-phy"; 1565 }; 1566 }; 1567 1568 pdc: interrupt-controller@b220000 { 1569 compatible = "qcom,sdm670-pdc", "qcom,pdc"; 1570 reg = <0 0x0b220000 0 0x30000>; 1571 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, 1572 <54 534 24>, <79 559 15>, <94 609 15>, 1573 <115 630 7>; 1574 #interrupt-cells = <2>; 1575 interrupt-parent = <&intc>; 1576 interrupt-controller; 1577 }; 1578 1579 spmi_bus: spmi@c440000 { 1580 compatible = "qcom,spmi-pmic-arb"; 1581 reg = <0 0x0c440000 0 0x1100>, 1582 <0 0x0c600000 0 0x2000000>, 1583 <0 0x0e600000 0 0x100000>, 1584 <0 0x0e700000 0 0xa0000>, 1585 <0 0x0c40a000 0 0x26000>; 1586 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1587 interrupt-names = "periph_irq"; 1588 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1589 qcom,ee = <0>; 1590 qcom,channel = <0>; 1591 #address-cells = <2>; 1592 #size-cells = <0>; 1593 interrupt-controller; 1594 #interrupt-cells = <4>; 1595 }; 1596 1597 camcc: clock-controller@ad00000 { 1598 compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc"; 1599 reg = <0 0x0ad00000 0 0x10000>; 1600 clocks = <&rpmhcc RPMH_CXO_CLK>; 1601 clock-names = "bi_tcxo"; 1602 #clock-cells = <1>; 1603 #reset-cells = <1>; 1604 #power-domain-cells = <1>; 1605 }; 1606 1607 mdss: display-subsystem@ae00000 { 1608 compatible = "qcom,sdm670-mdss"; 1609 reg = <0 0x0ae00000 0 0x1000>; 1610 reg-names = "mdss"; 1611 1612 power-domains = <&dispcc MDSS_GDSC>; 1613 1614 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1615 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1616 clock-names = "iface", "core"; 1617 1618 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1619 interrupt-controller; 1620 #interrupt-cells = <1>; 1621 1622 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, 1623 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; 1624 interconnect-names = "mdp0-mem", "mdp1-mem"; 1625 1626 iommus = <&apps_smmu 0x880 0x8>, 1627 <&apps_smmu 0xc80 0x8>; 1628 1629 #address-cells = <2>; 1630 #size-cells = <2>; 1631 ranges; 1632 1633 status = "disabled"; 1634 1635 mdss_mdp: display-controller@ae01000 { 1636 compatible = "qcom,sdm670-dpu"; 1637 reg = <0 0x0ae01000 0 0x8f000>, 1638 <0 0x0aeb0000 0 0x2008>; 1639 reg-names = "mdp", "vbif"; 1640 1641 clocks = <&gcc GCC_DISP_AXI_CLK>, 1642 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1643 <&dispcc DISP_CC_MDSS_AXI_CLK>, 1644 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1645 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1646 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 1647 1648 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1649 assigned-clock-rates = <19200000>; 1650 operating-points-v2 = <&mdp_opp_table>; 1651 power-domains = <&rpmhpd SDM670_CX>; 1652 1653 interrupt-parent = <&mdss>; 1654 interrupts = <0>; 1655 1656 ports { 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 1660 port@0 { 1661 reg = <0>; 1662 dpu_intf0_out: endpoint { 1663 remote-endpoint = <&mdss_dsi0_in>; 1664 }; 1665 }; 1666 1667 port@1 { 1668 reg = <1>; 1669 dpu_intf1_out: endpoint { 1670 remote-endpoint = <&mdss_dsi1_in>; 1671 }; 1672 }; 1673 }; 1674 1675 mdp_opp_table: opp-table { 1676 compatible = "operating-points-v2"; 1677 1678 opp-19200000 { 1679 opp-hz = /bits/ 64 <19200000>; 1680 required-opps = <&rpmhpd_opp_min_svs>; 1681 }; 1682 1683 opp-171428571 { 1684 opp-hz = /bits/ 64 <171428571>; 1685 required-opps = <&rpmhpd_opp_low_svs>; 1686 }; 1687 1688 opp-358000000 { 1689 opp-hz = /bits/ 64 <358000000>; 1690 required-opps = <&rpmhpd_opp_svs_l1>; 1691 }; 1692 1693 opp-430000000 { 1694 opp-hz = /bits/ 64 <430000000>; 1695 required-opps = <&rpmhpd_opp_nom>; 1696 }; 1697 }; 1698 }; 1699 1700 mdss_dsi0: dsi@ae94000 { 1701 compatible = "qcom,sdm670-dsi-ctrl", 1702 "qcom,mdss-dsi-ctrl"; 1703 reg = <0 0x0ae94000 0 0x400>; 1704 reg-names = "dsi_ctrl"; 1705 1706 interrupt-parent = <&mdss>; 1707 interrupts = <4>; 1708 1709 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1710 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1711 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1712 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1713 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1714 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1715 clock-names = "byte", 1716 "byte_intf", 1717 "pixel", 1718 "core", 1719 "iface", 1720 "bus"; 1721 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1722 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1723 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1724 <&mdss_dsi0_phy 1>; 1725 1726 operating-points-v2 = <&dsi_opp_table>; 1727 power-domains = <&rpmhpd SDM670_CX>; 1728 1729 phys = <&mdss_dsi0_phy>; 1730 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 1734 status = "disabled"; 1735 1736 ports { 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 1740 port@0 { 1741 reg = <0>; 1742 mdss_dsi0_in: endpoint { 1743 remote-endpoint = <&dpu_intf0_out>; 1744 }; 1745 }; 1746 1747 port@1 { 1748 reg = <1>; 1749 mdss_dsi0_out: endpoint { 1750 }; 1751 }; 1752 }; 1753 }; 1754 1755 mdss_dsi0_phy: phy@ae94400 { 1756 compatible = "qcom,dsi-phy-10nm"; 1757 reg = <0 0x0ae94400 0 0x200>, 1758 <0 0x0ae94600 0 0x280>, 1759 <0 0x0ae94a00 0 0x1e0>; 1760 reg-names = "dsi_phy", 1761 "dsi_phy_lane", 1762 "dsi_pll"; 1763 1764 #clock-cells = <1>; 1765 #phy-cells = <0>; 1766 1767 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1768 <&rpmhcc RPMH_CXO_CLK>; 1769 clock-names = "iface", "ref"; 1770 1771 status = "disabled"; 1772 }; 1773 1774 mdss_dsi1: dsi@ae96000 { 1775 compatible = "qcom,sdm670-dsi-ctrl", 1776 "qcom,mdss-dsi-ctrl"; 1777 reg = <0 0x0ae96000 0 0x400>; 1778 reg-names = "dsi_ctrl"; 1779 1780 interrupt-parent = <&mdss>; 1781 interrupts = <5>; 1782 1783 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 1784 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 1785 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 1786 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 1787 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1788 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1789 clock-names = "byte", 1790 "byte_intf", 1791 "pixel", 1792 "core", 1793 "iface", 1794 "bus"; 1795 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 1796 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 1797 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; 1798 1799 operating-points-v2 = <&dsi_opp_table>; 1800 power-domains = <&rpmhpd SDM670_CX>; 1801 1802 phys = <&mdss_dsi1_phy>; 1803 1804 #address-cells = <1>; 1805 #size-cells = <0>; 1806 1807 status = "disabled"; 1808 1809 ports { 1810 #address-cells = <1>; 1811 #size-cells = <0>; 1812 1813 port@0 { 1814 reg = <0>; 1815 mdss_dsi1_in: endpoint { 1816 remote-endpoint = <&dpu_intf1_out>; 1817 }; 1818 }; 1819 1820 port@1 { 1821 reg = <1>; 1822 mdss_dsi1_out: endpoint { 1823 }; 1824 }; 1825 }; 1826 }; 1827 1828 mdss_dsi1_phy: phy@ae96400 { 1829 compatible = "qcom,dsi-phy-10nm"; 1830 reg = <0 0x0ae96400 0 0x200>, 1831 <0 0x0ae96600 0 0x280>, 1832 <0 0x0ae96a00 0 0x10e>; 1833 reg-names = "dsi_phy", 1834 "dsi_phy_lane", 1835 "dsi_pll"; 1836 1837 #clock-cells = <1>; 1838 #phy-cells = <0>; 1839 1840 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1841 <&rpmhcc RPMH_CXO_CLK>; 1842 clock-names = "iface", "ref"; 1843 1844 status = "disabled"; 1845 }; 1846 }; 1847 1848 dispcc: clock-controller@af00000 { 1849 compatible = "qcom,sdm845-dispcc"; 1850 reg = <0 0x0af00000 0 0x10000>; 1851 clocks = <&rpmhcc RPMH_CXO_CLK>, 1852 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 1853 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 1854 <&mdss_dsi0_phy 0>, 1855 <&mdss_dsi0_phy 1>, 1856 <&mdss_dsi1_phy 0>, 1857 <&mdss_dsi1_phy 1>, 1858 <0>, 1859 <0>; 1860 clock-names = "bi_tcxo", 1861 "gcc_disp_gpll0_clk_src", 1862 "gcc_disp_gpll0_div_clk_src", 1863 "dsi0_phy_pll_out_byteclk", 1864 "dsi0_phy_pll_out_dsiclk", 1865 "dsi1_phy_pll_out_byteclk", 1866 "dsi1_phy_pll_out_dsiclk", 1867 "dp_link_clk_divsel_ten", 1868 "dp_vco_divided_clk_src_mux"; 1869 #clock-cells = <1>; 1870 #reset-cells = <1>; 1871 #power-domain-cells = <1>; 1872 }; 1873 1874 apps_smmu: iommu@15000000 { 1875 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1876 reg = <0 0x15000000 0 0x80000>; 1877 #iommu-cells = <2>; 1878 #global-interrupts = <1>; 1879 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1880 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1881 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1882 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1883 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1884 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1885 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1886 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1908 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1909 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1910 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1911 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1912 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1913 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1914 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1915 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1916 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1917 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1918 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1919 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1920 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1921 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1922 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1923 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1924 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1925 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1926 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1927 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1928 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1929 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1930 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1931 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1932 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1933 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1934 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1935 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1936 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1937 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1938 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1939 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1940 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1941 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1942 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1943 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1944 dma-coherent; 1945 }; 1946 1947 gladiator_noc: interconnect@17900000 { 1948 compatible = "qcom,sdm670-gladiator-noc"; 1949 reg = <0 0x17900000 0 0xd080>; 1950 #interconnect-cells = <2>; 1951 qcom,bcm-voters = <&apps_bcm_voter>; 1952 }; 1953 1954 apps_rsc: rsc@179c0000 { 1955 compatible = "qcom,rpmh-rsc"; 1956 reg = <0 0x179c0000 0 0x10000>, 1957 <0 0x179d0000 0 0x10000>, 1958 <0 0x179e0000 0 0x10000>; 1959 reg-names = "drv-0", "drv-1", "drv-2"; 1960 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1961 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1962 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1963 label = "apps_rsc"; 1964 qcom,tcs-offset = <0xd00>; 1965 qcom,drv-id = <2>; 1966 qcom,tcs-config = <ACTIVE_TCS 2>, 1967 <SLEEP_TCS 3>, 1968 <WAKE_TCS 3>, 1969 <CONTROL_TCS 1>; 1970 power-domains = <&cluster_pd>; 1971 1972 apps_bcm_voter: bcm-voter { 1973 compatible = "qcom,bcm-voter"; 1974 }; 1975 1976 rpmhcc: clock-controller { 1977 compatible = "qcom,sdm670-rpmh-clk"; 1978 #clock-cells = <1>; 1979 clock-names = "xo"; 1980 clocks = <&xo_board>; 1981 }; 1982 1983 rpmhpd: power-controller { 1984 compatible = "qcom,sdm670-rpmhpd"; 1985 #power-domain-cells = <1>; 1986 operating-points-v2 = <&rpmhpd_opp_table>; 1987 1988 rpmhpd_opp_table: opp-table { 1989 compatible = "operating-points-v2"; 1990 1991 rpmhpd_opp_ret: opp1 { 1992 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1993 }; 1994 1995 rpmhpd_opp_min_svs: opp2 { 1996 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1997 }; 1998 1999 rpmhpd_opp_low_svs: opp3 { 2000 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2001 }; 2002 2003 rpmhpd_opp_svs: opp4 { 2004 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2005 }; 2006 2007 rpmhpd_opp_svs_l1: opp5 { 2008 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2009 }; 2010 2011 rpmhpd_opp_nom: opp6 { 2012 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2013 }; 2014 2015 rpmhpd_opp_nom_l1: opp7 { 2016 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2017 }; 2018 2019 rpmhpd_opp_nom_l2: opp8 { 2020 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2021 }; 2022 2023 rpmhpd_opp_turbo: opp9 { 2024 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2025 }; 2026 2027 rpmhpd_opp_turbo_l1: opp10 { 2028 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2029 }; 2030 }; 2031 }; 2032 }; 2033 2034 intc: interrupt-controller@17a00000 { 2035 compatible = "arm,gic-v3"; 2036 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2037 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2038 interrupt-controller; 2039 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2040 #interrupt-cells = <3>; 2041 }; 2042 2043 osm_l3: interconnect@17d41000 { 2044 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; 2045 reg = <0 0x17d41000 0 0x1400>; 2046 2047 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2048 clock-names = "xo", "alternate"; 2049 2050 #interconnect-cells = <1>; 2051 }; 2052 2053 cpufreq_hw: cpufreq@17d43000 { 2054 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw"; 2055 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 2056 reg-names = "freq-domain0", "freq-domain1"; 2057 2058 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2059 clock-names = "xo", "alternate"; 2060 2061 #freq-domain-cells = <1>; 2062 }; 2063 }; 2064}; 2065