1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2020, Konrad Dybcio <[email protected]> 4 * Copyright (c) 2020, AngeloGioacchino Del Regno <[email protected]> 5 */ 6 7#include <dt-bindings/clock/qcom,gcc-sdm660.h> 8#include <dt-bindings/clock/qcom,gpucc-sdm660.h> 9#include <dt-bindings/clock/qcom,mmcc-sdm660.h> 10#include <dt-bindings/clock/qcom,rpmcc.h> 11#include <dt-bindings/firmware/qcom,scm.h> 12#include <dt-bindings/interconnect/qcom,sdm660.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/soc/qcom,apr.h> 18 19/ { 20 interrupt-parent = <&intc>; 21 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 mmc1 = &sdhc_1; 27 mmc2 = &sdhc_2; 28 }; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 clock-frequency = <19200000>; 37 clock-output-names = "xo_board"; 38 }; 39 40 sleep_clk: sleep-clk { 41 compatible = "fixed-clock"; 42 #clock-cells = <0>; 43 clock-frequency = <32764>; 44 clock-output-names = "sleep_clk"; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@100 { 53 device_type = "cpu"; 54 compatible = "arm,cortex-a53"; 55 reg = <0x0 0x100>; 56 enable-method = "psci"; 57 cpu-idle-states = <&perf_cpu_sleep_0 58 &perf_cpu_sleep_1 59 &perf_cluster_sleep_0 60 &perf_cluster_sleep_1 61 &perf_cluster_sleep_2>; 62 capacity-dmips-mhz = <1126>; 63 #cooling-cells = <2>; 64 next-level-cache = <&l2_1>; 65 l2_1: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 }; 70 }; 71 72 cpu1: cpu@101 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a53"; 75 reg = <0x0 0x101>; 76 enable-method = "psci"; 77 cpu-idle-states = <&perf_cpu_sleep_0 78 &perf_cpu_sleep_1 79 &perf_cluster_sleep_0 80 &perf_cluster_sleep_1 81 &perf_cluster_sleep_2>; 82 capacity-dmips-mhz = <1126>; 83 #cooling-cells = <2>; 84 next-level-cache = <&l2_1>; 85 }; 86 87 cpu2: cpu@102 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x102>; 91 enable-method = "psci"; 92 cpu-idle-states = <&perf_cpu_sleep_0 93 &perf_cpu_sleep_1 94 &perf_cluster_sleep_0 95 &perf_cluster_sleep_1 96 &perf_cluster_sleep_2>; 97 capacity-dmips-mhz = <1126>; 98 #cooling-cells = <2>; 99 next-level-cache = <&l2_1>; 100 }; 101 102 cpu3: cpu@103 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53"; 105 reg = <0x0 0x103>; 106 enable-method = "psci"; 107 cpu-idle-states = <&perf_cpu_sleep_0 108 &perf_cpu_sleep_1 109 &perf_cluster_sleep_0 110 &perf_cluster_sleep_1 111 &perf_cluster_sleep_2>; 112 capacity-dmips-mhz = <1126>; 113 #cooling-cells = <2>; 114 next-level-cache = <&l2_1>; 115 }; 116 117 cpu4: cpu@0 { 118 device_type = "cpu"; 119 compatible = "arm,cortex-a53"; 120 reg = <0x0 0x0>; 121 enable-method = "psci"; 122 cpu-idle-states = <&pwr_cpu_sleep_0 123 &pwr_cpu_sleep_1 124 &pwr_cluster_sleep_0 125 &pwr_cluster_sleep_1 126 &pwr_cluster_sleep_2>; 127 capacity-dmips-mhz = <1024>; 128 #cooling-cells = <2>; 129 next-level-cache = <&l2_0>; 130 l2_0: l2-cache { 131 compatible = "cache"; 132 cache-level = <2>; 133 cache-unified; 134 }; 135 }; 136 137 cpu5: cpu@1 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a53"; 140 reg = <0x0 0x1>; 141 enable-method = "psci"; 142 cpu-idle-states = <&pwr_cpu_sleep_0 143 &pwr_cpu_sleep_1 144 &pwr_cluster_sleep_0 145 &pwr_cluster_sleep_1 146 &pwr_cluster_sleep_2>; 147 capacity-dmips-mhz = <1024>; 148 #cooling-cells = <2>; 149 next-level-cache = <&l2_0>; 150 }; 151 152 cpu6: cpu@2 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a53"; 155 reg = <0x0 0x2>; 156 enable-method = "psci"; 157 cpu-idle-states = <&pwr_cpu_sleep_0 158 &pwr_cpu_sleep_1 159 &pwr_cluster_sleep_0 160 &pwr_cluster_sleep_1 161 &pwr_cluster_sleep_2>; 162 capacity-dmips-mhz = <1024>; 163 #cooling-cells = <2>; 164 next-level-cache = <&l2_0>; 165 }; 166 167 cpu7: cpu@3 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a53"; 170 reg = <0x0 0x3>; 171 enable-method = "psci"; 172 cpu-idle-states = <&pwr_cpu_sleep_0 173 &pwr_cpu_sleep_1 174 &pwr_cluster_sleep_0 175 &pwr_cluster_sleep_1 176 &pwr_cluster_sleep_2>; 177 capacity-dmips-mhz = <1024>; 178 #cooling-cells = <2>; 179 next-level-cache = <&l2_0>; 180 }; 181 182 cpu-map { 183 cluster0 { 184 core0 { 185 cpu = <&cpu4>; 186 }; 187 188 core1 { 189 cpu = <&cpu5>; 190 }; 191 192 core2 { 193 cpu = <&cpu6>; 194 }; 195 196 core3 { 197 cpu = <&cpu7>; 198 }; 199 }; 200 201 cluster1 { 202 core0 { 203 cpu = <&cpu0>; 204 }; 205 206 core1 { 207 cpu = <&cpu1>; 208 }; 209 210 core2 { 211 cpu = <&cpu2>; 212 }; 213 214 core3 { 215 cpu = <&cpu3>; 216 }; 217 }; 218 }; 219 220 idle-states { 221 entry-method = "psci"; 222 223 pwr_cpu_sleep_0: cpu-sleep-0-0 { 224 compatible = "arm,idle-state"; 225 idle-state-name = "pwr-retention"; 226 arm,psci-suspend-param = <0x40000002>; 227 entry-latency-us = <338>; 228 exit-latency-us = <423>; 229 min-residency-us = <200>; 230 }; 231 232 pwr_cpu_sleep_1: cpu-sleep-0-1 { 233 compatible = "arm,idle-state"; 234 idle-state-name = "pwr-power-collapse"; 235 arm,psci-suspend-param = <0x40000003>; 236 entry-latency-us = <515>; 237 exit-latency-us = <1821>; 238 min-residency-us = <1000>; 239 local-timer-stop; 240 }; 241 242 perf_cpu_sleep_0: cpu-sleep-1-0 { 243 compatible = "arm,idle-state"; 244 idle-state-name = "perf-retention"; 245 arm,psci-suspend-param = <0x40000002>; 246 entry-latency-us = <154>; 247 exit-latency-us = <87>; 248 min-residency-us = <200>; 249 }; 250 251 perf_cpu_sleep_1: cpu-sleep-1-1 { 252 compatible = "arm,idle-state"; 253 idle-state-name = "perf-power-collapse"; 254 arm,psci-suspend-param = <0x40000003>; 255 entry-latency-us = <262>; 256 exit-latency-us = <301>; 257 min-residency-us = <1000>; 258 local-timer-stop; 259 }; 260 261 pwr_cluster_sleep_0: cluster-sleep-0-0 { 262 compatible = "arm,idle-state"; 263 idle-state-name = "pwr-cluster-dynamic-retention"; 264 arm,psci-suspend-param = <0x400000F2>; 265 entry-latency-us = <284>; 266 exit-latency-us = <384>; 267 min-residency-us = <9987>; 268 local-timer-stop; 269 }; 270 271 pwr_cluster_sleep_1: cluster-sleep-0-1 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "pwr-cluster-retention"; 274 arm,psci-suspend-param = <0x400000F3>; 275 entry-latency-us = <338>; 276 exit-latency-us = <423>; 277 min-residency-us = <9987>; 278 local-timer-stop; 279 }; 280 281 pwr_cluster_sleep_2: cluster-sleep-0-2 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "pwr-cluster-retention"; 284 arm,psci-suspend-param = <0x400000F4>; 285 entry-latency-us = <515>; 286 exit-latency-us = <1821>; 287 min-residency-us = <9987>; 288 local-timer-stop; 289 }; 290 291 perf_cluster_sleep_0: cluster-sleep-1-0 { 292 compatible = "arm,idle-state"; 293 idle-state-name = "perf-cluster-dynamic-retention"; 294 arm,psci-suspend-param = <0x400000F2>; 295 entry-latency-us = <272>; 296 exit-latency-us = <329>; 297 min-residency-us = <9987>; 298 local-timer-stop; 299 }; 300 301 perf_cluster_sleep_1: cluster-sleep-1-1 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "perf-cluster-retention"; 304 arm,psci-suspend-param = <0x400000F3>; 305 entry-latency-us = <332>; 306 exit-latency-us = <368>; 307 min-residency-us = <9987>; 308 local-timer-stop; 309 }; 310 311 perf_cluster_sleep_2: cluster-sleep-1-2 { 312 compatible = "arm,idle-state"; 313 idle-state-name = "perf-cluster-retention"; 314 arm,psci-suspend-param = <0x400000F4>; 315 entry-latency-us = <545>; 316 exit-latency-us = <1609>; 317 min-residency-us = <9987>; 318 local-timer-stop; 319 }; 320 }; 321 }; 322 323 firmware { 324 scm { 325 compatible = "qcom,scm-msm8998", "qcom,scm"; 326 }; 327 }; 328 329 memory@80000000 { 330 device_type = "memory"; 331 /* We expect the bootloader to fill in the reg */ 332 reg = <0x0 0x80000000 0x0 0x0>; 333 }; 334 335 dsi_opp_table: opp-table-dsi { 336 compatible = "operating-points-v2"; 337 338 opp-131250000 { 339 opp-hz = /bits/ 64 <131250000>; 340 required-opps = <&rpmpd_opp_svs>; 341 }; 342 343 opp-210000000 { 344 opp-hz = /bits/ 64 <210000000>; 345 required-opps = <&rpmpd_opp_svs_plus>; 346 }; 347 348 opp-262500000 { 349 opp-hz = /bits/ 64 <262500000>; 350 required-opps = <&rpmpd_opp_nom>; 351 }; 352 }; 353 354 pmu { 355 compatible = "arm,armv8-pmuv3"; 356 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 357 }; 358 359 psci { 360 compatible = "arm,psci-1.0"; 361 method = "smc"; 362 }; 363 364 rpm: remoteproc { 365 compatible = "qcom,sdm660-rpm-proc", "qcom,rpm-proc"; 366 367 glink-edge { 368 compatible = "qcom,glink-rpm"; 369 370 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 371 qcom,rpm-msg-ram = <&rpm_msg_ram>; 372 mboxes = <&apcs_glb 0>; 373 374 rpm_requests: rpm-requests { 375 compatible = "qcom,rpm-sdm660", "qcom,glink-smd-rpm"; 376 qcom,glink-channels = "rpm_requests"; 377 378 rpmcc: clock-controller { 379 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc"; 380 #clock-cells = <1>; 381 }; 382 383 rpmpd: power-controller { 384 compatible = "qcom,sdm660-rpmpd"; 385 #power-domain-cells = <1>; 386 operating-points-v2 = <&rpmpd_opp_table>; 387 388 rpmpd_opp_table: opp-table { 389 compatible = "operating-points-v2"; 390 391 rpmpd_opp_ret: opp1 { 392 opp-level = <RPM_SMD_LEVEL_RETENTION>; 393 }; 394 395 rpmpd_opp_ret_plus: opp2 { 396 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 397 }; 398 399 rpmpd_opp_min_svs: opp3 { 400 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 401 }; 402 403 rpmpd_opp_low_svs: opp4 { 404 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 405 }; 406 407 rpmpd_opp_svs: opp5 { 408 opp-level = <RPM_SMD_LEVEL_SVS>; 409 }; 410 411 rpmpd_opp_svs_plus: opp6 { 412 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 413 }; 414 415 rpmpd_opp_nom: opp7 { 416 opp-level = <RPM_SMD_LEVEL_NOM>; 417 }; 418 419 rpmpd_opp_nom_plus: opp8 { 420 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 421 }; 422 423 rpmpd_opp_turbo: opp9 { 424 opp-level = <RPM_SMD_LEVEL_TURBO>; 425 }; 426 }; 427 }; 428 }; 429 }; 430 }; 431 432 reserved-memory { 433 #address-cells = <2>; 434 #size-cells = <2>; 435 ranges; 436 437 wlan_msa_guard: wlan-msa-guard@85600000 { 438 reg = <0x0 0x85600000 0x0 0x100000>; 439 no-map; 440 }; 441 442 wlan_msa_mem: wlan-msa-mem@85700000 { 443 reg = <0x0 0x85700000 0x0 0x100000>; 444 no-map; 445 }; 446 447 qhee_code: qhee-code@85800000 { 448 reg = <0x0 0x85800000 0x0 0x600000>; 449 no-map; 450 }; 451 452 rmtfs_mem: memory@85e00000 { 453 compatible = "qcom,rmtfs-mem"; 454 reg = <0x0 0x85e00000 0x0 0x200000>; 455 no-map; 456 457 qcom,client-id = <1>; 458 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 459 }; 460 461 smem_region: smem-mem@86000000 { 462 reg = <0 0x86000000 0 0x200000>; 463 no-map; 464 }; 465 466 tz_mem: memory@86200000 { 467 reg = <0x0 0x86200000 0x0 0x3300000>; 468 no-map; 469 }; 470 471 mpss_region: mpss@8ac00000 { 472 reg = <0x0 0x8ac00000 0x0 0x7e00000>; 473 no-map; 474 }; 475 476 adsp_region: adsp@92a00000 { 477 reg = <0x0 0x92a00000 0x0 0x1e00000>; 478 no-map; 479 }; 480 481 mba_region: mba@94800000 { 482 reg = <0x0 0x94800000 0x0 0x200000>; 483 no-map; 484 }; 485 486 buffer_mem: tzbuffer@94a00000 { 487 reg = <0x0 0x94a00000 0x0 0x100000>; 488 no-map; 489 }; 490 491 venus_region: venus@9f800000 { 492 reg = <0x0 0x9f800000 0x0 0x800000>; 493 no-map; 494 }; 495 496 adsp_mem: adsp-region@f6000000 { 497 reg = <0x0 0xf6000000 0x0 0x800000>; 498 no-map; 499 }; 500 501 qseecom_mem: qseecom-region@f6800000 { 502 reg = <0x0 0xf6800000 0x0 0x1400000>; 503 no-map; 504 }; 505 506 zap_shader_region: gpu@fed00000 { 507 compatible = "shared-dma-pool"; 508 reg = <0x0 0xfed00000 0x0 0xa00000>; 509 no-map; 510 }; 511 }; 512 513 smem: smem { 514 compatible = "qcom,smem"; 515 memory-region = <&smem_region>; 516 hwlocks = <&tcsr_mutex 3>; 517 }; 518 519 smp2p-adsp { 520 compatible = "qcom,smp2p"; 521 qcom,smem = <443>, <429>; 522 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 523 mboxes = <&apcs_glb 10>; 524 qcom,local-pid = <0>; 525 qcom,remote-pid = <2>; 526 527 adsp_smp2p_out: master-kernel { 528 qcom,entry-name = "master-kernel"; 529 #qcom,smem-state-cells = <1>; 530 }; 531 532 adsp_smp2p_in: slave-kernel { 533 qcom,entry-name = "slave-kernel"; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 }; 538 539 smp2p-mpss { 540 compatible = "qcom,smp2p"; 541 qcom,smem = <435>, <428>; 542 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 543 mboxes = <&apcs_glb 14>; 544 qcom,local-pid = <0>; 545 qcom,remote-pid = <1>; 546 547 modem_smp2p_out: master-kernel { 548 qcom,entry-name = "master-kernel"; 549 #qcom,smem-state-cells = <1>; 550 }; 551 552 modem_smp2p_in: slave-kernel { 553 qcom,entry-name = "slave-kernel"; 554 interrupt-controller; 555 #interrupt-cells = <2>; 556 }; 557 }; 558 559 soc@0 { 560 #address-cells = <1>; 561 #size-cells = <1>; 562 ranges = <0 0 0 0xffffffff>; 563 compatible = "simple-bus"; 564 565 gcc: clock-controller@100000 { 566 compatible = "qcom,gcc-sdm630"; 567 #clock-cells = <1>; 568 #reset-cells = <1>; 569 #power-domain-cells = <1>; 570 reg = <0x00100000 0x94000>; 571 572 clock-names = "xo", "sleep_clk"; 573 clocks = <&xo_board>, 574 <&sleep_clk>; 575 }; 576 577 rpm_msg_ram: sram@778000 { 578 compatible = "qcom,rpm-msg-ram"; 579 reg = <0x00778000 0x7000>; 580 }; 581 582 qfprom: qfprom@780000 { 583 compatible = "qcom,sdm630-qfprom", "qcom,qfprom"; 584 reg = <0x00780000 0x621c>; 585 #address-cells = <1>; 586 #size-cells = <1>; 587 588 qusb2_hstx_trim: hstx-trim@240 { 589 reg = <0x243 0x1>; 590 bits = <1 3>; 591 }; 592 593 gpu_speed_bin: gpu-speed-bin@41a0 { 594 reg = <0x41a2 0x1>; 595 bits = <5 7>; 596 }; 597 }; 598 599 rng: rng@793000 { 600 compatible = "qcom,prng-ee"; 601 reg = <0x00793000 0x1000>; 602 clocks = <&gcc GCC_PRNG_AHB_CLK>; 603 clock-names = "core"; 604 }; 605 606 bimc: interconnect@1008000 { 607 compatible = "qcom,sdm660-bimc"; 608 reg = <0x01008000 0x78000>; 609 #interconnect-cells = <1>; 610 }; 611 612 restart@10ac000 { 613 compatible = "qcom,pshold"; 614 reg = <0x010ac000 0x4>; 615 }; 616 617 cnoc: interconnect@1500000 { 618 compatible = "qcom,sdm660-cnoc"; 619 reg = <0x01500000 0x10000>; 620 #interconnect-cells = <1>; 621 }; 622 623 snoc: interconnect@1626000 { 624 compatible = "qcom,sdm660-snoc"; 625 reg = <0x01626000 0x7090>; 626 #interconnect-cells = <1>; 627 }; 628 629 anoc2_smmu: iommu@16c0000 { 630 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 631 reg = <0x016c0000 0x40000>; 632 #global-interrupts = <2>; 633 #iommu-cells = <1>; 634 635 interrupts = 636 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 638 639 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 374 IRQ_TYPE_LEVEL_LOW>, 641 <GIC_SPI 375 IRQ_TYPE_LEVEL_LOW>, 642 <GIC_SPI 376 IRQ_TYPE_LEVEL_LOW>, 643 <GIC_SPI 377 IRQ_TYPE_LEVEL_LOW>, 644 <GIC_SPI 378 IRQ_TYPE_LEVEL_LOW>, 645 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 668 }; 669 670 a2noc: interconnect@1704000 { 671 compatible = "qcom,sdm660-a2noc"; 672 reg = <0x01704000 0xc100>; 673 #interconnect-cells = <1>; 674 clock-names = "ipa", 675 "ufs_axi", 676 "aggre2_ufs_axi", 677 "aggre2_usb3_axi", 678 "cfg_noc_usb2_axi"; 679 clocks = <&rpmcc RPM_SMD_IPA_CLK>, 680 <&gcc GCC_UFS_AXI_CLK>, 681 <&gcc GCC_AGGRE2_UFS_AXI_CLK>, 682 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 683 <&gcc GCC_CFG_NOC_USB2_AXI_CLK>; 684 }; 685 686 mnoc: interconnect@1745000 { 687 compatible = "qcom,sdm660-mnoc"; 688 reg = <0x01745000 0xa010>; 689 #interconnect-cells = <1>; 690 clock-names = "iface"; 691 clocks = <&mmcc AHB_CLK_SRC>; 692 }; 693 694 tsens: thermal-sensor@10ae000 { 695 compatible = "qcom,sdm630-tsens", "qcom,tsens-v2"; 696 reg = <0x010ae000 0x1000>, /* TM */ 697 <0x010ad000 0x1000>; /* SROT */ 698 #qcom,sensors = <12>; 699 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 701 interrupt-names = "uplow", "critical"; 702 #thermal-sensor-cells = <1>; 703 }; 704 705 tcsr_mutex: hwlock@1f40000 { 706 compatible = "qcom,tcsr-mutex"; 707 reg = <0x01f40000 0x20000>; 708 #hwlock-cells = <1>; 709 }; 710 711 tcsr_regs_1: syscon@1f60000 { 712 compatible = "qcom,sdm630-tcsr", "syscon"; 713 reg = <0x01f60000 0x20000>; 714 }; 715 716 tlmm: pinctrl@3100000 { 717 compatible = "qcom,sdm630-pinctrl"; 718 reg = <0x03100000 0x400000>, 719 <0x03500000 0x400000>, 720 <0x03900000 0x400000>; 721 reg-names = "south", "center", "north"; 722 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 723 gpio-controller; 724 gpio-ranges = <&tlmm 0 0 114>; 725 #gpio-cells = <2>; 726 interrupt-controller; 727 #interrupt-cells = <2>; 728 729 blsp1_uart1_default: blsp1-uart1-default-state { 730 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 731 function = "blsp_uart1"; 732 drive-strength = <2>; 733 bias-disable; 734 }; 735 736 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 737 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 738 function = "gpio"; 739 drive-strength = <2>; 740 bias-disable; 741 }; 742 743 blsp1_uart2_default: blsp1-uart2-default-state { 744 pins = "gpio4", "gpio5"; 745 function = "blsp_uart2"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 blsp2_uart1_default: blsp2-uart1-active-state { 751 tx-rts-pins { 752 pins = "gpio16", "gpio19"; 753 function = "blsp_uart5"; 754 drive-strength = <2>; 755 bias-disable; 756 }; 757 758 rx-pins { 759 /* 760 * Avoid garbage data while BT module 761 * is powered off or not driving signal 762 */ 763 pins = "gpio17"; 764 function = "blsp_uart5"; 765 drive-strength = <2>; 766 bias-pull-up; 767 }; 768 769 cts-pins { 770 /* Match the pull of the BT module */ 771 pins = "gpio18"; 772 function = "blsp_uart5"; 773 drive-strength = <2>; 774 bias-pull-down; 775 }; 776 }; 777 778 blsp2_uart1_sleep: blsp2-uart1-sleep-state { 779 tx-pins { 780 pins = "gpio16"; 781 function = "gpio"; 782 drive-strength = <2>; 783 bias-pull-up; 784 }; 785 786 rx-cts-rts-pins { 787 pins = "gpio17", "gpio18", "gpio19"; 788 function = "gpio"; 789 drive-strength = <2>; 790 bias-disable; 791 }; 792 }; 793 794 i2c1_default: i2c1-default-state { 795 pins = "gpio2", "gpio3"; 796 function = "blsp_i2c1"; 797 drive-strength = <2>; 798 bias-disable; 799 }; 800 801 i2c1_sleep: i2c1-sleep-state { 802 pins = "gpio2", "gpio3"; 803 function = "blsp_i2c1"; 804 drive-strength = <2>; 805 bias-pull-up; 806 }; 807 808 i2c2_default: i2c2-default-state { 809 pins = "gpio6", "gpio7"; 810 function = "blsp_i2c2"; 811 drive-strength = <2>; 812 bias-disable; 813 }; 814 815 i2c2_sleep: i2c2-sleep-state { 816 pins = "gpio6", "gpio7"; 817 function = "blsp_i2c2"; 818 drive-strength = <2>; 819 bias-pull-up; 820 }; 821 822 i2c3_default: i2c3-default-state { 823 pins = "gpio10", "gpio11"; 824 function = "blsp_i2c3"; 825 drive-strength = <2>; 826 bias-disable; 827 }; 828 829 i2c3_sleep: i2c3-sleep-state { 830 pins = "gpio10", "gpio11"; 831 function = "blsp_i2c3"; 832 drive-strength = <2>; 833 bias-pull-up; 834 }; 835 836 i2c4_default: i2c4-default-state { 837 pins = "gpio14", "gpio15"; 838 function = "blsp_i2c4"; 839 drive-strength = <2>; 840 bias-disable; 841 }; 842 843 i2c4_sleep: i2c4-sleep-state { 844 pins = "gpio14", "gpio15"; 845 function = "blsp_i2c4"; 846 drive-strength = <2>; 847 bias-pull-up; 848 }; 849 850 i2c5_default: i2c5-default-state { 851 pins = "gpio18", "gpio19"; 852 function = "blsp_i2c5"; 853 drive-strength = <2>; 854 bias-disable; 855 }; 856 857 i2c5_sleep: i2c5-sleep-state { 858 pins = "gpio18", "gpio19"; 859 function = "blsp_i2c5"; 860 drive-strength = <2>; 861 bias-pull-up; 862 }; 863 864 i2c6_default: i2c6-default-state { 865 pins = "gpio22", "gpio23"; 866 function = "blsp_i2c6"; 867 drive-strength = <2>; 868 bias-disable; 869 }; 870 871 i2c6_sleep: i2c6-sleep-state { 872 pins = "gpio22", "gpio23"; 873 function = "blsp_i2c6"; 874 drive-strength = <2>; 875 bias-pull-up; 876 }; 877 878 i2c7_default: i2c7-default-state { 879 pins = "gpio26", "gpio27"; 880 function = "blsp_i2c7"; 881 drive-strength = <2>; 882 bias-disable; 883 }; 884 885 i2c7_sleep: i2c7-sleep-state { 886 pins = "gpio26", "gpio27"; 887 function = "blsp_i2c7"; 888 drive-strength = <2>; 889 bias-pull-up; 890 }; 891 892 i2c8_default: i2c8-default-state { 893 pins = "gpio30", "gpio31"; 894 function = "blsp_i2c8_a"; 895 drive-strength = <2>; 896 bias-disable; 897 }; 898 899 i2c8_sleep: i2c8-sleep-state { 900 pins = "gpio30", "gpio31"; 901 function = "blsp_i2c8_a"; 902 drive-strength = <2>; 903 bias-pull-up; 904 }; 905 906 cci0_default: cci0-default-state { 907 pins = "gpio36","gpio37"; 908 function = "cci_i2c"; 909 bias-pull-up; 910 drive-strength = <2>; 911 }; 912 913 cci1_default: cci1-default-state { 914 pins = "gpio38","gpio39"; 915 function = "cci_i2c"; 916 bias-pull-up; 917 drive-strength = <2>; 918 }; 919 920 sdc1_state_on: sdc1-on-state { 921 clk-pins { 922 pins = "sdc1_clk"; 923 bias-disable; 924 drive-strength = <16>; 925 }; 926 927 cmd-pins { 928 pins = "sdc1_cmd"; 929 bias-pull-up; 930 drive-strength = <10>; 931 }; 932 933 data-pins { 934 pins = "sdc1_data"; 935 bias-pull-up; 936 drive-strength = <10>; 937 }; 938 939 rclk-pins { 940 pins = "sdc1_rclk"; 941 bias-pull-down; 942 }; 943 }; 944 945 sdc1_state_off: sdc1-off-state { 946 clk-pins { 947 pins = "sdc1_clk"; 948 bias-disable; 949 drive-strength = <2>; 950 }; 951 952 cmd-pins { 953 pins = "sdc1_cmd"; 954 bias-pull-up; 955 drive-strength = <2>; 956 }; 957 958 data-pins { 959 pins = "sdc1_data"; 960 bias-pull-up; 961 drive-strength = <2>; 962 }; 963 964 rclk-pins { 965 pins = "sdc1_rclk"; 966 bias-pull-down; 967 }; 968 }; 969 970 sdc2_state_on: sdc2-on-state { 971 clk-pins { 972 pins = "sdc2_clk"; 973 bias-disable; 974 drive-strength = <16>; 975 }; 976 977 cmd-pins { 978 pins = "sdc2_cmd"; 979 bias-pull-up; 980 drive-strength = <10>; 981 }; 982 983 data-pins { 984 pins = "sdc2_data"; 985 bias-pull-up; 986 drive-strength = <10>; 987 }; 988 }; 989 990 sdc2_state_off: sdc2-off-state { 991 clk-pins { 992 pins = "sdc2_clk"; 993 bias-disable; 994 drive-strength = <2>; 995 }; 996 997 cmd-pins { 998 pins = "sdc2_cmd"; 999 bias-pull-up; 1000 drive-strength = <2>; 1001 }; 1002 1003 data-pins { 1004 pins = "sdc2_data"; 1005 bias-pull-up; 1006 drive-strength = <2>; 1007 }; 1008 }; 1009 }; 1010 1011 remoteproc_mss: remoteproc@4080000 { 1012 compatible = "qcom,sdm660-mss-pil"; 1013 reg = <0x04080000 0x100>, <0x04180000 0x40>; 1014 reg-names = "qdsp6", "rmb"; 1015 1016 interrupts-extended = <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1017 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1018 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1019 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1020 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1021 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1022 interrupt-names = "wdog", 1023 "fatal", 1024 "ready", 1025 "handover", 1026 "stop-ack", 1027 "shutdown-ack"; 1028 1029 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1030 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1031 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1032 <&gcc GPLL0_OUT_MSSCC>, 1033 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1034 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1035 <&rpmcc RPM_SMD_QDSS_CLK>, 1036 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1037 clock-names = "iface", 1038 "bus", 1039 "mem", 1040 "gpll0_mss", 1041 "snoc_axi", 1042 "mnoc_axi", 1043 "qdss", 1044 "xo"; 1045 1046 qcom,smem-states = <&modem_smp2p_out 0>; 1047 qcom,smem-state-names = "stop"; 1048 1049 resets = <&gcc GCC_MSS_RESTART>; 1050 reset-names = "mss_restart"; 1051 1052 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1053 1054 power-domains = <&rpmpd SDM660_VDDCX>, 1055 <&rpmpd SDM660_VDDMX>; 1056 power-domain-names = "cx", "mx"; 1057 1058 memory-region = <&mba_region>, <&mpss_region>; 1059 1060 status = "disabled"; 1061 1062 glink-edge { 1063 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1064 label = "modem"; 1065 qcom,remote-pid = <1>; 1066 mboxes = <&apcs_glb 15>; 1067 }; 1068 }; 1069 1070 adreno_gpu: gpu@5000000 { 1071 compatible = "qcom,adreno-508.0", "qcom,adreno"; 1072 1073 reg = <0x05000000 0x40000>; 1074 reg-names = "kgsl_3d0_reg_memory"; 1075 1076 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1077 1078 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1079 <&gpucc GPUCC_RBBMTIMER_CLK>, 1080 <&gcc GCC_BIMC_GFX_CLK>, 1081 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1082 <&gpucc GPUCC_RBCPR_CLK>, 1083 <&gpucc GPUCC_GFX3D_CLK>; 1084 1085 clock-names = "iface", 1086 "rbbmtimer", 1087 "mem", 1088 "mem_iface", 1089 "rbcpr", 1090 "core"; 1091 1092 power-domains = <&rpmpd SDM660_VDDMX>; 1093 iommus = <&kgsl_smmu 0>; 1094 1095 nvmem-cells = <&gpu_speed_bin>; 1096 nvmem-cell-names = "speed_bin"; 1097 1098 interconnects = <&bimc MASTER_OXILI &bimc SLAVE_EBI>; 1099 interconnect-names = "gfx-mem"; 1100 1101 operating-points-v2 = <&gpu_sdm630_opp_table>; 1102 #cooling-cells = <2>; 1103 1104 status = "disabled"; 1105 1106 gpu_sdm630_opp_table: opp-table { 1107 compatible = "operating-points-v2"; 1108 opp-775000000 { 1109 opp-hz = /bits/ 64 <775000000>; 1110 opp-level = <RPM_SMD_LEVEL_TURBO>; 1111 opp-peak-kBps = <5412000>; 1112 opp-supported-hw = <0xa2>; 1113 }; 1114 opp-647000000 { 1115 opp-hz = /bits/ 64 <647000000>; 1116 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1117 opp-peak-kBps = <4068000>; 1118 opp-supported-hw = <0xff>; 1119 }; 1120 opp-588000000 { 1121 opp-hz = /bits/ 64 <588000000>; 1122 opp-level = <RPM_SMD_LEVEL_NOM>; 1123 opp-peak-kBps = <3072000>; 1124 opp-supported-hw = <0xff>; 1125 }; 1126 opp-465000000 { 1127 opp-hz = /bits/ 64 <465000000>; 1128 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1129 opp-peak-kBps = <2724000>; 1130 opp-supported-hw = <0xff>; 1131 }; 1132 opp-370000000 { 1133 opp-hz = /bits/ 64 <370000000>; 1134 opp-level = <RPM_SMD_LEVEL_SVS>; 1135 opp-peak-kBps = <2188000>; 1136 opp-supported-hw = <0xff>; 1137 }; 1138 opp-240000000 { 1139 opp-hz = /bits/ 64 <240000000>; 1140 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1141 opp-peak-kBps = <1648000>; 1142 opp-supported-hw = <0xff>; 1143 }; 1144 opp-160000000 { 1145 opp-hz = /bits/ 64 <160000000>; 1146 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1147 opp-peak-kBps = <1200000>; 1148 opp-supported-hw = <0xff>; 1149 }; 1150 }; 1151 1152 adreno_gpu_zap: zap-shader { 1153 memory-region = <&zap_shader_region>; 1154 }; 1155 }; 1156 1157 kgsl_smmu: iommu@5040000 { 1158 compatible = "qcom,sdm630-smmu-v2", 1159 "qcom,adreno-smmu", "qcom,smmu-v2"; 1160 reg = <0x05040000 0x10000>; 1161 1162 /* 1163 * GX GDSC parent is CX. We need to bring up CX for SMMU 1164 * but we need both up for Adreno. On the other hand, we 1165 * need to manage the GX rpmpd domain in the adreno driver. 1166 * Enable CX/GX GDSCs here so that we can manage just the GX 1167 * RPM Power Domain in the Adreno driver. 1168 */ 1169 power-domains = <&gpucc GPU_GX_GDSC>; 1170 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1171 <&gcc GCC_BIMC_GFX_CLK>, 1172 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1173 clock-names = "iface", 1174 "mem", 1175 "mem_iface"; 1176 #global-interrupts = <2>; 1177 #iommu-cells = <1>; 1178 1179 interrupts = 1180 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1182 1183 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 1191 }; 1192 1193 gpucc: clock-controller@5065000 { 1194 compatible = "qcom,gpucc-sdm630"; 1195 #clock-cells = <1>; 1196 #reset-cells = <1>; 1197 #power-domain-cells = <1>; 1198 reg = <0x05065000 0x9038>; 1199 1200 clocks = <&xo_board>, 1201 <&gcc GCC_GPU_GPLL0_CLK>, 1202 <&gcc GCC_GPU_GPLL0_DIV_CLK>; 1203 clock-names = "xo", 1204 "gcc_gpu_gpll0_clk", 1205 "gcc_gpu_gpll0_div_clk"; 1206 }; 1207 1208 lpass_smmu: iommu@5100000 { 1209 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 1210 reg = <0x05100000 0x40000>; 1211 #iommu-cells = <1>; 1212 1213 #global-interrupts = <2>; 1214 interrupts = 1215 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1217 1218 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 1235 }; 1236 1237 sram@290000 { 1238 compatible = "qcom,rpm-stats"; 1239 reg = <0x00290000 0x10000>; 1240 }; 1241 1242 spmi_bus: spmi@800f000 { 1243 compatible = "qcom,spmi-pmic-arb"; 1244 reg = <0x0800f000 0x1000>, 1245 <0x08400000 0x1000000>, 1246 <0x09400000 0x1000000>, 1247 <0x0a400000 0x220000>, 1248 <0x0800a000 0x3000>; 1249 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1250 interrupt-names = "periph_irq"; 1251 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 1252 qcom,ee = <0>; 1253 qcom,channel = <0>; 1254 #address-cells = <2>; 1255 #size-cells = <0>; 1256 interrupt-controller; 1257 #interrupt-cells = <4>; 1258 }; 1259 1260 usb3: usb@a8f8800 { 1261 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1262 reg = <0x0a8f8800 0x400>; 1263 status = "disabled"; 1264 #address-cells = <1>; 1265 #size-cells = <1>; 1266 ranges; 1267 1268 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 1269 <&gcc GCC_USB30_MASTER_CLK>, 1270 <&gcc GCC_AGGRE2_USB3_AXI_CLK>, 1271 <&gcc GCC_USB30_SLEEP_CLK>, 1272 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1273 clock-names = "cfg_noc", 1274 "core", 1275 "iface", 1276 "sleep", 1277 "mock_utmi"; 1278 1279 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1280 <&gcc GCC_USB30_MASTER_CLK>; 1281 assigned-clock-rates = <19200000>, <120000000>; 1282 1283 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1284 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1286 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1287 interrupt-names = "pwr_event", 1288 "qusb2_phy", 1289 "hs_phy_irq", 1290 "ss_phy_irq"; 1291 1292 power-domains = <&gcc USB_30_GDSC>; 1293 1294 resets = <&gcc GCC_USB_30_BCR>; 1295 1296 usb3_dwc3: usb@a800000 { 1297 compatible = "snps,dwc3"; 1298 reg = <0x0a800000 0xc8d0>; 1299 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1300 snps,dis_u2_susphy_quirk; 1301 snps,dis_enblslpm_quirk; 1302 snps,parkmode-disable-ss-quirk; 1303 snps,dis-u1-entry-quirk; 1304 snps,dis-u2-entry-quirk; 1305 1306 phys = <&qusb2phy0>, <&usb3_qmpphy>; 1307 phy-names = "usb2-phy", "usb3-phy"; 1308 snps,hird-threshold = /bits/ 8 <0>; 1309 }; 1310 }; 1311 1312 usb3_qmpphy: phy@c010000 { 1313 compatible = "qcom,sdm660-qmp-usb3-phy"; 1314 reg = <0x0c010000 0x1000>; 1315 1316 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 1317 <&gcc GCC_USB3_CLKREF_CLK>, 1318 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1319 <&gcc GCC_USB3_PHY_PIPE_CLK>; 1320 clock-names = "aux", 1321 "ref", 1322 "cfg_ahb", 1323 "pipe"; 1324 clock-output-names = "usb3_phy_pipe_clk_src"; 1325 #clock-cells = <0>; 1326 #phy-cells = <0>; 1327 1328 resets = <&gcc GCC_USB3_PHY_BCR>, 1329 <&gcc GCC_USB3PHY_PHY_BCR>; 1330 reset-names = "phy", 1331 "phy_phy"; 1332 1333 qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; 1334 1335 status = "disabled"; 1336 }; 1337 1338 qusb2phy0: phy@c012000 { 1339 compatible = "qcom,sdm660-qusb2-phy"; 1340 reg = <0x0c012000 0x180>; 1341 #phy-cells = <0>; 1342 1343 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1344 <&gcc GCC_RX0_USB2_CLKREF_CLK>; 1345 clock-names = "cfg_ahb", "ref"; 1346 1347 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1348 nvmem-cells = <&qusb2_hstx_trim>; 1349 status = "disabled"; 1350 }; 1351 1352 qusb2phy1: phy@c014000 { 1353 compatible = "qcom,sdm660-qusb2-phy"; 1354 reg = <0x0c014000 0x180>; 1355 #phy-cells = <0>; 1356 1357 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1358 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 1359 clock-names = "cfg_ahb", "ref"; 1360 1361 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 1362 nvmem-cells = <&qusb2_hstx_trim>; 1363 status = "disabled"; 1364 }; 1365 1366 sdhc_2: mmc@c084000 { 1367 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1368 reg = <0x0c084000 0x1000>; 1369 reg-names = "hc"; 1370 1371 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1373 interrupt-names = "hc_irq", "pwr_irq"; 1374 1375 bus-width = <4>; 1376 1377 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1378 <&gcc GCC_SDCC2_APPS_CLK>, 1379 <&xo_board>; 1380 clock-names = "iface", "core", "xo"; 1381 1382 1383 interconnects = <&a2noc 3 &a2noc 10>, 1384 <&gnoc 0 &cnoc 28>; 1385 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1386 operating-points-v2 = <&sdhc2_opp_table>; 1387 1388 pinctrl-names = "default", "sleep"; 1389 pinctrl-0 = <&sdc2_state_on>; 1390 pinctrl-1 = <&sdc2_state_off>; 1391 power-domains = <&rpmpd SDM660_VDDCX>; 1392 1393 status = "disabled"; 1394 1395 sdhc2_opp_table: opp-table { 1396 compatible = "operating-points-v2"; 1397 1398 opp-50000000 { 1399 opp-hz = /bits/ 64 <50000000>; 1400 required-opps = <&rpmpd_opp_low_svs>; 1401 opp-peak-kBps = <200000 140000>; 1402 opp-avg-kBps = <130718 133320>; 1403 }; 1404 opp-100000000 { 1405 opp-hz = /bits/ 64 <100000000>; 1406 required-opps = <&rpmpd_opp_svs>; 1407 opp-peak-kBps = <250000 160000>; 1408 opp-avg-kBps = <196078 150000>; 1409 }; 1410 opp-200000000 { 1411 opp-hz = /bits/ 64 <200000000>; 1412 required-opps = <&rpmpd_opp_nom>; 1413 opp-peak-kBps = <4096000 4096000>; 1414 opp-avg-kBps = <1338562 1338562>; 1415 }; 1416 }; 1417 }; 1418 1419 sdhc_1: mmc@c0c4000 { 1420 compatible = "qcom,sdm630-sdhci", "qcom,sdhci-msm-v5"; 1421 reg = <0x0c0c4000 0x1000>, 1422 <0x0c0c5000 0x1000>, 1423 <0x0c0c8000 0x8000>; 1424 reg-names = "hc", "cqhci", "ice"; 1425 1426 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1428 interrupt-names = "hc_irq", "pwr_irq"; 1429 1430 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1431 <&gcc GCC_SDCC1_APPS_CLK>, 1432 <&xo_board>, 1433 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1434 clock-names = "iface", "core", "xo", "ice"; 1435 1436 interconnects = <&a2noc 2 &a2noc 10>, 1437 <&gnoc 0 &cnoc 27>; 1438 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 1439 operating-points-v2 = <&sdhc1_opp_table>; 1440 pinctrl-names = "default", "sleep"; 1441 pinctrl-0 = <&sdc1_state_on>; 1442 pinctrl-1 = <&sdc1_state_off>; 1443 power-domains = <&rpmpd SDM660_VDDCX>; 1444 1445 bus-width = <8>; 1446 non-removable; 1447 1448 status = "disabled"; 1449 1450 sdhc1_opp_table: opp-table { 1451 compatible = "operating-points-v2"; 1452 1453 opp-50000000 { 1454 opp-hz = /bits/ 64 <50000000>; 1455 required-opps = <&rpmpd_opp_low_svs>; 1456 opp-peak-kBps = <200000 140000>; 1457 opp-avg-kBps = <130718 133320>; 1458 }; 1459 opp-100000000 { 1460 opp-hz = /bits/ 64 <100000000>; 1461 required-opps = <&rpmpd_opp_svs>; 1462 opp-peak-kBps = <250000 160000>; 1463 opp-avg-kBps = <196078 150000>; 1464 }; 1465 opp-384000000 { 1466 opp-hz = /bits/ 64 <384000000>; 1467 required-opps = <&rpmpd_opp_nom>; 1468 opp-peak-kBps = <4096000 4096000>; 1469 opp-avg-kBps = <1338562 1338562>; 1470 }; 1471 }; 1472 }; 1473 1474 usb2: usb@c2f8800 { 1475 compatible = "qcom,sdm660-dwc3", "qcom,dwc3"; 1476 reg = <0x0c2f8800 0x400>; 1477 status = "disabled"; 1478 #address-cells = <1>; 1479 #size-cells = <1>; 1480 ranges; 1481 1482 clocks = <&gcc GCC_CFG_NOC_USB2_AXI_CLK>, 1483 <&gcc GCC_USB20_MASTER_CLK>, 1484 <&gcc GCC_USB20_SLEEP_CLK>, 1485 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 1486 clock-names = "cfg_noc", "core", 1487 "sleep", "mock_utmi"; 1488 1489 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 1490 <&gcc GCC_USB20_MASTER_CLK>; 1491 assigned-clock-rates = <19200000>, <60000000>; 1492 1493 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "pwr_event", 1497 "qusb2_phy", 1498 "hs_phy_irq"; 1499 1500 qcom,select-utmi-as-pipe-clk; 1501 1502 resets = <&gcc GCC_USB_20_BCR>; 1503 1504 usb2_dwc3: usb@c200000 { 1505 compatible = "snps,dwc3"; 1506 reg = <0x0c200000 0xc8d0>; 1507 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 1508 snps,dis_u2_susphy_quirk; 1509 snps,dis_enblslpm_quirk; 1510 snps,dis-u1-entry-quirk; 1511 snps,dis-u2-entry-quirk; 1512 1513 /* This is the HS-only host */ 1514 maximum-speed = "high-speed"; 1515 phys = <&qusb2phy1>; 1516 phy-names = "usb2-phy"; 1517 snps,hird-threshold = /bits/ 8 <0>; 1518 }; 1519 }; 1520 1521 mmcc: clock-controller@c8c0000 { 1522 compatible = "qcom,mmcc-sdm630"; 1523 reg = <0x0c8c0000 0x40000>; 1524 #clock-cells = <1>; 1525 #reset-cells = <1>; 1526 #power-domain-cells = <1>; 1527 clock-names = "xo", 1528 "sleep_clk", 1529 "gpll0", 1530 "gpll0_div", 1531 "dsi0pll", 1532 "dsi0pllbyte", 1533 "dsi1pll", 1534 "dsi1pllbyte", 1535 "dp_link_2x_clk_divsel_five", 1536 "dp_vco_divided_clk_src_mux"; 1537 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1538 <&sleep_clk>, 1539 <&gcc GCC_MMSS_GPLL0_CLK>, 1540 <&gcc GCC_MMSS_GPLL0_DIV_CLK>, 1541 <&mdss_dsi0_phy 1>, 1542 <&mdss_dsi0_phy 0>, 1543 <0>, 1544 <0>, 1545 <0>, 1546 <0>; 1547 }; 1548 1549 mdss: display-subsystem@c900000 { 1550 compatible = "qcom,mdss"; 1551 reg = <0x0c900000 0x1000>, 1552 <0x0c9b0000 0x1040>; 1553 reg-names = "mdss_phys", "vbif_phys"; 1554 1555 power-domains = <&mmcc MDSS_GDSC>; 1556 1557 clocks = <&mmcc MDSS_AHB_CLK>, 1558 <&mmcc MDSS_AXI_CLK>, 1559 <&mmcc MDSS_VSYNC_CLK>, 1560 <&mmcc MDSS_MDP_CLK>; 1561 clock-names = "iface", 1562 "bus", 1563 "vsync", 1564 "core"; 1565 1566 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1567 1568 interrupt-controller; 1569 #interrupt-cells = <1>; 1570 1571 #address-cells = <1>; 1572 #size-cells = <1>; 1573 ranges; 1574 status = "disabled"; 1575 1576 mdp: display-controller@c901000 { 1577 compatible = "qcom,sdm630-mdp5", "qcom,mdp5"; 1578 reg = <0x0c901000 0x89000>; 1579 reg-names = "mdp_phys"; 1580 1581 interrupt-parent = <&mdss>; 1582 interrupts = <0>; 1583 1584 assigned-clocks = <&mmcc MDSS_MDP_CLK>, 1585 <&mmcc MDSS_VSYNC_CLK>; 1586 assigned-clock-rates = <300000000>, 1587 <19200000>; 1588 clocks = <&mmcc MDSS_AHB_CLK>, 1589 <&mmcc MDSS_AXI_CLK>, 1590 <&mmcc MDSS_MDP_CLK>, 1591 <&mmcc MDSS_VSYNC_CLK>; 1592 clock-names = "iface", 1593 "bus", 1594 "core", 1595 "vsync"; 1596 1597 interconnects = <&mnoc 2 &bimc 5>, 1598 <&mnoc 3 &bimc 5>, 1599 <&gnoc 0 &mnoc 17>; 1600 interconnect-names = "mdp0-mem", 1601 "mdp1-mem", 1602 "rotator-mem"; 1603 iommus = <&mmss_smmu 0>; 1604 operating-points-v2 = <&mdp_opp_table>; 1605 power-domains = <&rpmpd SDM660_VDDCX>; 1606 1607 ports { 1608 #address-cells = <1>; 1609 #size-cells = <0>; 1610 1611 port@0 { 1612 reg = <0>; 1613 mdp5_intf1_out: endpoint { 1614 remote-endpoint = <&mdss_dsi0_in>; 1615 }; 1616 }; 1617 }; 1618 1619 mdp_opp_table: opp-table { 1620 compatible = "operating-points-v2"; 1621 1622 opp-150000000 { 1623 opp-hz = /bits/ 64 <150000000>; 1624 opp-peak-kBps = <320000 320000 76800>; 1625 required-opps = <&rpmpd_opp_low_svs>; 1626 }; 1627 opp-275000000 { 1628 opp-hz = /bits/ 64 <275000000>; 1629 opp-peak-kBps = <6400000 6400000 160000>; 1630 required-opps = <&rpmpd_opp_svs>; 1631 }; 1632 opp-300000000 { 1633 opp-hz = /bits/ 64 <300000000>; 1634 opp-peak-kBps = <6400000 6400000 190000>; 1635 required-opps = <&rpmpd_opp_svs_plus>; 1636 }; 1637 opp-330000000 { 1638 opp-hz = /bits/ 64 <330000000>; 1639 opp-peak-kBps = <6400000 6400000 240000>; 1640 required-opps = <&rpmpd_opp_nom>; 1641 }; 1642 opp-412500000 { 1643 opp-hz = /bits/ 64 <412500000>; 1644 opp-peak-kBps = <6400000 6400000 320000>; 1645 required-opps = <&rpmpd_opp_turbo>; 1646 }; 1647 }; 1648 }; 1649 1650 mdss_dsi0: dsi@c994000 { 1651 compatible = "qcom,sdm660-dsi-ctrl", 1652 "qcom,mdss-dsi-ctrl"; 1653 reg = <0x0c994000 0x400>; 1654 reg-names = "dsi_ctrl"; 1655 1656 operating-points-v2 = <&dsi_opp_table>; 1657 power-domains = <&rpmpd SDM660_VDDCX>; 1658 1659 interrupt-parent = <&mdss>; 1660 interrupts = <4>; 1661 1662 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 1663 <&mmcc PCLK0_CLK_SRC>; 1664 assigned-clock-parents = <&mdss_dsi0_phy 0>, 1665 <&mdss_dsi0_phy 1>; 1666 1667 clocks = <&mmcc MDSS_MDP_CLK>, 1668 <&mmcc MDSS_BYTE0_CLK>, 1669 <&mmcc MDSS_BYTE0_INTF_CLK>, 1670 <&mmcc MNOC_AHB_CLK>, 1671 <&mmcc MDSS_AHB_CLK>, 1672 <&mmcc MDSS_AXI_CLK>, 1673 <&mmcc MISC_AHB_CLK>, 1674 <&mmcc MDSS_PCLK0_CLK>, 1675 <&mmcc MDSS_ESC0_CLK>; 1676 clock-names = "mdp_core", 1677 "byte", 1678 "byte_intf", 1679 "mnoc", 1680 "iface", 1681 "bus", 1682 "core_mmss", 1683 "pixel", 1684 "core"; 1685 1686 phys = <&mdss_dsi0_phy>; 1687 1688 status = "disabled"; 1689 1690 ports { 1691 #address-cells = <1>; 1692 #size-cells = <0>; 1693 1694 port@0 { 1695 reg = <0>; 1696 mdss_dsi0_in: endpoint { 1697 remote-endpoint = <&mdp5_intf1_out>; 1698 }; 1699 }; 1700 1701 port@1 { 1702 reg = <1>; 1703 mdss_dsi0_out: endpoint { 1704 }; 1705 }; 1706 }; 1707 }; 1708 1709 mdss_dsi0_phy: phy@c994400 { 1710 compatible = "qcom,dsi-phy-14nm-660"; 1711 reg = <0x0c994400 0x100>, 1712 <0x0c994500 0x300>, 1713 <0x0c994800 0x188>; 1714 reg-names = "dsi_phy", 1715 "dsi_phy_lane", 1716 "dsi_pll"; 1717 1718 #clock-cells = <1>; 1719 #phy-cells = <0>; 1720 1721 clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; 1722 clock-names = "iface", "ref"; 1723 status = "disabled"; 1724 }; 1725 }; 1726 1727 blsp1_dma: dma-controller@c144000 { 1728 compatible = "qcom,bam-v1.7.0"; 1729 reg = <0x0c144000 0x1f000>; 1730 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1731 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1732 clock-names = "bam_clk"; 1733 #dma-cells = <1>; 1734 qcom,ee = <0>; 1735 qcom,controlled-remotely; 1736 num-channels = <18>; 1737 qcom,num-ees = <4>; 1738 }; 1739 1740 blsp1_uart1: serial@c16f000 { 1741 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1742 reg = <0x0c16f000 0x200>; 1743 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1744 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1745 <&gcc GCC_BLSP1_AHB_CLK>; 1746 clock-names = "core", "iface"; 1747 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1748 dma-names = "tx", "rx"; 1749 pinctrl-names = "default", "sleep"; 1750 pinctrl-0 = <&blsp1_uart1_default>; 1751 pinctrl-1 = <&blsp1_uart1_sleep>; 1752 status = "disabled"; 1753 }; 1754 1755 blsp1_uart2: serial@c170000 { 1756 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1757 reg = <0x0c170000 0x1000>; 1758 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1759 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1760 <&gcc GCC_BLSP1_AHB_CLK>; 1761 clock-names = "core", "iface"; 1762 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1763 dma-names = "tx", "rx"; 1764 pinctrl-names = "default"; 1765 pinctrl-0 = <&blsp1_uart2_default>; 1766 status = "disabled"; 1767 }; 1768 1769 blsp_i2c1: i2c@c175000 { 1770 compatible = "qcom,i2c-qup-v2.2.1"; 1771 reg = <0x0c175000 0x600>; 1772 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1773 1774 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1775 <&gcc GCC_BLSP1_AHB_CLK>; 1776 clock-names = "core", "iface"; 1777 clock-frequency = <400000>; 1778 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1779 dma-names = "tx", "rx"; 1780 1781 pinctrl-names = "default", "sleep"; 1782 pinctrl-0 = <&i2c1_default>; 1783 pinctrl-1 = <&i2c1_sleep>; 1784 #address-cells = <1>; 1785 #size-cells = <0>; 1786 status = "disabled"; 1787 }; 1788 1789 blsp_i2c2: i2c@c176000 { 1790 compatible = "qcom,i2c-qup-v2.2.1"; 1791 reg = <0x0c176000 0x600>; 1792 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1793 1794 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1795 <&gcc GCC_BLSP1_AHB_CLK>; 1796 clock-names = "core", "iface"; 1797 clock-frequency = <400000>; 1798 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1799 dma-names = "tx", "rx"; 1800 1801 pinctrl-names = "default", "sleep"; 1802 pinctrl-0 = <&i2c2_default>; 1803 pinctrl-1 = <&i2c2_sleep>; 1804 #address-cells = <1>; 1805 #size-cells = <0>; 1806 status = "disabled"; 1807 }; 1808 1809 blsp_i2c3: i2c@c177000 { 1810 compatible = "qcom,i2c-qup-v2.2.1"; 1811 reg = <0x0c177000 0x600>; 1812 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1813 1814 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1815 <&gcc GCC_BLSP1_AHB_CLK>; 1816 clock-names = "core", "iface"; 1817 clock-frequency = <400000>; 1818 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1819 dma-names = "tx", "rx"; 1820 1821 pinctrl-names = "default", "sleep"; 1822 pinctrl-0 = <&i2c3_default>; 1823 pinctrl-1 = <&i2c3_sleep>; 1824 #address-cells = <1>; 1825 #size-cells = <0>; 1826 status = "disabled"; 1827 }; 1828 1829 blsp_i2c4: i2c@c178000 { 1830 compatible = "qcom,i2c-qup-v2.2.1"; 1831 reg = <0x0c178000 0x600>; 1832 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1833 1834 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1835 <&gcc GCC_BLSP1_AHB_CLK>; 1836 clock-names = "core", "iface"; 1837 clock-frequency = <400000>; 1838 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1839 dma-names = "tx", "rx"; 1840 1841 pinctrl-names = "default", "sleep"; 1842 pinctrl-0 = <&i2c4_default>; 1843 pinctrl-1 = <&i2c4_sleep>; 1844 #address-cells = <1>; 1845 #size-cells = <0>; 1846 status = "disabled"; 1847 }; 1848 1849 blsp2_dma: dma-controller@c184000 { 1850 compatible = "qcom,bam-v1.7.0"; 1851 reg = <0x0c184000 0x1f000>; 1852 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1853 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1854 clock-names = "bam_clk"; 1855 #dma-cells = <1>; 1856 qcom,ee = <0>; 1857 qcom,controlled-remotely; 1858 num-channels = <18>; 1859 qcom,num-ees = <4>; 1860 }; 1861 1862 blsp2_uart1: serial@c1af000 { 1863 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1864 reg = <0x0c1af000 0x200>; 1865 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1866 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1867 <&gcc GCC_BLSP2_AHB_CLK>; 1868 clock-names = "core", "iface"; 1869 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1870 dma-names = "tx", "rx"; 1871 pinctrl-names = "default", "sleep"; 1872 pinctrl-0 = <&blsp2_uart1_default>; 1873 pinctrl-1 = <&blsp2_uart1_sleep>; 1874 status = "disabled"; 1875 }; 1876 1877 blsp_i2c5: i2c@c1b5000 { 1878 compatible = "qcom,i2c-qup-v2.2.1"; 1879 reg = <0x0c1b5000 0x600>; 1880 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 1881 1882 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1883 <&gcc GCC_BLSP2_AHB_CLK>; 1884 clock-names = "core", "iface"; 1885 clock-frequency = <400000>; 1886 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1887 dma-names = "tx", "rx"; 1888 1889 pinctrl-names = "default", "sleep"; 1890 pinctrl-0 = <&i2c5_default>; 1891 pinctrl-1 = <&i2c5_sleep>; 1892 #address-cells = <1>; 1893 #size-cells = <0>; 1894 status = "disabled"; 1895 }; 1896 1897 blsp_i2c6: i2c@c1b6000 { 1898 compatible = "qcom,i2c-qup-v2.2.1"; 1899 reg = <0x0c1b6000 0x600>; 1900 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1901 1902 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1903 <&gcc GCC_BLSP2_AHB_CLK>; 1904 clock-names = "core", "iface"; 1905 clock-frequency = <400000>; 1906 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1907 dma-names = "tx", "rx"; 1908 1909 pinctrl-names = "default", "sleep"; 1910 pinctrl-0 = <&i2c6_default>; 1911 pinctrl-1 = <&i2c6_sleep>; 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 status = "disabled"; 1915 }; 1916 1917 blsp_i2c7: i2c@c1b7000 { 1918 compatible = "qcom,i2c-qup-v2.2.1"; 1919 reg = <0x0c1b7000 0x600>; 1920 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1921 1922 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1923 <&gcc GCC_BLSP2_AHB_CLK>; 1924 clock-names = "core", "iface"; 1925 clock-frequency = <400000>; 1926 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1927 dma-names = "tx", "rx"; 1928 1929 pinctrl-names = "default", "sleep"; 1930 pinctrl-0 = <&i2c7_default>; 1931 pinctrl-1 = <&i2c7_sleep>; 1932 #address-cells = <1>; 1933 #size-cells = <0>; 1934 status = "disabled"; 1935 }; 1936 1937 blsp_i2c8: i2c@c1b8000 { 1938 compatible = "qcom,i2c-qup-v2.2.1"; 1939 reg = <0x0c1b8000 0x600>; 1940 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1941 1942 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1943 <&gcc GCC_BLSP2_AHB_CLK>; 1944 clock-names = "core", "iface"; 1945 clock-frequency = <400000>; 1946 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1947 dma-names = "tx", "rx"; 1948 1949 pinctrl-names = "default", "sleep"; 1950 pinctrl-0 = <&i2c8_default>; 1951 pinctrl-1 = <&i2c8_sleep>; 1952 #address-cells = <1>; 1953 #size-cells = <0>; 1954 status = "disabled"; 1955 }; 1956 1957 sram@146bf000 { 1958 compatible = "qcom,sdm630-imem", "syscon", "simple-mfd"; 1959 reg = <0x146bf000 0x1000>; 1960 1961 #address-cells = <1>; 1962 #size-cells = <1>; 1963 1964 ranges = <0 0x146bf000 0x1000>; 1965 1966 pil-reloc@94c { 1967 compatible = "qcom,pil-reloc-info"; 1968 reg = <0x94c 0xc8>; 1969 }; 1970 }; 1971 1972 camss: camss@ca00020 { 1973 compatible = "qcom,sdm660-camss"; 1974 reg = <0x0ca00020 0x10>, 1975 <0x0ca30000 0x100>, 1976 <0x0ca30400 0x100>, 1977 <0x0ca30800 0x100>, 1978 <0x0ca30c00 0x100>, 1979 <0x0c824000 0x1000>, 1980 <0x0ca00120 0x4>, 1981 <0x0c825000 0x1000>, 1982 <0x0ca00124 0x4>, 1983 <0x0c826000 0x1000>, 1984 <0x0ca00128 0x4>, 1985 <0x0ca31000 0x500>, 1986 <0x0ca10000 0x1000>, 1987 <0x0ca14000 0x1000>; 1988 reg-names = "csi_clk_mux", 1989 "csid0", 1990 "csid1", 1991 "csid2", 1992 "csid3", 1993 "csiphy0", 1994 "csiphy0_clk_mux", 1995 "csiphy1", 1996 "csiphy1_clk_mux", 1997 "csiphy2", 1998 "csiphy2_clk_mux", 1999 "ispif", 2000 "vfe0", 2001 "vfe1"; 2002 interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>, 2003 <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>, 2004 <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>, 2005 <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>, 2006 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 2007 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 2008 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 2009 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 2010 <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>, 2011 <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>; 2012 interrupt-names = "csid0", 2013 "csid1", 2014 "csid2", 2015 "csid3", 2016 "csiphy0", 2017 "csiphy1", 2018 "csiphy2", 2019 "ispif", 2020 "vfe0", 2021 "vfe1"; 2022 clocks = <&mmcc CAMSS_AHB_CLK>, 2023 <&mmcc CAMSS_CPHY_CSID0_CLK>, 2024 <&mmcc CAMSS_CPHY_CSID1_CLK>, 2025 <&mmcc CAMSS_CPHY_CSID2_CLK>, 2026 <&mmcc CAMSS_CPHY_CSID3_CLK>, 2027 <&mmcc CAMSS_CSI0_AHB_CLK>, 2028 <&mmcc CAMSS_CSI0_CLK>, 2029 <&mmcc CAMSS_CPHY_CSID0_CLK>, 2030 <&mmcc CAMSS_CSI0PIX_CLK>, 2031 <&mmcc CAMSS_CSI0RDI_CLK>, 2032 <&mmcc CAMSS_CSI1_AHB_CLK>, 2033 <&mmcc CAMSS_CSI1_CLK>, 2034 <&mmcc CAMSS_CPHY_CSID1_CLK>, 2035 <&mmcc CAMSS_CSI1PIX_CLK>, 2036 <&mmcc CAMSS_CSI1RDI_CLK>, 2037 <&mmcc CAMSS_CSI2_AHB_CLK>, 2038 <&mmcc CAMSS_CSI2_CLK>, 2039 <&mmcc CAMSS_CPHY_CSID2_CLK>, 2040 <&mmcc CAMSS_CSI2PIX_CLK>, 2041 <&mmcc CAMSS_CSI2RDI_CLK>, 2042 <&mmcc CAMSS_CSI3_AHB_CLK>, 2043 <&mmcc CAMSS_CSI3_CLK>, 2044 <&mmcc CAMSS_CPHY_CSID3_CLK>, 2045 <&mmcc CAMSS_CSI3PIX_CLK>, 2046 <&mmcc CAMSS_CSI3RDI_CLK>, 2047 <&mmcc CAMSS_CSI0PHYTIMER_CLK>, 2048 <&mmcc CAMSS_CSI1PHYTIMER_CLK>, 2049 <&mmcc CAMSS_CSI2PHYTIMER_CLK>, 2050 <&mmcc CSIPHY_AHB2CRIF_CLK>, 2051 <&mmcc CAMSS_CSI_VFE0_CLK>, 2052 <&mmcc CAMSS_CSI_VFE1_CLK>, 2053 <&mmcc CAMSS_ISPIF_AHB_CLK>, 2054 <&mmcc THROTTLE_CAMSS_AXI_CLK>, 2055 <&mmcc CAMSS_TOP_AHB_CLK>, 2056 <&mmcc CAMSS_VFE0_AHB_CLK>, 2057 <&mmcc CAMSS_VFE0_CLK>, 2058 <&mmcc CAMSS_VFE0_STREAM_CLK>, 2059 <&mmcc CAMSS_VFE1_AHB_CLK>, 2060 <&mmcc CAMSS_VFE1_CLK>, 2061 <&mmcc CAMSS_VFE1_STREAM_CLK>, 2062 <&mmcc CAMSS_VFE_VBIF_AHB_CLK>, 2063 <&mmcc CAMSS_VFE_VBIF_AXI_CLK>; 2064 clock-names = "ahb", 2065 "cphy_csid0", 2066 "cphy_csid1", 2067 "cphy_csid2", 2068 "cphy_csid3", 2069 "csi0_ahb", 2070 "csi0", 2071 "csi0_phy", 2072 "csi0_pix", 2073 "csi0_rdi", 2074 "csi1_ahb", 2075 "csi1", 2076 "csi1_phy", 2077 "csi1_pix", 2078 "csi1_rdi", 2079 "csi2_ahb", 2080 "csi2", 2081 "csi2_phy", 2082 "csi2_pix", 2083 "csi2_rdi", 2084 "csi3_ahb", 2085 "csi3", 2086 "csi3_phy", 2087 "csi3_pix", 2088 "csi3_rdi", 2089 "csiphy0_timer", 2090 "csiphy1_timer", 2091 "csiphy2_timer", 2092 "csiphy_ahb2crif", 2093 "csi_vfe0", 2094 "csi_vfe1", 2095 "ispif_ahb", 2096 "throttle_axi", 2097 "top_ahb", 2098 "vfe0_ahb", 2099 "vfe0", 2100 "vfe0_stream", 2101 "vfe1_ahb", 2102 "vfe1", 2103 "vfe1_stream", 2104 "vfe_ahb", 2105 "vfe_axi"; 2106 interconnects = <&mnoc 5 &bimc 5>; 2107 interconnect-names = "vfe-mem"; 2108 iommus = <&mmss_smmu 0xc00>, 2109 <&mmss_smmu 0xc01>, 2110 <&mmss_smmu 0xc02>, 2111 <&mmss_smmu 0xc03>; 2112 power-domains = <&mmcc CAMSS_VFE0_GDSC>, 2113 <&mmcc CAMSS_VFE1_GDSC>; 2114 status = "disabled"; 2115 2116 ports { 2117 #address-cells = <1>; 2118 #size-cells = <0>; 2119 }; 2120 }; 2121 2122 cci: cci@ca0c000 { 2123 compatible = "qcom,msm8996-cci"; 2124 #address-cells = <1>; 2125 #size-cells = <0>; 2126 reg = <0x0ca0c000 0x1000>; 2127 interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>; 2128 2129 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>, 2130 <&mmcc CAMSS_CCI_CLK>; 2131 assigned-clock-rates = <80800000>, <37500000>; 2132 clocks = <&mmcc CAMSS_TOP_AHB_CLK>, 2133 <&mmcc CAMSS_CCI_AHB_CLK>, 2134 <&mmcc CAMSS_CCI_CLK>, 2135 <&mmcc CAMSS_AHB_CLK>; 2136 clock-names = "camss_top_ahb", 2137 "cci_ahb", 2138 "cci", 2139 "camss_ahb"; 2140 2141 pinctrl-names = "default"; 2142 pinctrl-0 = <&cci0_default &cci1_default>; 2143 power-domains = <&mmcc CAMSS_TOP_GDSC>; 2144 status = "disabled"; 2145 2146 cci_i2c0: i2c-bus@0 { 2147 reg = <0>; 2148 clock-frequency = <400000>; 2149 #address-cells = <1>; 2150 #size-cells = <0>; 2151 }; 2152 2153 cci_i2c1: i2c-bus@1 { 2154 reg = <1>; 2155 clock-frequency = <400000>; 2156 #address-cells = <1>; 2157 #size-cells = <0>; 2158 }; 2159 }; 2160 2161 venus: video-codec@cc00000 { 2162 compatible = "qcom,sdm660-venus"; 2163 reg = <0x0cc00000 0xff000>; 2164 clocks = <&mmcc VIDEO_CORE_CLK>, 2165 <&mmcc VIDEO_AHB_CLK>, 2166 <&mmcc VIDEO_AXI_CLK>, 2167 <&mmcc THROTTLE_VIDEO_AXI_CLK>; 2168 clock-names = "core", "iface", "bus", "bus_throttle"; 2169 interconnects = <&gnoc 0 &mnoc 13>, 2170 <&mnoc 4 &bimc 5>; 2171 interconnect-names = "cpu-cfg", "video-mem"; 2172 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 2173 iommus = <&mmss_smmu 0x400>, 2174 <&mmss_smmu 0x401>, 2175 <&mmss_smmu 0x40a>, 2176 <&mmss_smmu 0x407>, 2177 <&mmss_smmu 0x40e>, 2178 <&mmss_smmu 0x40f>, 2179 <&mmss_smmu 0x408>, 2180 <&mmss_smmu 0x409>, 2181 <&mmss_smmu 0x40b>, 2182 <&mmss_smmu 0x40c>, 2183 <&mmss_smmu 0x40d>, 2184 <&mmss_smmu 0x410>, 2185 <&mmss_smmu 0x421>, 2186 <&mmss_smmu 0x428>, 2187 <&mmss_smmu 0x429>, 2188 <&mmss_smmu 0x42b>, 2189 <&mmss_smmu 0x42c>, 2190 <&mmss_smmu 0x42d>, 2191 <&mmss_smmu 0x411>, 2192 <&mmss_smmu 0x431>; 2193 memory-region = <&venus_region>; 2194 power-domains = <&mmcc VENUS_GDSC>; 2195 status = "disabled"; 2196 2197 video-decoder { 2198 compatible = "venus-decoder"; 2199 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2200 clock-names = "vcodec0_core"; 2201 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2202 }; 2203 2204 video-encoder { 2205 compatible = "venus-encoder"; 2206 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 2207 clock-names = "vcodec0_core"; 2208 power-domains = <&mmcc VENUS_CORE0_GDSC>; 2209 }; 2210 }; 2211 2212 mmss_smmu: iommu@cd00000 { 2213 compatible = "qcom,sdm630-smmu-v2", "qcom,smmu-v2"; 2214 reg = <0x0cd00000 0x40000>; 2215 2216 clocks = <&mmcc MNOC_AHB_CLK>, 2217 <&mmcc BIMC_SMMU_AHB_CLK>, 2218 <&mmcc BIMC_SMMU_AXI_CLK>; 2219 clock-names = "iface-mm", "iface-smmu", 2220 "bus-smmu"; 2221 #global-interrupts = <2>; 2222 #iommu-cells = <1>; 2223 2224 interrupts = 2225 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2227 2228 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 2229 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 2238 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 2239 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 2240 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 2241 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 2242 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 2243 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 2244 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 2245 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 2246 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 2247 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 2248 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 2249 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 2250 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 2251 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 2252 2253 status = "disabled"; 2254 }; 2255 2256 adsp_pil: remoteproc@15700000 { 2257 compatible = "qcom,sdm660-adsp-pas"; 2258 reg = <0x15700000 0x4040>; 2259 2260 interrupts-extended = 2261 <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2262 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2263 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2264 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2265 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2266 interrupt-names = "wdog", "fatal", "ready", 2267 "handover", "stop-ack"; 2268 2269 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2270 clock-names = "xo"; 2271 2272 memory-region = <&adsp_region>; 2273 power-domains = <&rpmpd SDM660_VDDCX>; 2274 power-domain-names = "cx"; 2275 2276 qcom,smem-states = <&adsp_smp2p_out 0>; 2277 qcom,smem-state-names = "stop"; 2278 2279 glink-edge { 2280 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 2281 2282 label = "lpass"; 2283 mboxes = <&apcs_glb 9>; 2284 qcom,remote-pid = <2>; 2285 2286 apr { 2287 compatible = "qcom,apr-v2"; 2288 qcom,glink-channels = "apr_audio_svc"; 2289 qcom,domain = <APR_DOMAIN_ADSP>; 2290 #address-cells = <1>; 2291 #size-cells = <0>; 2292 2293 service@3 { 2294 reg = <APR_SVC_ADSP_CORE>; 2295 compatible = "qcom,q6core"; 2296 }; 2297 2298 q6afe: service@4 { 2299 compatible = "qcom,q6afe"; 2300 reg = <APR_SVC_AFE>; 2301 q6afedai: dais { 2302 compatible = "qcom,q6afe-dais"; 2303 #address-cells = <1>; 2304 #size-cells = <0>; 2305 #sound-dai-cells = <1>; 2306 }; 2307 }; 2308 2309 q6asm: service@7 { 2310 compatible = "qcom,q6asm"; 2311 reg = <APR_SVC_ASM>; 2312 q6asmdai: dais { 2313 compatible = "qcom,q6asm-dais"; 2314 #address-cells = <1>; 2315 #size-cells = <0>; 2316 #sound-dai-cells = <1>; 2317 iommus = <&lpass_smmu 1>; 2318 }; 2319 }; 2320 2321 q6adm: service@8 { 2322 compatible = "qcom,q6adm"; 2323 reg = <APR_SVC_ADM>; 2324 q6routing: routing { 2325 compatible = "qcom,q6adm-routing"; 2326 #sound-dai-cells = <0>; 2327 }; 2328 }; 2329 }; 2330 }; 2331 }; 2332 2333 gnoc: interconnect@17900000 { 2334 compatible = "qcom,sdm660-gnoc"; 2335 reg = <0x17900000 0xe000>; 2336 #interconnect-cells = <1>; 2337 }; 2338 2339 apcs_glb: mailbox@17911000 { 2340 compatible = "qcom,sdm660-apcs-hmss-global", 2341 "qcom,msm8994-apcs-kpss-global"; 2342 reg = <0x17911000 0x1000>; 2343 2344 #mbox-cells = <1>; 2345 }; 2346 2347 timer@17920000 { 2348 #address-cells = <1>; 2349 #size-cells = <1>; 2350 ranges; 2351 compatible = "arm,armv7-timer-mem"; 2352 reg = <0x17920000 0x1000>; 2353 clock-frequency = <19200000>; 2354 2355 frame@17921000 { 2356 frame-number = <0>; 2357 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2358 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2359 reg = <0x17921000 0x1000>, 2360 <0x17922000 0x1000>; 2361 }; 2362 2363 frame@17923000 { 2364 frame-number = <1>; 2365 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2366 reg = <0x17923000 0x1000>; 2367 status = "disabled"; 2368 }; 2369 2370 frame@17924000 { 2371 frame-number = <2>; 2372 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2373 reg = <0x17924000 0x1000>; 2374 status = "disabled"; 2375 }; 2376 2377 frame@17925000 { 2378 frame-number = <3>; 2379 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2380 reg = <0x17925000 0x1000>; 2381 status = "disabled"; 2382 }; 2383 2384 frame@17926000 { 2385 frame-number = <4>; 2386 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2387 reg = <0x17926000 0x1000>; 2388 status = "disabled"; 2389 }; 2390 2391 frame@17927000 { 2392 frame-number = <5>; 2393 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2394 reg = <0x17927000 0x1000>; 2395 status = "disabled"; 2396 }; 2397 2398 frame@17928000 { 2399 frame-number = <6>; 2400 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2401 reg = <0x17928000 0x1000>; 2402 status = "disabled"; 2403 }; 2404 }; 2405 2406 intc: interrupt-controller@17a00000 { 2407 compatible = "arm,gic-v3"; 2408 reg = <0x17a00000 0x10000>, /* GICD */ 2409 <0x17b00000 0x100000>; /* GICR * 8 */ 2410 #interrupt-cells = <3>; 2411 #address-cells = <1>; 2412 #size-cells = <1>; 2413 ranges; 2414 interrupt-controller; 2415 #redistributor-regions = <1>; 2416 redistributor-stride = <0x0 0x20000>; 2417 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2418 }; 2419 2420 wifi: wifi@18800000 { 2421 compatible = "qcom,wcn3990-wifi"; 2422 reg = <0x18800000 0x800000>; 2423 reg-names = "membase"; 2424 memory-region = <&wlan_msa_mem>; 2425 clocks = <&rpmcc RPM_SMD_RF_CLK1_PIN>; 2426 clock-names = "cxo_ref_clk_pin"; 2427 interrupts = 2428 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 2429 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 2430 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 2431 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 2432 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 2433 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 2434 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 2435 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 2436 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 2437 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 2438 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 2439 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 2440 iommus = <&anoc2_smmu 0x1a00>, 2441 <&anoc2_smmu 0x1a01>; 2442 qcom,snoc-host-cap-8bit-quirk; 2443 qcom,no-msa-ready-indicator; 2444 status = "disabled"; 2445 }; 2446 }; 2447 2448 sound: sound { 2449 }; 2450 2451 thermal-zones { 2452 aoss-thermal { 2453 polling-delay-passive = <250>; 2454 2455 thermal-sensors = <&tsens 0>; 2456 2457 trips { 2458 aoss_alert0: trip-point0 { 2459 temperature = <105000>; 2460 hysteresis = <1000>; 2461 type = "hot"; 2462 }; 2463 }; 2464 }; 2465 2466 cpuss0-thermal { 2467 polling-delay-passive = <250>; 2468 2469 thermal-sensors = <&tsens 1>; 2470 2471 trips { 2472 cpuss0_alert0: trip-point0 { 2473 temperature = <125000>; 2474 hysteresis = <1000>; 2475 type = "hot"; 2476 }; 2477 }; 2478 }; 2479 2480 cpuss1-thermal { 2481 polling-delay-passive = <250>; 2482 2483 thermal-sensors = <&tsens 2>; 2484 2485 trips { 2486 cpuss1_alert0: trip-point0 { 2487 temperature = <125000>; 2488 hysteresis = <1000>; 2489 type = "hot"; 2490 }; 2491 }; 2492 }; 2493 2494 cpu0-thermal { 2495 polling-delay-passive = <250>; 2496 2497 thermal-sensors = <&tsens 3>; 2498 2499 trips { 2500 cpu0_alert0: trip-point0 { 2501 temperature = <70000>; 2502 hysteresis = <1000>; 2503 type = "passive"; 2504 }; 2505 2506 cpu0_crit: cpu-crit { 2507 temperature = <110000>; 2508 hysteresis = <1000>; 2509 type = "critical"; 2510 }; 2511 }; 2512 }; 2513 2514 cpu1-thermal { 2515 polling-delay-passive = <250>; 2516 2517 thermal-sensors = <&tsens 4>; 2518 2519 trips { 2520 cpu1_alert0: trip-point0 { 2521 temperature = <70000>; 2522 hysteresis = <1000>; 2523 type = "passive"; 2524 }; 2525 2526 cpu1_crit: cpu-crit { 2527 temperature = <110000>; 2528 hysteresis = <1000>; 2529 type = "critical"; 2530 }; 2531 }; 2532 }; 2533 2534 cpu2-thermal { 2535 polling-delay-passive = <250>; 2536 2537 thermal-sensors = <&tsens 5>; 2538 2539 trips { 2540 cpu2_alert0: trip-point0 { 2541 temperature = <70000>; 2542 hysteresis = <1000>; 2543 type = "passive"; 2544 }; 2545 2546 cpu2_crit: cpu-crit { 2547 temperature = <110000>; 2548 hysteresis = <1000>; 2549 type = "critical"; 2550 }; 2551 }; 2552 }; 2553 2554 cpu3-thermal { 2555 polling-delay-passive = <250>; 2556 2557 thermal-sensors = <&tsens 6>; 2558 2559 trips { 2560 cpu3_alert0: trip-point0 { 2561 temperature = <70000>; 2562 hysteresis = <1000>; 2563 type = "passive"; 2564 }; 2565 2566 cpu3_crit: cpu-crit { 2567 temperature = <110000>; 2568 hysteresis = <1000>; 2569 type = "critical"; 2570 }; 2571 }; 2572 }; 2573 2574 /* 2575 * According to what downstream DTS says, 2576 * the entire power efficient cluster has 2577 * only a single thermal sensor. 2578 */ 2579 2580 pwr-cluster-thermal { 2581 polling-delay-passive = <250>; 2582 2583 thermal-sensors = <&tsens 7>; 2584 2585 trips { 2586 pwr_cluster_alert0: trip-point0 { 2587 temperature = <70000>; 2588 hysteresis = <1000>; 2589 type = "passive"; 2590 }; 2591 2592 pwr_cluster_crit: cpu-crit { 2593 temperature = <110000>; 2594 hysteresis = <1000>; 2595 type = "critical"; 2596 }; 2597 }; 2598 }; 2599 2600 gpu-thermal { 2601 polling-delay-passive = <250>; 2602 2603 thermal-sensors = <&tsens 8>; 2604 2605 cooling-maps { 2606 map0 { 2607 trip = <&gpu_alert0>; 2608 cooling-device = <&adreno_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2609 }; 2610 }; 2611 2612 trips { 2613 gpu_alert0: trip-point0 { 2614 temperature = <85000>; 2615 hysteresis = <1000>; 2616 type = "passive"; 2617 }; 2618 2619 trip-point1 { 2620 temperature = <90000>; 2621 hysteresis = <1000>; 2622 type = "hot"; 2623 }; 2624 2625 trip-point2 { 2626 temperature = <110000>; 2627 hysteresis = <1000>; 2628 type = "critical"; 2629 }; 2630 }; 2631 }; 2632 }; 2633 2634 timer { 2635 compatible = "arm,armv8-timer"; 2636 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2637 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2638 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2639 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2640 }; 2641}; 2642 2643