1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> 8#include <dt-bindings/clock/qcom,gcc-sc8280xp.h> 9#include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> 10#include <dt-bindings/clock/qcom,rpmh.h> 11#include <dt-bindings/clock/qcom,sc8280xp-camcc.h> 12#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> 13#include <dt-bindings/interconnect/qcom,osm-l3.h> 14#include <dt-bindings/interconnect/qcom,sc8280xp.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/mailbox/qcom-ipcc.h> 17#include <dt-bindings/phy/phy-qcom-qmp.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/soc/qcom,gpr.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/sound/qcom,q6afe.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 }; 35 36 sleep_clk: sleep-clk { 37 compatible = "fixed-clock"; 38 #clock-cells = <0>; 39 clock-frequency = <32764>; 40 }; 41 }; 42 43 cpus { 44 #address-cells = <2>; 45 #size-cells = <0>; 46 47 cpu0: cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a78c"; 50 reg = <0x0 0x0>; 51 clocks = <&cpufreq_hw 0>; 52 enable-method = "psci"; 53 capacity-dmips-mhz = <981>; 54 dynamic-power-coefficient = <549>; 55 next-level-cache = <&l2_0>; 56 power-domains = <&cpu_pd0>; 57 power-domain-names = "psci"; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 61 #cooling-cells = <2>; 62 l2_0: l2-cache { 63 compatible = "cache"; 64 cache-level = <2>; 65 cache-unified; 66 next-level-cache = <&l3_0>; 67 l3_0: l3-cache { 68 compatible = "cache"; 69 cache-level = <3>; 70 cache-unified; 71 }; 72 }; 73 }; 74 75 cpu1: cpu@100 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a78c"; 78 reg = <0x0 0x100>; 79 clocks = <&cpufreq_hw 0>; 80 enable-method = "psci"; 81 capacity-dmips-mhz = <981>; 82 dynamic-power-coefficient = <549>; 83 next-level-cache = <&l2_100>; 84 power-domains = <&cpu_pd1>; 85 power-domain-names = "psci"; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 89 #cooling-cells = <2>; 90 l2_100: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a78c"; 101 reg = <0x0 0x200>; 102 clocks = <&cpufreq_hw 0>; 103 enable-method = "psci"; 104 capacity-dmips-mhz = <981>; 105 dynamic-power-coefficient = <549>; 106 next-level-cache = <&l2_200>; 107 power-domains = <&cpu_pd2>; 108 power-domain-names = "psci"; 109 qcom,freq-domain = <&cpufreq_hw 0>; 110 operating-points-v2 = <&cpu0_opp_table>; 111 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 112 #cooling-cells = <2>; 113 l2_200: l2-cache { 114 compatible = "cache"; 115 cache-level = <2>; 116 cache-unified; 117 next-level-cache = <&l3_0>; 118 }; 119 }; 120 121 cpu3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a78c"; 124 reg = <0x0 0x300>; 125 clocks = <&cpufreq_hw 0>; 126 enable-method = "psci"; 127 capacity-dmips-mhz = <981>; 128 dynamic-power-coefficient = <549>; 129 next-level-cache = <&l2_300>; 130 power-domains = <&cpu_pd3>; 131 power-domain-names = "psci"; 132 qcom,freq-domain = <&cpufreq_hw 0>; 133 operating-points-v2 = <&cpu0_opp_table>; 134 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 135 #cooling-cells = <2>; 136 l2_300: l2-cache { 137 compatible = "cache"; 138 cache-level = <2>; 139 cache-unified; 140 next-level-cache = <&l3_0>; 141 }; 142 }; 143 144 cpu4: cpu@400 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-x1c"; 147 reg = <0x0 0x400>; 148 clocks = <&cpufreq_hw 1>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <1024>; 151 dynamic-power-coefficient = <590>; 152 next-level-cache = <&l2_400>; 153 power-domains = <&cpu_pd4>; 154 power-domain-names = "psci"; 155 qcom,freq-domain = <&cpufreq_hw 1>; 156 operating-points-v2 = <&cpu4_opp_table>; 157 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 158 #cooling-cells = <2>; 159 l2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&l3_0>; 164 }; 165 }; 166 167 cpu5: cpu@500 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-x1c"; 170 reg = <0x0 0x500>; 171 clocks = <&cpufreq_hw 1>; 172 enable-method = "psci"; 173 capacity-dmips-mhz = <1024>; 174 dynamic-power-coefficient = <590>; 175 next-level-cache = <&l2_500>; 176 power-domains = <&cpu_pd5>; 177 power-domain-names = "psci"; 178 qcom,freq-domain = <&cpufreq_hw 1>; 179 operating-points-v2 = <&cpu4_opp_table>; 180 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 181 #cooling-cells = <2>; 182 l2_500: l2-cache { 183 compatible = "cache"; 184 cache-level = <2>; 185 cache-unified; 186 next-level-cache = <&l3_0>; 187 }; 188 }; 189 190 cpu6: cpu@600 { 191 device_type = "cpu"; 192 compatible = "arm,cortex-x1c"; 193 reg = <0x0 0x600>; 194 clocks = <&cpufreq_hw 1>; 195 enable-method = "psci"; 196 capacity-dmips-mhz = <1024>; 197 dynamic-power-coefficient = <590>; 198 next-level-cache = <&l2_600>; 199 power-domains = <&cpu_pd6>; 200 power-domain-names = "psci"; 201 qcom,freq-domain = <&cpufreq_hw 1>; 202 operating-points-v2 = <&cpu4_opp_table>; 203 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 204 #cooling-cells = <2>; 205 l2_600: l2-cache { 206 compatible = "cache"; 207 cache-level = <2>; 208 cache-unified; 209 next-level-cache = <&l3_0>; 210 }; 211 }; 212 213 cpu7: cpu@700 { 214 device_type = "cpu"; 215 compatible = "arm,cortex-x1c"; 216 reg = <0x0 0x700>; 217 clocks = <&cpufreq_hw 1>; 218 enable-method = "psci"; 219 capacity-dmips-mhz = <1024>; 220 dynamic-power-coefficient = <590>; 221 next-level-cache = <&l2_700>; 222 power-domains = <&cpu_pd7>; 223 power-domain-names = "psci"; 224 qcom,freq-domain = <&cpufreq_hw 1>; 225 operating-points-v2 = <&cpu4_opp_table>; 226 interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 227 #cooling-cells = <2>; 228 l2_700: l2-cache { 229 compatible = "cache"; 230 cache-level = <2>; 231 cache-unified; 232 next-level-cache = <&l3_0>; 233 }; 234 }; 235 236 cpu-map { 237 cluster0 { 238 core0 { 239 cpu = <&cpu0>; 240 }; 241 242 core1 { 243 cpu = <&cpu1>; 244 }; 245 246 core2 { 247 cpu = <&cpu2>; 248 }; 249 250 core3 { 251 cpu = <&cpu3>; 252 }; 253 254 core4 { 255 cpu = <&cpu4>; 256 }; 257 258 core5 { 259 cpu = <&cpu5>; 260 }; 261 262 core6 { 263 cpu = <&cpu6>; 264 }; 265 266 core7 { 267 cpu = <&cpu7>; 268 }; 269 }; 270 }; 271 272 idle-states { 273 entry-method = "psci"; 274 275 little_cpu_sleep_0: cpu-sleep-0-0 { 276 compatible = "arm,idle-state"; 277 idle-state-name = "little-rail-power-collapse"; 278 arm,psci-suspend-param = <0x40000004>; 279 entry-latency-us = <355>; 280 exit-latency-us = <909>; 281 min-residency-us = <3934>; 282 local-timer-stop; 283 }; 284 285 big_cpu_sleep_0: cpu-sleep-1-0 { 286 compatible = "arm,idle-state"; 287 idle-state-name = "big-rail-power-collapse"; 288 arm,psci-suspend-param = <0x40000004>; 289 entry-latency-us = <241>; 290 exit-latency-us = <1461>; 291 min-residency-us = <4488>; 292 local-timer-stop; 293 }; 294 }; 295 296 domain-idle-states { 297 cluster_sleep_0: cluster-sleep-0 { 298 compatible = "domain-idle-state"; 299 arm,psci-suspend-param = <0x4100c344>; 300 entry-latency-us = <3263>; 301 exit-latency-us = <6562>; 302 min-residency-us = <9987>; 303 }; 304 }; 305 }; 306 307 firmware { 308 scm: scm { 309 compatible = "qcom,scm-sc8280xp", "qcom,scm"; 310 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 311 qcom,dload-mode = <&tcsr 0x13000>; 312 }; 313 }; 314 315 aggre1_noc: interconnect-aggre1-noc { 316 compatible = "qcom,sc8280xp-aggre1-noc"; 317 #interconnect-cells = <2>; 318 qcom,bcm-voters = <&apps_bcm_voter>; 319 }; 320 321 aggre2_noc: interconnect-aggre2-noc { 322 compatible = "qcom,sc8280xp-aggre2-noc"; 323 #interconnect-cells = <2>; 324 qcom,bcm-voters = <&apps_bcm_voter>; 325 }; 326 327 clk_virt: interconnect-clk-virt { 328 compatible = "qcom,sc8280xp-clk-virt"; 329 #interconnect-cells = <2>; 330 qcom,bcm-voters = <&apps_bcm_voter>; 331 }; 332 333 config_noc: interconnect-config-noc { 334 compatible = "qcom,sc8280xp-config-noc"; 335 #interconnect-cells = <2>; 336 qcom,bcm-voters = <&apps_bcm_voter>; 337 }; 338 339 dc_noc: interconnect-dc-noc { 340 compatible = "qcom,sc8280xp-dc-noc"; 341 #interconnect-cells = <2>; 342 qcom,bcm-voters = <&apps_bcm_voter>; 343 }; 344 345 gem_noc: interconnect-gem-noc { 346 compatible = "qcom,sc8280xp-gem-noc"; 347 #interconnect-cells = <2>; 348 qcom,bcm-voters = <&apps_bcm_voter>; 349 }; 350 351 lpass_noc: interconnect-lpass-ag-noc { 352 compatible = "qcom,sc8280xp-lpass-ag-noc"; 353 #interconnect-cells = <2>; 354 qcom,bcm-voters = <&apps_bcm_voter>; 355 }; 356 357 mc_virt: interconnect-mc-virt { 358 compatible = "qcom,sc8280xp-mc-virt"; 359 #interconnect-cells = <2>; 360 qcom,bcm-voters = <&apps_bcm_voter>; 361 }; 362 363 mmss_noc: interconnect-mmss-noc { 364 compatible = "qcom,sc8280xp-mmss-noc"; 365 #interconnect-cells = <2>; 366 qcom,bcm-voters = <&apps_bcm_voter>; 367 }; 368 369 nspa_noc: interconnect-nspa-noc { 370 compatible = "qcom,sc8280xp-nspa-noc"; 371 #interconnect-cells = <2>; 372 qcom,bcm-voters = <&apps_bcm_voter>; 373 }; 374 375 nspb_noc: interconnect-nspb-noc { 376 compatible = "qcom,sc8280xp-nspb-noc"; 377 #interconnect-cells = <2>; 378 qcom,bcm-voters = <&apps_bcm_voter>; 379 }; 380 381 system_noc: interconnect-system-noc { 382 compatible = "qcom,sc8280xp-system-noc"; 383 #interconnect-cells = <2>; 384 qcom,bcm-voters = <&apps_bcm_voter>; 385 }; 386 387 memory@80000000 { 388 device_type = "memory"; 389 /* We expect the bootloader to fill in the size */ 390 reg = <0x0 0x80000000 0x0 0x0>; 391 }; 392 393 cpu0_opp_table: opp-table-cpu0 { 394 compatible = "operating-points-v2"; 395 opp-shared; 396 397 opp-300000000 { 398 opp-hz = /bits/ 64 <300000000>; 399 opp-peak-kBps = <(300000 * 32)>; 400 }; 401 opp-403200000 { 402 opp-hz = /bits/ 64 <403200000>; 403 opp-peak-kBps = <(384000 * 32)>; 404 }; 405 opp-499200000 { 406 opp-hz = /bits/ 64 <499200000>; 407 opp-peak-kBps = <(480000 * 32)>; 408 }; 409 opp-595200000 { 410 opp-hz = /bits/ 64 <595200000>; 411 opp-peak-kBps = <(576000 * 32)>; 412 }; 413 opp-691200000 { 414 opp-hz = /bits/ 64 <691200000>; 415 opp-peak-kBps = <(672000 * 32)>; 416 }; 417 opp-806400000 { 418 opp-hz = /bits/ 64 <806400000>; 419 opp-peak-kBps = <(768000 * 32)>; 420 }; 421 opp-902400000 { 422 opp-hz = /bits/ 64 <902400000>; 423 opp-peak-kBps = <(864000 * 32)>; 424 }; 425 opp-1017600000 { 426 opp-hz = /bits/ 64 <1017600000>; 427 opp-peak-kBps = <(960000 * 32)>; 428 }; 429 opp-1113600000 { 430 opp-hz = /bits/ 64 <1113600000>; 431 opp-peak-kBps = <(1075200 * 32)>; 432 }; 433 opp-1209600000 { 434 opp-hz = /bits/ 64 <1209600000>; 435 opp-peak-kBps = <(1171200 * 32)>; 436 }; 437 opp-1324800000 { 438 opp-hz = /bits/ 64 <1324800000>; 439 opp-peak-kBps = <(1267200 * 32)>; 440 }; 441 opp-1440000000 { 442 opp-hz = /bits/ 64 <1440000000>; 443 opp-peak-kBps = <(1363200 * 32)>; 444 }; 445 opp-1555200000 { 446 opp-hz = /bits/ 64 <1555200000>; 447 opp-peak-kBps = <(1536000 * 32)>; 448 }; 449 opp-1670400000 { 450 opp-hz = /bits/ 64 <1670400000>; 451 opp-peak-kBps = <(1612800 * 32)>; 452 }; 453 opp-1785600000 { 454 opp-hz = /bits/ 64 <1785600000>; 455 opp-peak-kBps = <(1689600 * 32)>; 456 }; 457 opp-1881600000 { 458 opp-hz = /bits/ 64 <1881600000>; 459 opp-peak-kBps = <(1689600 * 32)>; 460 }; 461 opp-1996800000 { 462 opp-hz = /bits/ 64 <1996800000>; 463 opp-peak-kBps = <(1689600 * 32)>; 464 }; 465 opp-2112000000 { 466 opp-hz = /bits/ 64 <2112000000>; 467 opp-peak-kBps = <(1689600 * 32)>; 468 }; 469 opp-2227200000 { 470 opp-hz = /bits/ 64 <2227200000>; 471 opp-peak-kBps = <(1689600 * 32)>; 472 }; 473 opp-2342400000 { 474 opp-hz = /bits/ 64 <2342400000>; 475 opp-peak-kBps = <(1689600 * 32)>; 476 }; 477 opp-2438400000 { 478 opp-hz = /bits/ 64 <2438400000>; 479 opp-peak-kBps = <(1689600 * 32)>; 480 }; 481 }; 482 483 cpu4_opp_table: opp-table-cpu4 { 484 compatible = "operating-points-v2"; 485 opp-shared; 486 487 opp-825600000 { 488 opp-hz = /bits/ 64 <825600000>; 489 opp-peak-kBps = <(768000 * 32)>; 490 }; 491 opp-940800000 { 492 opp-hz = /bits/ 64 <940800000>; 493 opp-peak-kBps = <(864000 * 32)>; 494 }; 495 opp-1056000000 { 496 opp-hz = /bits/ 64 <1056000000>; 497 opp-peak-kBps = <(960000 * 32)>; 498 }; 499 opp-1171200000 { 500 opp-hz = /bits/ 64 <1171200000>; 501 opp-peak-kBps = <(1171200 * 32)>; 502 }; 503 opp-1286400000 { 504 opp-hz = /bits/ 64 <1286400000>; 505 opp-peak-kBps = <(1267200 * 32)>; 506 }; 507 opp-1401600000 { 508 opp-hz = /bits/ 64 <1401600000>; 509 opp-peak-kBps = <(1363200 * 32)>; 510 }; 511 opp-1516800000 { 512 opp-hz = /bits/ 64 <1516800000>; 513 opp-peak-kBps = <(1459200 * 32)>; 514 }; 515 opp-1632000000 { 516 opp-hz = /bits/ 64 <1632000000>; 517 opp-peak-kBps = <(1612800 * 32)>; 518 }; 519 opp-1747200000 { 520 opp-hz = /bits/ 64 <1747200000>; 521 opp-peak-kBps = <(1689600 * 32)>; 522 }; 523 opp-1862400000 { 524 opp-hz = /bits/ 64 <1862400000>; 525 opp-peak-kBps = <(1689600 * 32)>; 526 }; 527 opp-1977600000 { 528 opp-hz = /bits/ 64 <1977600000>; 529 opp-peak-kBps = <(1689600 * 32)>; 530 }; 531 opp-2073600000 { 532 opp-hz = /bits/ 64 <2073600000>; 533 opp-peak-kBps = <(1689600 * 32)>; 534 }; 535 opp-2169600000 { 536 opp-hz = /bits/ 64 <2169600000>; 537 opp-peak-kBps = <(1689600 * 32)>; 538 }; 539 opp-2284800000 { 540 opp-hz = /bits/ 64 <2284800000>; 541 opp-peak-kBps = <(1689600 * 32)>; 542 }; 543 opp-2400000000 { 544 opp-hz = /bits/ 64 <2400000000>; 545 opp-peak-kBps = <(1689600 * 32)>; 546 }; 547 opp-2496000000 { 548 opp-hz = /bits/ 64 <2496000000>; 549 opp-peak-kBps = <(1689600 * 32)>; 550 }; 551 opp-2592000000 { 552 opp-hz = /bits/ 64 <2592000000>; 553 opp-peak-kBps = <(1689600 * 32)>; 554 }; 555 opp-2688000000 { 556 opp-hz = /bits/ 64 <2688000000>; 557 opp-peak-kBps = <(1689600 * 32)>; 558 }; 559 opp-2803200000 { 560 opp-hz = /bits/ 64 <2803200000>; 561 opp-peak-kBps = <(1689600 * 32)>; 562 }; 563 opp-2899200000 { 564 opp-hz = /bits/ 64 <2899200000>; 565 opp-peak-kBps = <(1689600 * 32)>; 566 }; 567 opp-2995200000 { 568 opp-hz = /bits/ 64 <2995200000>; 569 opp-peak-kBps = <(1689600 * 32)>; 570 }; 571 }; 572 573 qup_opp_table_100mhz: opp-table-qup100mhz { 574 compatible = "operating-points-v2"; 575 576 opp-75000000 { 577 opp-hz = /bits/ 64 <75000000>; 578 required-opps = <&rpmhpd_opp_low_svs>; 579 }; 580 581 opp-100000000 { 582 opp-hz = /bits/ 64 <100000000>; 583 required-opps = <&rpmhpd_opp_svs>; 584 }; 585 }; 586 587 pmu { 588 compatible = "arm,armv8-pmuv3"; 589 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 590 }; 591 592 psci { 593 compatible = "arm,psci-1.0"; 594 method = "smc"; 595 596 cpu_pd0: power-domain-cpu0 { 597 #power-domain-cells = <0>; 598 power-domains = <&cluster_pd>; 599 domain-idle-states = <&little_cpu_sleep_0>; 600 }; 601 602 cpu_pd1: power-domain-cpu1 { 603 #power-domain-cells = <0>; 604 power-domains = <&cluster_pd>; 605 domain-idle-states = <&little_cpu_sleep_0>; 606 }; 607 608 cpu_pd2: power-domain-cpu2 { 609 #power-domain-cells = <0>; 610 power-domains = <&cluster_pd>; 611 domain-idle-states = <&little_cpu_sleep_0>; 612 }; 613 614 cpu_pd3: power-domain-cpu3 { 615 #power-domain-cells = <0>; 616 power-domains = <&cluster_pd>; 617 domain-idle-states = <&little_cpu_sleep_0>; 618 }; 619 620 cpu_pd4: power-domain-cpu4 { 621 #power-domain-cells = <0>; 622 power-domains = <&cluster_pd>; 623 domain-idle-states = <&big_cpu_sleep_0>; 624 }; 625 626 cpu_pd5: power-domain-cpu5 { 627 #power-domain-cells = <0>; 628 power-domains = <&cluster_pd>; 629 domain-idle-states = <&big_cpu_sleep_0>; 630 }; 631 632 cpu_pd6: power-domain-cpu6 { 633 #power-domain-cells = <0>; 634 power-domains = <&cluster_pd>; 635 domain-idle-states = <&big_cpu_sleep_0>; 636 }; 637 638 cpu_pd7: power-domain-cpu7 { 639 #power-domain-cells = <0>; 640 power-domains = <&cluster_pd>; 641 domain-idle-states = <&big_cpu_sleep_0>; 642 }; 643 644 cluster_pd: power-domain-cpu-cluster0 { 645 #power-domain-cells = <0>; 646 domain-idle-states = <&cluster_sleep_0>; 647 }; 648 }; 649 650 reserved-memory { 651 #address-cells = <2>; 652 #size-cells = <2>; 653 ranges; 654 655 reserved-region@80000000 { 656 reg = <0 0x80000000 0 0x860000>; 657 no-map; 658 }; 659 660 cmd_db: cmd-db-region@80860000 { 661 compatible = "qcom,cmd-db"; 662 reg = <0 0x80860000 0 0x20000>; 663 no-map; 664 }; 665 666 reserved-region@80880000 { 667 reg = <0 0x80880000 0 0x80000>; 668 no-map; 669 }; 670 671 smem_mem: smem-region@80900000 { 672 compatible = "qcom,smem"; 673 reg = <0 0x80900000 0 0x200000>; 674 no-map; 675 hwlocks = <&tcsr_mutex 3>; 676 }; 677 678 reserved-region@80b00000 { 679 reg = <0 0x80b00000 0 0x100000>; 680 no-map; 681 }; 682 683 reserved-region@83b00000 { 684 reg = <0 0x83b00000 0 0x1700000>; 685 no-map; 686 }; 687 688 reserved-region@85b00000 { 689 reg = <0 0x85b00000 0 0xc00000>; 690 no-map; 691 }; 692 693 pil_adsp_mem: adsp-region@86c00000 { 694 reg = <0 0x86c00000 0 0x2000000>; 695 no-map; 696 }; 697 698 pil_nsp0_mem: cdsp0-region@8a100000 { 699 reg = <0 0x8a100000 0 0x1e00000>; 700 no-map; 701 }; 702 703 pil_nsp1_mem: cdsp1-region@8c600000 { 704 reg = <0 0x8c600000 0 0x1e00000>; 705 no-map; 706 }; 707 708 reserved-region@aeb00000 { 709 reg = <0 0xaeb00000 0 0x16600000>; 710 no-map; 711 }; 712 }; 713 714 smp2p-adsp { 715 compatible = "qcom,smp2p"; 716 qcom,smem = <443>, <429>; 717 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 718 IPCC_MPROC_SIGNAL_SMP2P 719 IRQ_TYPE_EDGE_RISING>; 720 mboxes = <&ipcc IPCC_CLIENT_LPASS 721 IPCC_MPROC_SIGNAL_SMP2P>; 722 723 qcom,local-pid = <0>; 724 qcom,remote-pid = <2>; 725 726 smp2p_adsp_out: master-kernel { 727 qcom,entry-name = "master-kernel"; 728 #qcom,smem-state-cells = <1>; 729 }; 730 731 smp2p_adsp_in: slave-kernel { 732 qcom,entry-name = "slave-kernel"; 733 interrupt-controller; 734 #interrupt-cells = <2>; 735 }; 736 }; 737 738 smp2p-nsp0 { 739 compatible = "qcom,smp2p"; 740 qcom,smem = <94>, <432>; 741 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 742 IPCC_MPROC_SIGNAL_SMP2P 743 IRQ_TYPE_EDGE_RISING>; 744 mboxes = <&ipcc IPCC_CLIENT_CDSP 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,local-pid = <0>; 748 qcom,remote-pid = <5>; 749 750 smp2p_nsp0_out: master-kernel { 751 qcom,entry-name = "master-kernel"; 752 #qcom,smem-state-cells = <1>; 753 }; 754 755 smp2p_nsp0_in: slave-kernel { 756 qcom,entry-name = "slave-kernel"; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 }; 761 762 smp2p-nsp1 { 763 compatible = "qcom,smp2p"; 764 qcom,smem = <617>, <616>; 765 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 766 IPCC_MPROC_SIGNAL_SMP2P 767 IRQ_TYPE_EDGE_RISING>; 768 mboxes = <&ipcc IPCC_CLIENT_NSP1 769 IPCC_MPROC_SIGNAL_SMP2P>; 770 771 qcom,local-pid = <0>; 772 qcom,remote-pid = <12>; 773 774 smp2p_nsp1_out: master-kernel { 775 qcom,entry-name = "master-kernel"; 776 #qcom,smem-state-cells = <1>; 777 }; 778 779 smp2p_nsp1_in: slave-kernel { 780 qcom,entry-name = "slave-kernel"; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 }; 784 }; 785 786 soc: soc@0 { 787 compatible = "simple-bus"; 788 #address-cells = <2>; 789 #size-cells = <2>; 790 ranges = <0 0 0 0 0x10 0>; 791 dma-ranges = <0 0 0 0 0x10 0>; 792 793 ethernet0: ethernet@20000 { 794 compatible = "qcom,sc8280xp-ethqos"; 795 reg = <0x0 0x00020000 0x0 0x10000>, 796 <0x0 0x00036000 0x0 0x100>; 797 reg-names = "stmmaceth", "rgmii"; 798 799 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 800 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 801 <&gcc GCC_EMAC0_PTP_CLK>, 802 <&gcc GCC_EMAC0_RGMII_CLK>; 803 clock-names = "stmmaceth", 804 "pclk", 805 "ptp_ref", 806 "rgmii"; 807 808 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; 810 interrupt-names = "macirq", "eth_lpi"; 811 812 iommus = <&apps_smmu 0x4c0 0xf>; 813 power-domains = <&gcc EMAC_0_GDSC>; 814 815 snps,tso; 816 snps,pbl = <32>; 817 rx-fifo-depth = <4096>; 818 tx-fifo-depth = <4096>; 819 820 status = "disabled"; 821 }; 822 823 gcc: clock-controller@100000 { 824 compatible = "qcom,gcc-sc8280xp"; 825 reg = <0x0 0x00100000 0x0 0x1f0000>; 826 #clock-cells = <1>; 827 #reset-cells = <1>; 828 #power-domain-cells = <1>; 829 clocks = <&rpmhcc RPMH_CXO_CLK>, 830 <&sleep_clk>, 831 <0>, 832 <0>, 833 <0>, 834 <0>, 835 <0>, 836 <0>, 837 <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 838 <0>, 839 <0>, 840 <0>, 841 <0>, 842 <0>, 843 <0>, 844 <0>, 845 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, 846 <0>, 847 <0>, 848 <0>, 849 <0>, 850 <0>, 851 <0>, 852 <0>, 853 <0>, 854 <0>, 855 <&pcie2a_phy>, 856 <&pcie2b_phy>, 857 <&pcie3a_phy>, 858 <&pcie3b_phy>, 859 <&pcie4_phy>, 860 <0>, 861 <0>; 862 power-domains = <&rpmhpd SC8280XP_CX>; 863 }; 864 865 ipcc: mailbox@408000 { 866 compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; 867 reg = <0 0x00408000 0 0x1000>; 868 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-controller; 870 #interrupt-cells = <3>; 871 #mbox-cells = <2>; 872 }; 873 874 qfprom: efuse@784000 { 875 compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; 876 reg = <0 0x00784000 0 0x3000>; 877 #address-cells = <1>; 878 #size-cells = <1>; 879 880 gpu_speed_bin: gpu-speed-bin@18b { 881 reg = <0x18b 0x1>; 882 bits = <5 3>; 883 }; 884 }; 885 886 qup2: geniqup@8c0000 { 887 compatible = "qcom,geni-se-qup"; 888 reg = <0 0x008c0000 0 0x2000>; 889 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 890 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 891 clock-names = "m-ahb", "s-ahb"; 892 iommus = <&apps_smmu 0xa3 0>; 893 894 #address-cells = <2>; 895 #size-cells = <2>; 896 ranges; 897 898 status = "disabled"; 899 900 i2c16: i2c@880000 { 901 compatible = "qcom,geni-i2c"; 902 reg = <0 0x00880000 0 0x4000>; 903 #address-cells = <1>; 904 #size-cells = <0>; 905 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 906 clock-names = "se"; 907 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 908 power-domains = <&rpmhpd SC8280XP_CX>; 909 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 910 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 911 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 912 interconnect-names = "qup-core", "qup-config", "qup-memory"; 913 status = "disabled"; 914 }; 915 916 spi16: spi@880000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00880000 0 0x4000>; 919 #address-cells = <1>; 920 #size-cells = <0>; 921 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 922 clock-names = "se"; 923 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 924 power-domains = <&rpmhpd SC8280XP_CX>; 925 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 926 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 927 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 928 interconnect-names = "qup-core", "qup-config", "qup-memory"; 929 status = "disabled"; 930 }; 931 932 i2c17: i2c@884000 { 933 compatible = "qcom,geni-i2c"; 934 reg = <0 0x00884000 0 0x4000>; 935 #address-cells = <1>; 936 #size-cells = <0>; 937 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 938 clock-names = "se"; 939 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 940 power-domains = <&rpmhpd SC8280XP_CX>; 941 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 942 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 943 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 944 interconnect-names = "qup-core", "qup-config", "qup-memory"; 945 status = "disabled"; 946 }; 947 948 spi17: spi@884000 { 949 compatible = "qcom,geni-spi"; 950 reg = <0 0x00884000 0 0x4000>; 951 #address-cells = <1>; 952 #size-cells = <0>; 953 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 954 clock-names = "se"; 955 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 956 power-domains = <&rpmhpd SC8280XP_CX>; 957 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 958 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 959 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 960 interconnect-names = "qup-core", "qup-config", "qup-memory"; 961 status = "disabled"; 962 }; 963 964 uart17: serial@884000 { 965 compatible = "qcom,geni-uart"; 966 reg = <0 0x00884000 0 0x4000>; 967 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 968 clock-names = "se"; 969 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 970 operating-points-v2 = <&qup_opp_table_100mhz>; 971 power-domains = <&rpmhpd SC8280XP_CX>; 972 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 973 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 974 interconnect-names = "qup-core", "qup-config"; 975 status = "disabled"; 976 }; 977 978 i2c18: i2c@888000 { 979 compatible = "qcom,geni-i2c"; 980 reg = <0 0x00888000 0 0x4000>; 981 #address-cells = <1>; 982 #size-cells = <0>; 983 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 984 clock-names = "se"; 985 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 986 power-domains = <&rpmhpd SC8280XP_CX>; 987 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 989 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 990 interconnect-names = "qup-core", "qup-config", "qup-memory"; 991 status = "disabled"; 992 }; 993 994 spi18: spi@888000 { 995 compatible = "qcom,geni-spi"; 996 reg = <0 0x00888000 0 0x4000>; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1000 clock-names = "se"; 1001 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1002 power-domains = <&rpmhpd SC8280XP_CX>; 1003 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1005 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1006 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1007 status = "disabled"; 1008 }; 1009 1010 uart18: serial@888000 { 1011 compatible = "qcom,geni-uart"; 1012 reg = <0 0x00888000 0 0x4000>; 1013 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1014 clock-names = "se"; 1015 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1016 operating-points-v2 = <&qup_opp_table_100mhz>; 1017 power-domains = <&rpmhpd SC8280XP_CX>; 1018 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1019 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; 1020 interconnect-names = "qup-core", "qup-config"; 1021 1022 pinctrl-0 = <&qup_uart18_default>; 1023 pinctrl-names = "default"; 1024 1025 status = "disabled"; 1026 }; 1027 1028 i2c19: i2c@88c000 { 1029 compatible = "qcom,geni-i2c"; 1030 reg = <0 0x0088c000 0 0x4000>; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1034 clock-names = "se"; 1035 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1036 power-domains = <&rpmhpd SC8280XP_CX>; 1037 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1038 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1039 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1040 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1041 status = "disabled"; 1042 }; 1043 1044 spi19: spi@88c000 { 1045 compatible = "qcom,geni-spi"; 1046 reg = <0 0x0088c000 0 0x4000>; 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1050 clock-names = "se"; 1051 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1052 power-domains = <&rpmhpd SC8280XP_CX>; 1053 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1054 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1055 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 status = "disabled"; 1058 }; 1059 1060 i2c20: i2c@890000 { 1061 compatible = "qcom,geni-i2c"; 1062 reg = <0 0x00890000 0 0x4000>; 1063 #address-cells = <1>; 1064 #size-cells = <0>; 1065 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1066 clock-names = "se"; 1067 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1068 power-domains = <&rpmhpd SC8280XP_CX>; 1069 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1070 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1071 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1072 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1073 status = "disabled"; 1074 }; 1075 1076 spi20: spi@890000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00890000 0 0x4000>; 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1082 clock-names = "se"; 1083 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1084 power-domains = <&rpmhpd SC8280XP_CX>; 1085 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1086 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1087 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1088 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1089 status = "disabled"; 1090 }; 1091 1092 i2c21: i2c@894000 { 1093 compatible = "qcom,geni-i2c"; 1094 reg = <0 0x00894000 0 0x4000>; 1095 clock-names = "se"; 1096 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1097 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 power-domains = <&rpmhpd SC8280XP_CX>; 1101 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1102 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1103 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1104 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1105 status = "disabled"; 1106 }; 1107 1108 spi21: spi@894000 { 1109 compatible = "qcom,geni-spi"; 1110 reg = <0 0x00894000 0 0x4000>; 1111 #address-cells = <1>; 1112 #size-cells = <0>; 1113 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1114 clock-names = "se"; 1115 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1116 power-domains = <&rpmhpd SC8280XP_CX>; 1117 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1118 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1119 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1120 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1121 status = "disabled"; 1122 }; 1123 1124 i2c22: i2c@898000 { 1125 compatible = "qcom,geni-i2c"; 1126 reg = <0 0x00898000 0 0x4000>; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1131 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1132 power-domains = <&rpmhpd SC8280XP_CX>; 1133 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1134 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1135 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1136 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1137 status = "disabled"; 1138 }; 1139 1140 spi22: spi@898000 { 1141 compatible = "qcom,geni-spi"; 1142 reg = <0 0x00898000 0 0x4000>; 1143 #address-cells = <1>; 1144 #size-cells = <0>; 1145 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1146 clock-names = "se"; 1147 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1148 power-domains = <&rpmhpd SC8280XP_CX>; 1149 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1150 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1151 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1152 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1153 status = "disabled"; 1154 }; 1155 1156 i2c23: i2c@89c000 { 1157 compatible = "qcom,geni-i2c"; 1158 reg = <0 0x0089c000 0 0x4000>; 1159 #address-cells = <1>; 1160 #size-cells = <0>; 1161 clock-names = "se"; 1162 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1163 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1164 power-domains = <&rpmhpd SC8280XP_CX>; 1165 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1166 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1167 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1168 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1169 status = "disabled"; 1170 }; 1171 1172 spi23: spi@89c000 { 1173 compatible = "qcom,geni-spi"; 1174 reg = <0 0x0089c000 0 0x4000>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1178 clock-names = "se"; 1179 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1180 power-domains = <&rpmhpd SC8280XP_CX>; 1181 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, 1182 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, 1183 <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; 1184 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1185 status = "disabled"; 1186 }; 1187 }; 1188 1189 qup0: geniqup@9c0000 { 1190 compatible = "qcom,geni-se-qup"; 1191 reg = <0 0x009c0000 0 0x6000>; 1192 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1193 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1194 clock-names = "m-ahb", "s-ahb"; 1195 iommus = <&apps_smmu 0x563 0>; 1196 1197 #address-cells = <2>; 1198 #size-cells = <2>; 1199 ranges; 1200 1201 status = "disabled"; 1202 1203 i2c0: i2c@980000 { 1204 compatible = "qcom,geni-i2c"; 1205 reg = <0 0x00980000 0 0x4000>; 1206 #address-cells = <1>; 1207 #size-cells = <0>; 1208 clock-names = "se"; 1209 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1210 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1211 power-domains = <&rpmhpd SC8280XP_CX>; 1212 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1213 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1214 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1215 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1216 status = "disabled"; 1217 }; 1218 1219 spi0: spi@980000 { 1220 compatible = "qcom,geni-spi"; 1221 reg = <0 0x00980000 0 0x4000>; 1222 #address-cells = <1>; 1223 #size-cells = <0>; 1224 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 1225 clock-names = "se"; 1226 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1227 power-domains = <&rpmhpd SC8280XP_CX>; 1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1229 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1230 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1231 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1232 status = "disabled"; 1233 }; 1234 1235 i2c1: i2c@984000 { 1236 compatible = "qcom,geni-i2c"; 1237 reg = <0 0x00984000 0 0x4000>; 1238 #address-cells = <1>; 1239 #size-cells = <0>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1242 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1243 power-domains = <&rpmhpd SC8280XP_CX>; 1244 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1245 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1246 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1247 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1248 status = "disabled"; 1249 }; 1250 1251 spi1: spi@984000 { 1252 compatible = "qcom,geni-spi"; 1253 reg = <0 0x00984000 0 0x4000>; 1254 #address-cells = <1>; 1255 #size-cells = <0>; 1256 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 1257 clock-names = "se"; 1258 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1259 power-domains = <&rpmhpd SC8280XP_CX>; 1260 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1261 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1262 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1263 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1264 status = "disabled"; 1265 }; 1266 1267 i2c2: i2c@988000 { 1268 compatible = "qcom,geni-i2c"; 1269 reg = <0 0x00988000 0 0x4000>; 1270 #address-cells = <1>; 1271 #size-cells = <0>; 1272 clock-names = "se"; 1273 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1274 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1275 power-domains = <&rpmhpd SC8280XP_CX>; 1276 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1277 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1278 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1279 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1280 status = "disabled"; 1281 }; 1282 1283 spi2: spi@988000 { 1284 compatible = "qcom,geni-spi"; 1285 reg = <0 0x00988000 0 0x4000>; 1286 #address-cells = <1>; 1287 #size-cells = <0>; 1288 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 1289 clock-names = "se"; 1290 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1291 power-domains = <&rpmhpd SC8280XP_CX>; 1292 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1293 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1294 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1295 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1296 status = "disabled"; 1297 }; 1298 1299 uart2: serial@988000 { 1300 compatible = "qcom,geni-uart"; 1301 reg = <0 0x00988000 0 0x4000>; 1302 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1303 clock-names = "se"; 1304 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1305 operating-points-v2 = <&qup_opp_table_100mhz>; 1306 power-domains = <&rpmhpd SC8280XP_CX>; 1307 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1308 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; 1309 interconnect-names = "qup-core", "qup-config"; 1310 status = "disabled"; 1311 }; 1312 1313 i2c3: i2c@98c000 { 1314 compatible = "qcom,geni-i2c"; 1315 reg = <0 0x0098c000 0 0x4000>; 1316 #address-cells = <1>; 1317 #size-cells = <0>; 1318 clock-names = "se"; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1320 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1321 power-domains = <&rpmhpd SC8280XP_CX>; 1322 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1323 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1324 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1325 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1326 status = "disabled"; 1327 }; 1328 1329 spi3: spi@98c000 { 1330 compatible = "qcom,geni-spi"; 1331 reg = <0 0x0098c000 0 0x4000>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 1335 clock-names = "se"; 1336 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1337 power-domains = <&rpmhpd SC8280XP_CX>; 1338 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1339 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1340 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1341 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1342 status = "disabled"; 1343 }; 1344 1345 i2c4: i2c@990000 { 1346 compatible = "qcom,geni-i2c"; 1347 reg = <0 0x00990000 0 0x4000>; 1348 clock-names = "se"; 1349 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1350 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1351 #address-cells = <1>; 1352 #size-cells = <0>; 1353 power-domains = <&rpmhpd SC8280XP_CX>; 1354 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1355 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1356 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1357 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1358 status = "disabled"; 1359 }; 1360 1361 spi4: spi@990000 { 1362 compatible = "qcom,geni-spi"; 1363 reg = <0 0x00990000 0 0x4000>; 1364 #address-cells = <1>; 1365 #size-cells = <0>; 1366 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1367 clock-names = "se"; 1368 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1369 power-domains = <&rpmhpd SC8280XP_CX>; 1370 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1371 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1372 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1373 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1374 status = "disabled"; 1375 }; 1376 1377 i2c5: i2c@994000 { 1378 compatible = "qcom,geni-i2c"; 1379 reg = <0 0x00994000 0 0x4000>; 1380 #address-cells = <1>; 1381 #size-cells = <0>; 1382 clock-names = "se"; 1383 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1384 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1385 power-domains = <&rpmhpd SC8280XP_CX>; 1386 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1387 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1388 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1389 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1390 status = "disabled"; 1391 }; 1392 1393 spi5: spi@994000 { 1394 compatible = "qcom,geni-spi"; 1395 reg = <0 0x00994000 0 0x4000>; 1396 #address-cells = <1>; 1397 #size-cells = <0>; 1398 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1399 clock-names = "se"; 1400 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1401 power-domains = <&rpmhpd SC8280XP_CX>; 1402 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1403 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1404 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1405 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1406 status = "disabled"; 1407 }; 1408 1409 i2c6: i2c@998000 { 1410 compatible = "qcom,geni-i2c"; 1411 reg = <0 0x00998000 0 0x4000>; 1412 #address-cells = <1>; 1413 #size-cells = <0>; 1414 clock-names = "se"; 1415 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1416 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1417 power-domains = <&rpmhpd SC8280XP_CX>; 1418 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1419 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1420 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1421 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1422 status = "disabled"; 1423 }; 1424 1425 spi6: spi@998000 { 1426 compatible = "qcom,geni-spi"; 1427 reg = <0 0x00998000 0 0x4000>; 1428 #address-cells = <1>; 1429 #size-cells = <0>; 1430 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1431 clock-names = "se"; 1432 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1433 power-domains = <&rpmhpd SC8280XP_CX>; 1434 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1435 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1436 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1437 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1438 status = "disabled"; 1439 }; 1440 1441 i2c7: i2c@99c000 { 1442 compatible = "qcom,geni-i2c"; 1443 reg = <0 0x0099c000 0 0x4000>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 clock-names = "se"; 1447 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1448 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1449 power-domains = <&rpmhpd SC8280XP_CX>; 1450 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1451 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1452 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1453 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1454 status = "disabled"; 1455 }; 1456 1457 spi7: spi@99c000 { 1458 compatible = "qcom,geni-spi"; 1459 reg = <0 0x0099c000 0 0x4000>; 1460 #address-cells = <1>; 1461 #size-cells = <0>; 1462 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1463 clock-names = "se"; 1464 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1465 power-domains = <&rpmhpd SC8280XP_CX>; 1466 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1467 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, 1468 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1469 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1470 status = "disabled"; 1471 }; 1472 }; 1473 1474 qup1: geniqup@ac0000 { 1475 compatible = "qcom,geni-se-qup"; 1476 reg = <0 0x00ac0000 0 0x6000>; 1477 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1478 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1479 clock-names = "m-ahb", "s-ahb"; 1480 iommus = <&apps_smmu 0x83 0>; 1481 1482 #address-cells = <2>; 1483 #size-cells = <2>; 1484 ranges; 1485 1486 status = "disabled"; 1487 1488 i2c8: i2c@a80000 { 1489 compatible = "qcom,geni-i2c"; 1490 reg = <0 0x00a80000 0 0x4000>; 1491 #address-cells = <1>; 1492 #size-cells = <0>; 1493 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1494 clock-names = "se"; 1495 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1496 power-domains = <&rpmhpd SC8280XP_CX>; 1497 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1498 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1499 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1500 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1501 status = "disabled"; 1502 }; 1503 1504 spi8: spi@a80000 { 1505 compatible = "qcom,geni-spi"; 1506 reg = <0 0x00a80000 0 0x4000>; 1507 #address-cells = <1>; 1508 #size-cells = <0>; 1509 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1510 clock-names = "se"; 1511 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1512 power-domains = <&rpmhpd SC8280XP_CX>; 1513 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1514 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1515 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1516 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1517 status = "disabled"; 1518 }; 1519 1520 i2c9: i2c@a84000 { 1521 compatible = "qcom,geni-i2c"; 1522 reg = <0 0x00a84000 0 0x4000>; 1523 #address-cells = <1>; 1524 #size-cells = <0>; 1525 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1526 clock-names = "se"; 1527 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1528 power-domains = <&rpmhpd SC8280XP_CX>; 1529 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1530 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1531 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1532 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1533 status = "disabled"; 1534 }; 1535 1536 spi9: spi@a84000 { 1537 compatible = "qcom,geni-spi"; 1538 reg = <0 0x00a84000 0 0x4000>; 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1542 clock-names = "se"; 1543 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1544 power-domains = <&rpmhpd SC8280XP_CX>; 1545 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1546 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1547 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1548 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1549 status = "disabled"; 1550 }; 1551 1552 i2c10: i2c@a88000 { 1553 compatible = "qcom,geni-i2c"; 1554 reg = <0 0x00a88000 0 0x4000>; 1555 #address-cells = <1>; 1556 #size-cells = <0>; 1557 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1558 clock-names = "se"; 1559 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1560 power-domains = <&rpmhpd SC8280XP_CX>; 1561 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1562 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1563 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1564 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1565 status = "disabled"; 1566 }; 1567 1568 spi10: spi@a88000 { 1569 compatible = "qcom,geni-spi"; 1570 reg = <0 0x00a88000 0 0x4000>; 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1574 clock-names = "se"; 1575 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1576 power-domains = <&rpmhpd SC8280XP_CX>; 1577 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1578 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1579 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1580 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1581 status = "disabled"; 1582 }; 1583 1584 i2c11: i2c@a8c000 { 1585 compatible = "qcom,geni-i2c"; 1586 reg = <0 0x00a8c000 0 0x4000>; 1587 #address-cells = <1>; 1588 #size-cells = <0>; 1589 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1590 clock-names = "se"; 1591 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1592 power-domains = <&rpmhpd SC8280XP_CX>; 1593 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1594 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1595 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1596 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1597 status = "disabled"; 1598 }; 1599 1600 spi11: spi@a8c000 { 1601 compatible = "qcom,geni-spi"; 1602 reg = <0 0x00a8c000 0 0x4000>; 1603 #address-cells = <1>; 1604 #size-cells = <0>; 1605 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1606 clock-names = "se"; 1607 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1608 power-domains = <&rpmhpd SC8280XP_CX>; 1609 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1610 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1611 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1612 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1613 status = "disabled"; 1614 }; 1615 1616 i2c12: i2c@a90000 { 1617 compatible = "qcom,geni-i2c"; 1618 reg = <0 0x00a90000 0 0x4000>; 1619 #address-cells = <1>; 1620 #size-cells = <0>; 1621 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1622 clock-names = "se"; 1623 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1624 power-domains = <&rpmhpd SC8280XP_CX>; 1625 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1626 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1627 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1628 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1629 status = "disabled"; 1630 }; 1631 1632 spi12: spi@a90000 { 1633 compatible = "qcom,geni-spi"; 1634 reg = <0 0x00a90000 0 0x4000>; 1635 #address-cells = <1>; 1636 #size-cells = <0>; 1637 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1638 clock-names = "se"; 1639 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1640 power-domains = <&rpmhpd SC8280XP_CX>; 1641 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1642 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1643 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1644 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1645 status = "disabled"; 1646 }; 1647 1648 i2c13: i2c@a94000 { 1649 compatible = "qcom,geni-i2c"; 1650 reg = <0 0x00a94000 0 0x4000>; 1651 #address-cells = <1>; 1652 #size-cells = <0>; 1653 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1654 clock-names = "se"; 1655 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1656 power-domains = <&rpmhpd SC8280XP_CX>; 1657 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1658 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1659 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1660 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1661 status = "disabled"; 1662 }; 1663 1664 spi13: spi@a94000 { 1665 compatible = "qcom,geni-spi"; 1666 reg = <0 0x00a94000 0 0x4000>; 1667 #address-cells = <1>; 1668 #size-cells = <0>; 1669 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1670 clock-names = "se"; 1671 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1672 power-domains = <&rpmhpd SC8280XP_CX>; 1673 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1674 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1675 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1676 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1677 status = "disabled"; 1678 }; 1679 1680 i2c14: i2c@a98000 { 1681 compatible = "qcom,geni-i2c"; 1682 reg = <0 0x00a98000 0 0x4000>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1686 clock-names = "se"; 1687 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1688 power-domains = <&rpmhpd SC8280XP_CX>; 1689 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1690 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1691 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1692 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1693 status = "disabled"; 1694 }; 1695 1696 spi14: spi@a98000 { 1697 compatible = "qcom,geni-spi"; 1698 reg = <0 0x00a98000 0 0x4000>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1702 clock-names = "se"; 1703 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1704 power-domains = <&rpmhpd SC8280XP_CX>; 1705 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1706 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1707 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1708 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1709 status = "disabled"; 1710 }; 1711 1712 i2c15: i2c@a9c000 { 1713 compatible = "qcom,geni-i2c"; 1714 reg = <0 0x00a9c000 0 0x4000>; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1718 clock-names = "se"; 1719 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1720 power-domains = <&rpmhpd SC8280XP_CX>; 1721 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1722 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1723 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1724 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1725 status = "disabled"; 1726 }; 1727 1728 spi15: spi@a9c000 { 1729 compatible = "qcom,geni-spi"; 1730 reg = <0 0x00a9c000 0 0x4000>; 1731 #address-cells = <1>; 1732 #size-cells = <0>; 1733 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1734 clock-names = "se"; 1735 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 1736 power-domains = <&rpmhpd SC8280XP_CX>; 1737 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1738 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, 1739 <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1740 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1741 status = "disabled"; 1742 }; 1743 }; 1744 1745 rng: rng@10d3000 { 1746 compatible = "qcom,prng-ee"; 1747 reg = <0 0x010d3000 0 0x1000>; 1748 clocks = <&rpmhcc RPMH_HWKM_CLK>; 1749 clock-names = "core"; 1750 }; 1751 1752 pcie4: pcie@1c00000 { 1753 device_type = "pci"; 1754 compatible = "qcom,pcie-sc8280xp"; 1755 reg = <0x0 0x01c00000 0x0 0x3000>, 1756 <0x0 0x30000000 0x0 0xf1d>, 1757 <0x0 0x30000f20 0x0 0xa8>, 1758 <0x0 0x30001000 0x0 0x1000>, 1759 <0x0 0x30100000 0x0 0x100000>, 1760 <0x0 0x01c03000 0x0 0x1000>; 1761 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1762 #address-cells = <3>; 1763 #size-cells = <2>; 1764 ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, 1765 <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; 1766 bus-range = <0x00 0xff>; 1767 1768 dma-coherent; 1769 1770 linux,pci-domain = <6>; 1771 num-lanes = <1>; 1772 1773 msi-map = <0x0 &its 0xe0000 0x10000>; 1774 1775 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1777 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1778 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1779 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1780 1781 #interrupt-cells = <1>; 1782 interrupt-map-mask = <0 0 0 0x7>; 1783 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1784 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1785 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1786 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1787 1788 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1789 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1790 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, 1791 <&gcc GCC_PCIE_4_SLV_AXI_CLK>, 1792 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, 1793 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1794 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1795 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, 1796 <&gcc GCC_CNOC_PCIE4_QX_CLK>; 1797 clock-names = "aux", 1798 "cfg", 1799 "bus_master", 1800 "bus_slave", 1801 "slave_q2a", 1802 "ddrss_sf_tbu", 1803 "noc_aggr_4", 1804 "noc_aggr_south_sf", 1805 "cnoc_qx"; 1806 1807 assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; 1808 assigned-clock-rates = <19200000>; 1809 1810 interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, 1811 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; 1812 interconnect-names = "pcie-mem", "cpu-pcie"; 1813 1814 resets = <&gcc GCC_PCIE_4_BCR>; 1815 reset-names = "pci"; 1816 1817 power-domains = <&gcc PCIE_4_GDSC>; 1818 required-opps = <&rpmhpd_opp_nom>; 1819 1820 phys = <&pcie4_phy>; 1821 phy-names = "pciephy"; 1822 1823 status = "disabled"; 1824 1825 pcie4_port0: pcie@0 { 1826 device_type = "pci"; 1827 reg = <0x0 0x0 0x0 0x0 0x0>; 1828 bus-range = <0x01 0xff>; 1829 1830 #address-cells = <3>; 1831 #size-cells = <2>; 1832 ranges; 1833 }; 1834 }; 1835 1836 pcie4_phy: phy@1c06000 { 1837 compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; 1838 reg = <0x0 0x01c06000 0x0 0x2000>; 1839 1840 clocks = <&gcc GCC_PCIE_4_AUX_CLK>, 1841 <&gcc GCC_PCIE_4_CFG_AHB_CLK>, 1842 <&gcc GCC_PCIE_4_CLKREF_CLK>, 1843 <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, 1844 <&gcc GCC_PCIE_4_PIPE_CLK>, 1845 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; 1846 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1847 "pipe", "pipediv2"; 1848 1849 assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; 1850 assigned-clock-rates = <100000000>; 1851 1852 power-domains = <&gcc PCIE_4_GDSC>; 1853 1854 resets = <&gcc GCC_PCIE_4_PHY_BCR>; 1855 reset-names = "phy"; 1856 1857 #clock-cells = <0>; 1858 clock-output-names = "pcie_4_pipe_clk"; 1859 1860 #phy-cells = <0>; 1861 1862 status = "disabled"; 1863 }; 1864 1865 pcie3b: pcie@1c08000 { 1866 device_type = "pci"; 1867 compatible = "qcom,pcie-sc8280xp"; 1868 reg = <0x0 0x01c08000 0x0 0x3000>, 1869 <0x0 0x32000000 0x0 0xf1d>, 1870 <0x0 0x32000f20 0x0 0xa8>, 1871 <0x0 0x32001000 0x0 0x1000>, 1872 <0x0 0x32100000 0x0 0x100000>, 1873 <0x0 0x01c0b000 0x0 0x1000>; 1874 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1875 #address-cells = <3>; 1876 #size-cells = <2>; 1877 ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, 1878 <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; 1879 bus-range = <0x00 0xff>; 1880 1881 dma-coherent; 1882 1883 linux,pci-domain = <5>; 1884 num-lanes = <2>; 1885 1886 msi-map = <0x0 &its 0xd0000 0x10000>; 1887 1888 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1892 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 1893 1894 #interrupt-cells = <1>; 1895 interrupt-map-mask = <0 0 0 0x7>; 1896 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 1897 <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 1898 <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 1899 <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1900 1901 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1902 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1903 <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, 1904 <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, 1905 <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, 1906 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 1907 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 1908 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 1909 clock-names = "aux", 1910 "cfg", 1911 "bus_master", 1912 "bus_slave", 1913 "slave_q2a", 1914 "ddrss_sf_tbu", 1915 "noc_aggr_4", 1916 "noc_aggr_south_sf"; 1917 1918 assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; 1919 assigned-clock-rates = <19200000>; 1920 1921 interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, 1922 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; 1923 interconnect-names = "pcie-mem", "cpu-pcie"; 1924 1925 resets = <&gcc GCC_PCIE_3B_BCR>; 1926 reset-names = "pci"; 1927 1928 power-domains = <&gcc PCIE_3B_GDSC>; 1929 required-opps = <&rpmhpd_opp_nom>; 1930 1931 phys = <&pcie3b_phy>; 1932 phy-names = "pciephy"; 1933 1934 status = "disabled"; 1935 1936 pcie3b_port0: pcie@0 { 1937 device_type = "pci"; 1938 reg = <0x0 0x0 0x0 0x0 0x0>; 1939 bus-range = <0x01 0xff>; 1940 1941 #address-cells = <3>; 1942 #size-cells = <2>; 1943 ranges; 1944 }; 1945 }; 1946 1947 pcie3b_phy: phy@1c0e000 { 1948 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 1949 reg = <0x0 0x01c0e000 0x0 0x2000>; 1950 1951 clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, 1952 <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, 1953 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 1954 <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, 1955 <&gcc GCC_PCIE_3B_PIPE_CLK>, 1956 <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; 1957 clock-names = "aux", "cfg_ahb", "ref", "rchng", 1958 "pipe", "pipediv2"; 1959 1960 assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; 1961 assigned-clock-rates = <100000000>; 1962 1963 power-domains = <&gcc PCIE_3B_GDSC>; 1964 1965 resets = <&gcc GCC_PCIE_3B_PHY_BCR>; 1966 reset-names = "phy"; 1967 1968 #clock-cells = <0>; 1969 clock-output-names = "pcie_3b_pipe_clk"; 1970 1971 #phy-cells = <0>; 1972 1973 status = "disabled"; 1974 }; 1975 1976 pcie3a: pcie@1c10000 { 1977 device_type = "pci"; 1978 compatible = "qcom,pcie-sc8280xp"; 1979 reg = <0x0 0x01c10000 0x0 0x3000>, 1980 <0x0 0x34000000 0x0 0xf1d>, 1981 <0x0 0x34000f20 0x0 0xa8>, 1982 <0x0 0x34001000 0x0 0x1000>, 1983 <0x0 0x34100000 0x0 0x100000>, 1984 <0x0 0x01c13000 0x0 0x1000>; 1985 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 1986 #address-cells = <3>; 1987 #size-cells = <2>; 1988 ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, 1989 <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; 1990 bus-range = <0x00 0xff>; 1991 1992 dma-coherent; 1993 1994 linux,pci-domain = <4>; 1995 num-lanes = <4>; 1996 1997 msi-map = <0x0 &its 0xc0000 0x10000>; 1998 1999 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2000 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2001 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2002 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; 2003 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2004 2005 #interrupt-cells = <1>; 2006 interrupt-map-mask = <0 0 0 0x7>; 2007 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 2008 <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 2009 <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 2010 <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 2011 2012 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2013 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2014 <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, 2015 <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, 2016 <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, 2017 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2018 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2019 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2020 clock-names = "aux", 2021 "cfg", 2022 "bus_master", 2023 "bus_slave", 2024 "slave_q2a", 2025 "ddrss_sf_tbu", 2026 "noc_aggr_4", 2027 "noc_aggr_south_sf"; 2028 2029 assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; 2030 assigned-clock-rates = <19200000>; 2031 2032 interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, 2033 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; 2034 interconnect-names = "pcie-mem", "cpu-pcie"; 2035 2036 resets = <&gcc GCC_PCIE_3A_BCR>; 2037 reset-names = "pci"; 2038 2039 power-domains = <&gcc PCIE_3A_GDSC>; 2040 required-opps = <&rpmhpd_opp_nom>; 2041 2042 phys = <&pcie3a_phy>; 2043 phy-names = "pciephy"; 2044 2045 status = "disabled"; 2046 2047 pcie3a_port0: pcie@0 { 2048 device_type = "pci"; 2049 reg = <0x0 0x0 0x0 0x0 0x0>; 2050 bus-range = <0x01 0xff>; 2051 2052 #address-cells = <3>; 2053 #size-cells = <2>; 2054 ranges; 2055 }; 2056 }; 2057 2058 pcie3a_phy: phy@1c14000 { 2059 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2060 reg = <0x0 0x01c14000 0x0 0x2000>, 2061 <0x0 0x01c16000 0x0 0x2000>; 2062 2063 clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, 2064 <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, 2065 <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, 2066 <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, 2067 <&gcc GCC_PCIE_3A_PIPE_CLK>, 2068 <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; 2069 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2070 "pipe", "pipediv2"; 2071 2072 assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; 2073 assigned-clock-rates = <100000000>; 2074 2075 power-domains = <&gcc PCIE_3A_GDSC>; 2076 2077 resets = <&gcc GCC_PCIE_3A_PHY_BCR>; 2078 reset-names = "phy"; 2079 2080 qcom,4ln-config-sel = <&tcsr 0xa044 1>; 2081 2082 #clock-cells = <0>; 2083 clock-output-names = "pcie_3a_pipe_clk"; 2084 2085 #phy-cells = <0>; 2086 2087 status = "disabled"; 2088 }; 2089 2090 pcie2b: pcie@1c18000 { 2091 device_type = "pci"; 2092 compatible = "qcom,pcie-sc8280xp"; 2093 reg = <0x0 0x01c18000 0x0 0x3000>, 2094 <0x0 0x38000000 0x0 0xf1d>, 2095 <0x0 0x38000f20 0x0 0xa8>, 2096 <0x0 0x38001000 0x0 0x1000>, 2097 <0x0 0x38100000 0x0 0x100000>, 2098 <0x0 0x01c1b000 0x0 0x1000>; 2099 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2100 #address-cells = <3>; 2101 #size-cells = <2>; 2102 ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, 2103 <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; 2104 bus-range = <0x00 0xff>; 2105 2106 dma-coherent; 2107 2108 linux,pci-domain = <3>; 2109 num-lanes = <2>; 2110 2111 msi-map = <0x0 &its 0xb0000 0x10000>; 2112 2113 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 2117 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2118 2119 #interrupt-cells = <1>; 2120 interrupt-map-mask = <0 0 0 0x7>; 2121 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2122 <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2123 <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2124 <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; 2125 2126 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2127 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2128 <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, 2129 <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, 2130 <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, 2131 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2132 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2133 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2134 clock-names = "aux", 2135 "cfg", 2136 "bus_master", 2137 "bus_slave", 2138 "slave_q2a", 2139 "ddrss_sf_tbu", 2140 "noc_aggr_4", 2141 "noc_aggr_south_sf"; 2142 2143 assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; 2144 assigned-clock-rates = <19200000>; 2145 2146 interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, 2147 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; 2148 interconnect-names = "pcie-mem", "cpu-pcie"; 2149 2150 resets = <&gcc GCC_PCIE_2B_BCR>; 2151 reset-names = "pci"; 2152 2153 power-domains = <&gcc PCIE_2B_GDSC>; 2154 required-opps = <&rpmhpd_opp_nom>; 2155 2156 phys = <&pcie2b_phy>; 2157 phy-names = "pciephy"; 2158 2159 status = "disabled"; 2160 2161 pcie2b_port0: pcie@0 { 2162 device_type = "pci"; 2163 reg = <0x0 0x0 0x0 0x0 0x0>; 2164 bus-range = <0x01 0xff>; 2165 2166 #address-cells = <3>; 2167 #size-cells = <2>; 2168 ranges; 2169 }; 2170 }; 2171 2172 pcie2b_phy: phy@1c1e000 { 2173 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; 2174 reg = <0x0 0x01c1e000 0x0 0x2000>; 2175 2176 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, 2177 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, 2178 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2179 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, 2180 <&gcc GCC_PCIE_2B_PIPE_CLK>, 2181 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; 2182 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2183 "pipe", "pipediv2"; 2184 2185 assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; 2186 assigned-clock-rates = <100000000>; 2187 2188 power-domains = <&gcc PCIE_2B_GDSC>; 2189 2190 resets = <&gcc GCC_PCIE_2B_PHY_BCR>; 2191 reset-names = "phy"; 2192 2193 #clock-cells = <0>; 2194 clock-output-names = "pcie_2b_pipe_clk"; 2195 2196 #phy-cells = <0>; 2197 2198 status = "disabled"; 2199 }; 2200 2201 pcie2a: pcie@1c20000 { 2202 device_type = "pci"; 2203 compatible = "qcom,pcie-sc8280xp"; 2204 reg = <0x0 0x01c20000 0x0 0x3000>, 2205 <0x0 0x3c000000 0x0 0xf1d>, 2206 <0x0 0x3c000f20 0x0 0xa8>, 2207 <0x0 0x3c001000 0x0 0x1000>, 2208 <0x0 0x3c100000 0x0 0x100000>, 2209 <0x0 0x01c23000 0x0 0x1000>; 2210 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2211 #address-cells = <3>; 2212 #size-cells = <2>; 2213 ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, 2214 <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; 2215 bus-range = <0x00 0xff>; 2216 2217 dma-coherent; 2218 2219 linux,pci-domain = <2>; 2220 num-lanes = <4>; 2221 2222 msi-map = <0x0 &its 0xa0000 0x10000>; 2223 2224 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 2225 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 2226 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 2227 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; 2228 interrupt-names = "msi0", "msi1", "msi2", "msi3"; 2229 2230 #interrupt-cells = <1>; 2231 interrupt-map-mask = <0 0 0 0x7>; 2232 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 2233 <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 2234 <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 2235 <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 2236 2237 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2238 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2239 <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, 2240 <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, 2241 <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, 2242 <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, 2243 <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, 2244 <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; 2245 clock-names = "aux", 2246 "cfg", 2247 "bus_master", 2248 "bus_slave", 2249 "slave_q2a", 2250 "ddrss_sf_tbu", 2251 "noc_aggr_4", 2252 "noc_aggr_south_sf"; 2253 2254 assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; 2255 assigned-clock-rates = <19200000>; 2256 2257 interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, 2258 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; 2259 interconnect-names = "pcie-mem", "cpu-pcie"; 2260 2261 resets = <&gcc GCC_PCIE_2A_BCR>; 2262 reset-names = "pci"; 2263 2264 power-domains = <&gcc PCIE_2A_GDSC>; 2265 required-opps = <&rpmhpd_opp_nom>; 2266 2267 phys = <&pcie2a_phy>; 2268 phy-names = "pciephy"; 2269 2270 status = "disabled"; 2271 2272 pcie2a_port0: pcie@0 { 2273 device_type = "pci"; 2274 reg = <0x0 0x0 0x0 0x0 0x0>; 2275 bus-range = <0x01 0xff>; 2276 2277 #address-cells = <3>; 2278 #size-cells = <2>; 2279 ranges; 2280 }; 2281 }; 2282 2283 pcie2a_phy: phy@1c24000 { 2284 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; 2285 reg = <0x0 0x01c24000 0x0 0x2000>, 2286 <0x0 0x01c26000 0x0 0x2000>; 2287 2288 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, 2289 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, 2290 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, 2291 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, 2292 <&gcc GCC_PCIE_2A_PIPE_CLK>, 2293 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; 2294 clock-names = "aux", "cfg_ahb", "ref", "rchng", 2295 "pipe", "pipediv2"; 2296 2297 assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; 2298 assigned-clock-rates = <100000000>; 2299 2300 power-domains = <&gcc PCIE_2A_GDSC>; 2301 2302 resets = <&gcc GCC_PCIE_2A_PHY_BCR>; 2303 reset-names = "phy"; 2304 2305 qcom,4ln-config-sel = <&tcsr 0xa044 0>; 2306 2307 #clock-cells = <0>; 2308 clock-output-names = "pcie_2a_pipe_clk"; 2309 2310 #phy-cells = <0>; 2311 2312 status = "disabled"; 2313 }; 2314 2315 ufs_mem_hc: ufshc@1d84000 { 2316 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2317 "jedec,ufs-2.0"; 2318 reg = <0 0x01d84000 0 0x3000>; 2319 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2320 phys = <&ufs_mem_phy>; 2321 phy-names = "ufsphy"; 2322 lanes-per-direction = <2>; 2323 #reset-cells = <1>; 2324 resets = <&gcc GCC_UFS_PHY_BCR>; 2325 reset-names = "rst"; 2326 2327 power-domains = <&gcc UFS_PHY_GDSC>; 2328 required-opps = <&rpmhpd_opp_nom>; 2329 2330 iommus = <&apps_smmu 0xe0 0x0>; 2331 dma-coherent; 2332 2333 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2334 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2335 <&gcc GCC_UFS_PHY_AHB_CLK>, 2336 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2337 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2338 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2339 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2340 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2341 clock-names = "core_clk", 2342 "bus_aggr_clk", 2343 "iface_clk", 2344 "core_clk_unipro", 2345 "ref_clk", 2346 "tx_lane0_sync_clk", 2347 "rx_lane0_sync_clk", 2348 "rx_lane1_sync_clk"; 2349 freq-table-hz = <75000000 300000000>, 2350 <0 0>, 2351 <0 0>, 2352 <75000000 300000000>, 2353 <0 0>, 2354 <0 0>, 2355 <0 0>, 2356 <0 0>; 2357 status = "disabled"; 2358 }; 2359 2360 ufs_mem_phy: phy@1d87000 { 2361 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2362 reg = <0 0x01d87000 0 0x1000>; 2363 2364 clocks = <&rpmhcc RPMH_CXO_CLK>, 2365 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2366 <&gcc GCC_UFS_CARD_CLKREF_CLK>; 2367 clock-names = "ref", 2368 "ref_aux", 2369 "qref"; 2370 2371 power-domains = <&gcc UFS_PHY_GDSC>; 2372 2373 resets = <&ufs_mem_hc 0>; 2374 reset-names = "ufsphy"; 2375 2376 #phy-cells = <0>; 2377 2378 status = "disabled"; 2379 }; 2380 2381 ufs_card_hc: ufshc@1da4000 { 2382 compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", 2383 "jedec,ufs-2.0"; 2384 reg = <0 0x01da4000 0 0x3000>; 2385 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2386 phys = <&ufs_card_phy>; 2387 phy-names = "ufsphy"; 2388 lanes-per-direction = <2>; 2389 #reset-cells = <1>; 2390 resets = <&gcc GCC_UFS_CARD_BCR>; 2391 reset-names = "rst"; 2392 2393 power-domains = <&gcc UFS_CARD_GDSC>; 2394 2395 iommus = <&apps_smmu 0x4a0 0x0>; 2396 dma-coherent; 2397 2398 clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, 2399 <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, 2400 <&gcc GCC_UFS_CARD_AHB_CLK>, 2401 <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, 2402 <&gcc GCC_UFS_REF_CLKREF_CLK>, 2403 <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, 2404 <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, 2405 <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; 2406 clock-names = "core_clk", 2407 "bus_aggr_clk", 2408 "iface_clk", 2409 "core_clk_unipro", 2410 "ref_clk", 2411 "tx_lane0_sync_clk", 2412 "rx_lane0_sync_clk", 2413 "rx_lane1_sync_clk"; 2414 freq-table-hz = <75000000 300000000>, 2415 <0 0>, 2416 <0 0>, 2417 <75000000 300000000>, 2418 <0 0>, 2419 <0 0>, 2420 <0 0>, 2421 <0 0>; 2422 status = "disabled"; 2423 }; 2424 2425 ufs_card_phy: phy@1da7000 { 2426 compatible = "qcom,sc8280xp-qmp-ufs-phy"; 2427 reg = <0 0x01da7000 0 0x1000>; 2428 2429 clocks = <&rpmhcc RPMH_CXO_CLK>, 2430 <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, 2431 <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; 2432 clock-names = "ref", 2433 "ref_aux", 2434 "qref"; 2435 2436 power-domains = <&gcc UFS_CARD_GDSC>; 2437 2438 resets = <&ufs_card_hc 0>; 2439 reset-names = "ufsphy"; 2440 2441 #phy-cells = <0>; 2442 2443 status = "disabled"; 2444 }; 2445 2446 tcsr_mutex: hwlock@1f40000 { 2447 compatible = "qcom,tcsr-mutex"; 2448 reg = <0x0 0x01f40000 0x0 0x20000>; 2449 #hwlock-cells = <1>; 2450 }; 2451 2452 tcsr: syscon@1fc0000 { 2453 compatible = "qcom,sc8280xp-tcsr", "syscon"; 2454 reg = <0x0 0x01fc0000 0x0 0x30000>; 2455 }; 2456 2457 gpu: gpu@3d00000 { 2458 compatible = "qcom,adreno-690.0", "qcom,adreno"; 2459 2460 reg = <0 0x03d00000 0 0x40000>, 2461 <0 0x03d9e000 0 0x1000>, 2462 <0 0x03d61000 0 0x800>; 2463 reg-names = "kgsl_3d0_reg_memory", 2464 "cx_mem", 2465 "cx_dbgc"; 2466 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2467 iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; 2468 operating-points-v2 = <&gpu_opp_table>; 2469 2470 qcom,gmu = <&gmu>; 2471 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 2472 interconnect-names = "gfx-mem"; 2473 #cooling-cells = <2>; 2474 2475 status = "disabled"; 2476 2477 gpu_opp_table: opp-table { 2478 compatible = "operating-points-v2"; 2479 2480 opp-270000000 { 2481 opp-hz = /bits/ 64 <270000000>; 2482 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2483 opp-peak-kBps = <451000>; 2484 }; 2485 2486 opp-410000000 { 2487 opp-hz = /bits/ 64 <410000000>; 2488 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2489 opp-peak-kBps = <1555000>; 2490 }; 2491 2492 opp-500000000 { 2493 opp-hz = /bits/ 64 <500000000>; 2494 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2495 opp-peak-kBps = <1555000>; 2496 }; 2497 2498 opp-547000000 { 2499 opp-hz = /bits/ 64 <547000000>; 2500 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 2501 opp-peak-kBps = <1555000>; 2502 }; 2503 2504 opp-606000000 { 2505 opp-hz = /bits/ 64 <606000000>; 2506 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2507 opp-peak-kBps = <2736000>; 2508 }; 2509 2510 opp-640000000 { 2511 opp-hz = /bits/ 64 <640000000>; 2512 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2513 opp-peak-kBps = <2736000>; 2514 }; 2515 2516 opp-655000000 { 2517 opp-hz = /bits/ 64 <655000000>; 2518 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2519 opp-peak-kBps = <2736000>; 2520 }; 2521 2522 opp-690000000 { 2523 opp-hz = /bits/ 64 <690000000>; 2524 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2525 opp-peak-kBps = <2736000>; 2526 }; 2527 }; 2528 }; 2529 2530 gmu: gmu@3d6a000 { 2531 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; 2532 reg = <0 0x03d6a000 0 0x34000>, 2533 <0 0x03de0000 0 0x10000>, 2534 <0 0x0b290000 0 0x10000>; 2535 reg-names = "gmu", "rscc", "gmu_pdc"; 2536 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2537 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2538 interrupt-names = "hfi", "gmu"; 2539 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2540 <&gpucc GPU_CC_CXO_CLK>, 2541 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2542 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2543 <&gpucc GPU_CC_AHB_CLK>, 2544 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2545 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 2546 clock-names = "gmu", 2547 "cxo", 2548 "axi", 2549 "memnoc", 2550 "ahb", 2551 "hub", 2552 "smmu_vote"; 2553 power-domains = <&gpucc GPU_CC_CX_GDSC>, 2554 <&gpucc GPU_CC_GX_GDSC>; 2555 power-domain-names = "cx", 2556 "gx"; 2557 iommus = <&gpu_smmu 5 0xc00>; 2558 operating-points-v2 = <&gmu_opp_table>; 2559 2560 gmu_opp_table: opp-table { 2561 compatible = "operating-points-v2"; 2562 2563 opp-200000000 { 2564 opp-hz = /bits/ 64 <200000000>; 2565 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2566 }; 2567 2568 opp-500000000 { 2569 opp-hz = /bits/ 64 <500000000>; 2570 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2571 }; 2572 }; 2573 }; 2574 2575 gpucc: clock-controller@3d90000 { 2576 compatible = "qcom,sc8280xp-gpucc"; 2577 reg = <0 0x03d90000 0 0x9000>; 2578 clocks = <&rpmhcc RPMH_CXO_CLK>, 2579 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2580 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2581 clock-names = "bi_tcxo", 2582 "gcc_gpu_gpll0_clk_src", 2583 "gcc_gpu_gpll0_div_clk_src"; 2584 2585 power-domains = <&rpmhpd SC8280XP_GFX>; 2586 #clock-cells = <1>; 2587 #reset-cells = <1>; 2588 #power-domain-cells = <1>; 2589 }; 2590 2591 gpu_smmu: iommu@3da0000 { 2592 compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", 2593 "qcom,smmu-500", "arm,mmu-500"; 2594 reg = <0 0x03da0000 0 0x20000>; 2595 #iommu-cells = <2>; 2596 #global-interrupts = <2>; 2597 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 2598 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 2599 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 2600 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 2601 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 2602 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 2603 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 2604 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 2605 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 2606 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 2607 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 2608 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, 2609 <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, 2610 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; 2611 2612 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2613 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 2614 <&gpucc GPU_CC_AHB_CLK>, 2615 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 2616 <&gpucc GPU_CC_CX_GMU_CLK>, 2617 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 2618 <&gpucc GPU_CC_HUB_AON_CLK>; 2619 clock-names = "gcc_gpu_memnoc_gfx_clk", 2620 "gcc_gpu_snoc_dvm_gfx_clk", 2621 "gpu_cc_ahb_clk", 2622 "gpu_cc_hlos1_vote_gpu_smmu_clk", 2623 "gpu_cc_cx_gmu_clk", 2624 "gpu_cc_hub_cx_int_clk", 2625 "gpu_cc_hub_aon_clk"; 2626 2627 power-domains = <&gpucc GPU_CC_CX_GDSC>; 2628 dma-coherent; 2629 }; 2630 2631 usb_0_hsphy: phy@88e5000 { 2632 compatible = "qcom,sc8280xp-usb-hs-phy", 2633 "qcom,usb-snps-hs-5nm-phy"; 2634 reg = <0 0x088e5000 0 0x400>; 2635 clocks = <&rpmhcc RPMH_CXO_CLK>; 2636 clock-names = "ref"; 2637 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2638 2639 #phy-cells = <0>; 2640 2641 status = "disabled"; 2642 }; 2643 2644 usb_2_hsphy0: phy@88e7000 { 2645 compatible = "qcom,sc8280xp-usb-hs-phy", 2646 "qcom,usb-snps-hs-5nm-phy"; 2647 reg = <0 0x088e7000 0 0x400>; 2648 clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; 2649 clock-names = "ref"; 2650 resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; 2651 2652 #phy-cells = <0>; 2653 2654 status = "disabled"; 2655 }; 2656 2657 usb_2_hsphy1: phy@88e8000 { 2658 compatible = "qcom,sc8280xp-usb-hs-phy", 2659 "qcom,usb-snps-hs-5nm-phy"; 2660 reg = <0 0x088e8000 0 0x400>; 2661 clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; 2662 clock-names = "ref"; 2663 resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; 2664 2665 #phy-cells = <0>; 2666 2667 status = "disabled"; 2668 }; 2669 2670 usb_2_hsphy2: phy@88e9000 { 2671 compatible = "qcom,sc8280xp-usb-hs-phy", 2672 "qcom,usb-snps-hs-5nm-phy"; 2673 reg = <0 0x088e9000 0 0x400>; 2674 clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; 2675 clock-names = "ref"; 2676 resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; 2677 2678 #phy-cells = <0>; 2679 2680 status = "disabled"; 2681 }; 2682 2683 usb_2_hsphy3: phy@88ea000 { 2684 compatible = "qcom,sc8280xp-usb-hs-phy", 2685 "qcom,usb-snps-hs-5nm-phy"; 2686 reg = <0 0x088ea000 0 0x400>; 2687 clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; 2688 clock-names = "ref"; 2689 resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; 2690 2691 #phy-cells = <0>; 2692 2693 status = "disabled"; 2694 }; 2695 2696 usb_2_qmpphy0: phy@88ef000 { 2697 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2698 reg = <0 0x088ef000 0 0x2000>; 2699 2700 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2701 <&gcc GCC_USB3_MP0_CLKREF_CLK>, 2702 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2703 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; 2704 clock-names = "aux", "ref", "com_aux", "pipe"; 2705 2706 resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, 2707 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; 2708 reset-names = "phy", "phy_phy"; 2709 2710 power-domains = <&gcc USB30_MP_GDSC>; 2711 2712 #clock-cells = <0>; 2713 clock-output-names = "usb2_phy0_pipe_clk"; 2714 2715 #phy-cells = <0>; 2716 2717 status = "disabled"; 2718 }; 2719 2720 usb_2_qmpphy1: phy@88f1000 { 2721 compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; 2722 reg = <0 0x088f1000 0 0x2000>; 2723 2724 clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, 2725 <&gcc GCC_USB3_MP1_CLKREF_CLK>, 2726 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, 2727 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; 2728 clock-names = "aux", "ref", "com_aux", "pipe"; 2729 2730 resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, 2731 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; 2732 reset-names = "phy", "phy_phy"; 2733 2734 power-domains = <&gcc USB30_MP_GDSC>; 2735 2736 #clock-cells = <0>; 2737 clock-output-names = "usb2_phy1_pipe_clk"; 2738 2739 #phy-cells = <0>; 2740 2741 status = "disabled"; 2742 }; 2743 2744 remoteproc_adsp: remoteproc@3000000 { 2745 compatible = "qcom,sc8280xp-adsp-pas"; 2746 reg = <0 0x03000000 0 0x10000>; 2747 2748 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 2749 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2750 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2751 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2752 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2753 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2754 interrupt-names = "wdog", "fatal", "ready", 2755 "handover", "stop-ack", "shutdown-ack"; 2756 2757 clocks = <&rpmhcc RPMH_CXO_CLK>; 2758 clock-names = "xo"; 2759 2760 power-domains = <&rpmhpd SC8280XP_LCX>, 2761 <&rpmhpd SC8280XP_LMX>; 2762 power-domain-names = "lcx", "lmx"; 2763 2764 memory-region = <&pil_adsp_mem>; 2765 2766 qcom,qmp = <&aoss_qmp>; 2767 2768 qcom,smem-states = <&smp2p_adsp_out 0>; 2769 qcom,smem-state-names = "stop"; 2770 2771 status = "disabled"; 2772 2773 remoteproc_adsp_glink: glink-edge { 2774 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2775 IPCC_MPROC_SIGNAL_GLINK_QMP 2776 IRQ_TYPE_EDGE_RISING>; 2777 mboxes = <&ipcc IPCC_CLIENT_LPASS 2778 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2779 2780 label = "lpass"; 2781 qcom,remote-pid = <2>; 2782 2783 gpr { 2784 compatible = "qcom,gpr"; 2785 qcom,glink-channels = "adsp_apps"; 2786 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2787 qcom,intents = <512 20>; 2788 #address-cells = <1>; 2789 #size-cells = <0>; 2790 2791 q6apm: service@1 { 2792 compatible = "qcom,q6apm"; 2793 reg = <GPR_APM_MODULE_IID>; 2794 #sound-dai-cells = <0>; 2795 qcom,protection-domain = "avs/audio", 2796 "msm/adsp/audio_pd"; 2797 q6apmdai: dais { 2798 compatible = "qcom,q6apm-dais"; 2799 iommus = <&apps_smmu 0x0c01 0x0>; 2800 }; 2801 2802 q6apmbedai: bedais { 2803 compatible = "qcom,q6apm-lpass-dais"; 2804 #sound-dai-cells = <1>; 2805 }; 2806 }; 2807 2808 q6prm: service@2 { 2809 compatible = "qcom,q6prm"; 2810 reg = <GPR_PRM_MODULE_IID>; 2811 qcom,protection-domain = "avs/audio", 2812 "msm/adsp/audio_pd"; 2813 q6prmcc: clock-controller { 2814 compatible = "qcom,q6prm-lpass-clocks"; 2815 #clock-cells = <2>; 2816 }; 2817 }; 2818 }; 2819 }; 2820 }; 2821 2822 rxmacro: rxmacro@3200000 { 2823 compatible = "qcom,sc8280xp-lpass-rx-macro"; 2824 reg = <0 0x03200000 0 0x1000>; 2825 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2826 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2827 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2828 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2829 <&vamacro>; 2830 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2831 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2832 <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2833 assigned-clock-rates = <19200000>, <19200000>; 2834 2835 clock-output-names = "mclk"; 2836 #clock-cells = <0>; 2837 #sound-dai-cells = <1>; 2838 2839 pinctrl-names = "default"; 2840 pinctrl-0 = <&rx_swr_default>; 2841 2842 status = "disabled"; 2843 }; 2844 2845 swr1: soundwire@3210000 { 2846 compatible = "qcom,soundwire-v1.6.0"; 2847 reg = <0 0x03210000 0 0x2000>; 2848 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2849 clocks = <&rxmacro>; 2850 clock-names = "iface"; 2851 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2852 reset-names = "swr_audio_cgcr"; 2853 label = "RX"; 2854 2855 qcom,din-ports = <0>; 2856 qcom,dout-ports = <5>; 2857 2858 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; 2859 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; 2860 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>; 2861 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>; 2862 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>; 2863 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2864 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>; 2865 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2866 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>; 2867 2868 #sound-dai-cells = <1>; 2869 #address-cells = <2>; 2870 #size-cells = <0>; 2871 2872 status = "disabled"; 2873 }; 2874 2875 txmacro: txmacro@3220000 { 2876 compatible = "qcom,sc8280xp-lpass-tx-macro"; 2877 reg = <0 0x03220000 0 0x1000>; 2878 pinctrl-names = "default"; 2879 pinctrl-0 = <&tx_swr_default>; 2880 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2881 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2882 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2883 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2884 <&vamacro>; 2885 2886 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2887 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2888 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2889 assigned-clock-rates = <19200000>, <19200000>; 2890 clock-output-names = "mclk"; 2891 2892 #clock-cells = <0>; 2893 #sound-dai-cells = <1>; 2894 2895 status = "disabled"; 2896 }; 2897 2898 wsamacro: codec@3240000 { 2899 compatible = "qcom,sc8280xp-lpass-wsa-macro"; 2900 reg = <0 0x03240000 0 0x1000>; 2901 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2902 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2903 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2904 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2905 <&vamacro>; 2906 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; 2907 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2908 <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2909 assigned-clock-rates = <19200000>, <19200000>; 2910 2911 #clock-cells = <0>; 2912 clock-output-names = "mclk"; 2913 #sound-dai-cells = <1>; 2914 2915 pinctrl-names = "default"; 2916 pinctrl-0 = <&wsa_swr_default>; 2917 2918 status = "disabled"; 2919 }; 2920 2921 swr0: soundwire@3250000 { 2922 reg = <0 0x03250000 0 0x2000>; 2923 compatible = "qcom,soundwire-v1.6.0"; 2924 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2925 clocks = <&wsamacro>; 2926 clock-names = "iface"; 2927 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2928 reset-names = "swr_audio_cgcr"; 2929 label = "WSA"; 2930 2931 qcom,din-ports = <2>; 2932 qcom,dout-ports = <6>; 2933 2934 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>; 2935 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2936 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2937 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2938 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2939 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2940 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>; 2941 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2942 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2943 2944 #sound-dai-cells = <1>; 2945 #address-cells = <2>; 2946 #size-cells = <0>; 2947 2948 status = "disabled"; 2949 }; 2950 2951 lpass_audiocc: clock-controller@32a9000 { 2952 compatible = "qcom,sc8280xp-lpassaudiocc"; 2953 reg = <0 0x032a9000 0 0x1000>; 2954 #clock-cells = <1>; 2955 #reset-cells = <1>; 2956 }; 2957 2958 swr2: soundwire@3330000 { 2959 compatible = "qcom,soundwire-v1.6.0"; 2960 reg = <0 0x03330000 0 0x2000>; 2961 interrupts = <GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>; 2963 interrupt-names = "core", "wakeup"; 2964 2965 clocks = <&txmacro>; 2966 clock-names = "iface"; 2967 resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>; 2968 reset-names = "swr_audio_cgcr"; 2969 label = "TX"; 2970 #sound-dai-cells = <1>; 2971 #address-cells = <2>; 2972 #size-cells = <0>; 2973 2974 qcom,din-ports = <4>; 2975 qcom,dout-ports = <0>; 2976 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2977 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>; 2978 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2979 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2980 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2981 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2982 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2983 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2984 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>; 2985 2986 status = "disabled"; 2987 }; 2988 2989 vamacro: codec@3370000 { 2990 compatible = "qcom,sc8280xp-lpass-va-macro"; 2991 reg = <0 0x03370000 0 0x1000>; 2992 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2993 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2994 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2995 <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2996 clock-names = "mclk", "macro", "dcodec", "npl"; 2997 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2998 assigned-clock-rates = <19200000>; 2999 3000 #clock-cells = <0>; 3001 clock-output-names = "fsgen"; 3002 #sound-dai-cells = <1>; 3003 3004 status = "disabled"; 3005 }; 3006 3007 lpass_tlmm: pinctrl@33c0000 { 3008 compatible = "qcom,sc8280xp-lpass-lpi-pinctrl"; 3009 reg = <0 0x33c0000 0x0 0x20000>, 3010 <0 0x3550000 0x0 0x10000>; 3011 gpio-controller; 3012 #gpio-cells = <2>; 3013 gpio-ranges = <&lpass_tlmm 0 0 19>; 3014 3015 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3016 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3017 clock-names = "core", "audio"; 3018 3019 status = "disabled"; 3020 3021 tx_swr_default: tx-swr-default-state { 3022 clk-pins { 3023 pins = "gpio0"; 3024 function = "swr_tx_clk"; 3025 drive-strength = <2>; 3026 slew-rate = <1>; 3027 bias-disable; 3028 }; 3029 3030 data-pins { 3031 pins = "gpio1", "gpio2"; 3032 function = "swr_tx_data"; 3033 drive-strength = <2>; 3034 slew-rate = <1>; 3035 bias-bus-hold; 3036 }; 3037 }; 3038 3039 rx_swr_default: rx-swr-default-state { 3040 clk-pins { 3041 pins = "gpio3"; 3042 function = "swr_rx_clk"; 3043 drive-strength = <2>; 3044 slew-rate = <1>; 3045 bias-disable; 3046 }; 3047 3048 data-pins { 3049 pins = "gpio4", "gpio5"; 3050 function = "swr_rx_data"; 3051 drive-strength = <2>; 3052 slew-rate = <1>; 3053 bias-bus-hold; 3054 }; 3055 }; 3056 3057 dmic01_default: dmic01-default-state { 3058 clk-pins { 3059 pins = "gpio6"; 3060 function = "dmic1_clk"; 3061 drive-strength = <8>; 3062 output-high; 3063 }; 3064 3065 data-pins { 3066 pins = "gpio7"; 3067 function = "dmic1_data"; 3068 drive-strength = <8>; 3069 input-enable; 3070 }; 3071 }; 3072 3073 dmic01_sleep: dmic01-sleep-state { 3074 clk-pins { 3075 pins = "gpio6"; 3076 function = "dmic1_clk"; 3077 drive-strength = <2>; 3078 bias-disable; 3079 output-low; 3080 }; 3081 3082 data-pins { 3083 pins = "gpio7"; 3084 function = "dmic1_data"; 3085 drive-strength = <2>; 3086 bias-pull-down; 3087 input-enable; 3088 }; 3089 }; 3090 3091 dmic23_default: dmic23-default-state { 3092 clk-pins { 3093 pins = "gpio8"; 3094 function = "dmic2_clk"; 3095 drive-strength = <8>; 3096 output-high; 3097 }; 3098 3099 data-pins { 3100 pins = "gpio9"; 3101 function = "dmic2_data"; 3102 drive-strength = <8>; 3103 input-enable; 3104 }; 3105 }; 3106 3107 dmic23_sleep: dmic23-sleep-state { 3108 clk-pins { 3109 pins = "gpio8"; 3110 function = "dmic2_clk"; 3111 drive-strength = <2>; 3112 bias-disable; 3113 output-low; 3114 }; 3115 3116 data-pins { 3117 pins = "gpio9"; 3118 function = "dmic2_data"; 3119 drive-strength = <2>; 3120 bias-pull-down; 3121 input-enable; 3122 }; 3123 }; 3124 3125 wsa_swr_default: wsa-swr-default-state { 3126 clk-pins { 3127 pins = "gpio10"; 3128 function = "wsa_swr_clk"; 3129 drive-strength = <2>; 3130 slew-rate = <1>; 3131 bias-disable; 3132 }; 3133 3134 data-pins { 3135 pins = "gpio11"; 3136 function = "wsa_swr_data"; 3137 drive-strength = <2>; 3138 slew-rate = <1>; 3139 bias-bus-hold; 3140 }; 3141 }; 3142 3143 wsa2_swr_default: wsa2-swr-default-state { 3144 clk-pins { 3145 pins = "gpio15"; 3146 function = "wsa2_swr_clk"; 3147 drive-strength = <2>; 3148 slew-rate = <1>; 3149 bias-disable; 3150 }; 3151 3152 data-pins { 3153 pins = "gpio16"; 3154 function = "wsa2_swr_data"; 3155 drive-strength = <2>; 3156 slew-rate = <1>; 3157 bias-bus-hold; 3158 }; 3159 }; 3160 }; 3161 3162 lpasscc: clock-controller@33e0000 { 3163 compatible = "qcom,sc8280xp-lpasscc"; 3164 reg = <0 0x033e0000 0 0x12000>; 3165 #clock-cells = <1>; 3166 #reset-cells = <1>; 3167 }; 3168 3169 sdc2: mmc@8804000 { 3170 compatible = "qcom,sc8280xp-sdhci", "qcom,sdhci-msm-v5"; 3171 reg = <0 0x08804000 0 0x1000>; 3172 3173 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3174 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3175 interrupt-names = "hc_irq", "pwr_irq"; 3176 3177 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3178 <&gcc GCC_SDCC2_APPS_CLK>, 3179 <&rpmhcc RPMH_CXO_CLK>; 3180 clock-names = "iface", "core", "xo"; 3181 resets = <&gcc GCC_SDCC2_BCR>; 3182 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 3183 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>; 3184 interconnect-names = "sdhc-ddr","cpu-sdhc"; 3185 iommus = <&apps_smmu 0x4e0 0x0>; 3186 power-domains = <&rpmhpd SC8280XP_CX>; 3187 operating-points-v2 = <&sdc2_opp_table>; 3188 bus-width = <4>; 3189 dma-coherent; 3190 3191 status = "disabled"; 3192 3193 sdc2_opp_table: opp-table { 3194 compatible = "operating-points-v2"; 3195 3196 opp-100000000 { 3197 opp-hz = /bits/ 64 <100000000>; 3198 required-opps = <&rpmhpd_opp_low_svs>; 3199 opp-peak-kBps = <1800000 400000>; 3200 opp-avg-kBps = <100000 0>; 3201 }; 3202 3203 opp-202000000 { 3204 opp-hz = /bits/ 64 <202000000>; 3205 required-opps = <&rpmhpd_opp_svs_l1>; 3206 opp-peak-kBps = <5400000 1600000>; 3207 opp-avg-kBps = <200000 0>; 3208 }; 3209 }; 3210 }; 3211 3212 usb_0_qmpphy: phy@88eb000 { 3213 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3214 reg = <0 0x088eb000 0 0x4000>; 3215 3216 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 3217 <&gcc GCC_USB4_EUD_CLKREF_CLK>, 3218 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 3219 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 3220 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3221 3222 power-domains = <&gcc USB30_PRIM_GDSC>; 3223 3224 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 3225 <&gcc GCC_USB4_DP_PHY_PRIM_BCR>; 3226 reset-names = "phy", "common"; 3227 3228 #clock-cells = <1>; 3229 #phy-cells = <1>; 3230 3231 status = "disabled"; 3232 3233 ports { 3234 #address-cells = <1>; 3235 #size-cells = <0>; 3236 3237 port@0 { 3238 reg = <0>; 3239 3240 usb_0_qmpphy_out: endpoint {}; 3241 }; 3242 3243 port@1 { 3244 reg = <1>; 3245 3246 usb_0_qmpphy_usb_ss_in: endpoint { 3247 remote-endpoint = <&usb_0_dwc3_ss>; 3248 }; 3249 }; 3250 3251 port@2 { 3252 reg = <2>; 3253 3254 usb_0_qmpphy_dp_in: endpoint {}; 3255 }; 3256 }; 3257 }; 3258 3259 usb_1_hsphy: phy@8902000 { 3260 compatible = "qcom,sc8280xp-usb-hs-phy", 3261 "qcom,usb-snps-hs-5nm-phy"; 3262 reg = <0 0x08902000 0 0x400>; 3263 #phy-cells = <0>; 3264 3265 clocks = <&rpmhcc RPMH_CXO_CLK>; 3266 clock-names = "ref"; 3267 3268 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 3269 3270 status = "disabled"; 3271 }; 3272 3273 usb_1_qmpphy: phy@8903000 { 3274 compatible = "qcom,sc8280xp-qmp-usb43dp-phy"; 3275 reg = <0 0x08903000 0 0x4000>; 3276 3277 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 3278 <&gcc GCC_USB4_CLKREF_CLK>, 3279 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>, 3280 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 3281 clock-names = "aux", "ref", "com_aux", "usb3_pipe"; 3282 3283 power-domains = <&gcc USB30_SEC_GDSC>; 3284 3285 resets = <&gcc GCC_USB3_PHY_SEC_BCR>, 3286 <&gcc GCC_USB4_1_DP_PHY_PRIM_BCR>; 3287 reset-names = "phy", "common"; 3288 3289 #clock-cells = <1>; 3290 #phy-cells = <1>; 3291 3292 status = "disabled"; 3293 3294 ports { 3295 #address-cells = <1>; 3296 #size-cells = <0>; 3297 3298 port@0 { 3299 reg = <0>; 3300 3301 usb_1_qmpphy_out: endpoint {}; 3302 }; 3303 3304 port@1 { 3305 reg = <1>; 3306 3307 usb_1_qmpphy_usb_ss_in: endpoint { 3308 remote-endpoint = <&usb_1_dwc3_ss>; 3309 }; 3310 }; 3311 3312 port@2 { 3313 reg = <2>; 3314 3315 usb_1_qmpphy_dp_in: endpoint {}; 3316 }; 3317 }; 3318 }; 3319 3320 mdss1_dp0_phy: phy@8909a00 { 3321 compatible = "qcom,sc8280xp-dp-phy"; 3322 reg = <0 0x08909a00 0 0x19c>, 3323 <0 0x08909200 0 0xec>, 3324 <0 0x08909600 0 0xec>, 3325 <0 0x08909000 0 0x1c8>; 3326 3327 clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 3328 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3329 clock-names = "aux", "cfg_ahb"; 3330 power-domains = <&rpmhpd SC8280XP_MX>; 3331 3332 #clock-cells = <1>; 3333 #phy-cells = <0>; 3334 3335 status = "disabled"; 3336 }; 3337 3338 mdss1_dp1_phy: phy@890ca00 { 3339 compatible = "qcom,sc8280xp-dp-phy"; 3340 reg = <0 0x0890ca00 0 0x19c>, 3341 <0 0x0890c200 0 0xec>, 3342 <0 0x0890c600 0 0xec>, 3343 <0 0x0890c000 0 0x1c8>; 3344 3345 clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 3346 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 3347 clock-names = "aux", "cfg_ahb"; 3348 power-domains = <&rpmhpd SC8280XP_MX>; 3349 3350 #clock-cells = <1>; 3351 #phy-cells = <0>; 3352 3353 status = "disabled"; 3354 }; 3355 3356 pmu@9091000 { 3357 compatible = "qcom,sc8280xp-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3358 reg = <0 0x09091000 0 0x1000>; 3359 3360 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 3361 3362 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 3363 3364 operating-points-v2 = <&llcc_bwmon_opp_table>; 3365 3366 llcc_bwmon_opp_table: opp-table { 3367 compatible = "operating-points-v2"; 3368 3369 opp-0 { 3370 opp-peak-kBps = <762000>; 3371 }; 3372 opp-1 { 3373 opp-peak-kBps = <1720000>; 3374 }; 3375 opp-2 { 3376 opp-peak-kBps = <2086000>; 3377 }; 3378 opp-3 { 3379 opp-peak-kBps = <2597000>; 3380 }; 3381 opp-4 { 3382 opp-peak-kBps = <2929000>; 3383 }; 3384 opp-5 { 3385 opp-peak-kBps = <3879000>; 3386 }; 3387 opp-6 { 3388 opp-peak-kBps = <5161000>; 3389 }; 3390 opp-7 { 3391 opp-peak-kBps = <5931000>; 3392 }; 3393 opp-8 { 3394 opp-peak-kBps = <6515000>; 3395 }; 3396 opp-9 { 3397 opp-peak-kBps = <7980000>; 3398 }; 3399 opp-10 { 3400 opp-peak-kBps = <8136000>; 3401 }; 3402 opp-11 { 3403 opp-peak-kBps = <10437000>; 3404 }; 3405 opp-12 { 3406 opp-peak-kBps = <12191000>; 3407 }; 3408 }; 3409 }; 3410 3411 pmu@90b6400 { 3412 compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon"; 3413 reg = <0 0x090b6400 0 0x600>; 3414 3415 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3416 3417 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 3418 operating-points-v2 = <&cpu_bwmon_opp_table>; 3419 3420 cpu_bwmon_opp_table: opp-table { 3421 compatible = "operating-points-v2"; 3422 3423 opp-0 { 3424 opp-peak-kBps = <2288000>; 3425 }; 3426 opp-1 { 3427 opp-peak-kBps = <4577000>; 3428 }; 3429 opp-2 { 3430 opp-peak-kBps = <7110000>; 3431 }; 3432 opp-3 { 3433 opp-peak-kBps = <9155000>; 3434 }; 3435 opp-4 { 3436 opp-peak-kBps = <12298000>; 3437 }; 3438 opp-5 { 3439 opp-peak-kBps = <14236000>; 3440 }; 3441 opp-6 { 3442 opp-peak-kBps = <15258001>; 3443 }; 3444 }; 3445 }; 3446 3447 system-cache-controller@9200000 { 3448 compatible = "qcom,sc8280xp-llcc"; 3449 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 3450 <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, 3451 <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, 3452 <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, 3453 <0 0x09600000 0 0x58000>; 3454 reg-names = "llcc0_base", "llcc1_base", "llcc2_base", 3455 "llcc3_base", "llcc4_base", "llcc5_base", 3456 "llcc6_base", "llcc7_base", "llcc_broadcast_base"; 3457 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 3458 }; 3459 3460 usb_2: usb@a4f8800 { 3461 compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; 3462 reg = <0 0x0a4f8800 0 0x400>; 3463 #address-cells = <2>; 3464 #size-cells = <2>; 3465 ranges; 3466 3467 clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, 3468 <&gcc GCC_USB30_MP_MASTER_CLK>, 3469 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, 3470 <&gcc GCC_USB30_MP_SLEEP_CLK>, 3471 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3472 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3473 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3474 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3475 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3476 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3477 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3478 3479 assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, 3480 <&gcc GCC_USB30_MP_MASTER_CLK>; 3481 assigned-clock-rates = <19200000>, <200000000>; 3482 3483 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 3484 <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 3485 <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, 3486 <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 3487 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 3488 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 3489 <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, 3490 <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, 3491 <&pdc 127 IRQ_TYPE_EDGE_BOTH>, 3492 <&pdc 126 IRQ_TYPE_EDGE_BOTH>, 3493 <&pdc 129 IRQ_TYPE_EDGE_BOTH>, 3494 <&pdc 128 IRQ_TYPE_EDGE_BOTH>, 3495 <&pdc 131 IRQ_TYPE_EDGE_BOTH>, 3496 <&pdc 130 IRQ_TYPE_EDGE_BOTH>, 3497 <&pdc 133 IRQ_TYPE_EDGE_BOTH>, 3498 <&pdc 132 IRQ_TYPE_EDGE_BOTH>, 3499 <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, 3500 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 3501 3502 interrupt-names = "pwr_event_1", "pwr_event_2", 3503 "pwr_event_3", "pwr_event_4", 3504 "hs_phy_1", "hs_phy_2", 3505 "hs_phy_3", "hs_phy_4", 3506 "dp_hs_phy_1", "dm_hs_phy_1", 3507 "dp_hs_phy_2", "dm_hs_phy_2", 3508 "dp_hs_phy_3", "dm_hs_phy_3", 3509 "dp_hs_phy_4", "dm_hs_phy_4", 3510 "ss_phy_1", "ss_phy_2"; 3511 3512 power-domains = <&gcc USB30_MP_GDSC>; 3513 required-opps = <&rpmhpd_opp_nom>; 3514 3515 resets = <&gcc GCC_USB30_MP_BCR>; 3516 3517 interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, 3518 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; 3519 interconnect-names = "usb-ddr", "apps-usb"; 3520 3521 wakeup-source; 3522 3523 status = "disabled"; 3524 3525 usb_2_dwc3: usb@a400000 { 3526 compatible = "snps,dwc3"; 3527 reg = <0 0x0a400000 0 0xcd00>; 3528 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 3529 iommus = <&apps_smmu 0x800 0x0>; 3530 phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, 3531 <&usb_2_hsphy1>, <&usb_2_qmpphy1>, 3532 <&usb_2_hsphy2>, 3533 <&usb_2_hsphy3>; 3534 phy-names = "usb2-0", "usb3-0", 3535 "usb2-1", "usb3-1", 3536 "usb2-2", 3537 "usb2-3"; 3538 dr_mode = "host"; 3539 snps,dis-u1-entry-quirk; 3540 snps,dis-u2-entry-quirk; 3541 }; 3542 }; 3543 3544 usb_0: usb@a6f8800 { 3545 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3546 reg = <0 0x0a6f8800 0 0x400>; 3547 #address-cells = <2>; 3548 #size-cells = <2>; 3549 ranges; 3550 3551 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 3552 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 3553 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 3554 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 3555 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3556 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3557 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3558 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3559 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3560 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3561 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3562 3563 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 3564 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 3565 assigned-clock-rates = <19200000>, <200000000>; 3566 3567 interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 3568 <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 3569 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 3570 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 3571 <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; 3572 interrupt-names = "pwr_event", 3573 "hs_phy_irq", 3574 "dp_hs_phy_irq", 3575 "dm_hs_phy_irq", 3576 "ss_phy_irq"; 3577 3578 power-domains = <&gcc USB30_PRIM_GDSC>; 3579 required-opps = <&rpmhpd_opp_nom>; 3580 3581 resets = <&gcc GCC_USB30_PRIM_BCR>; 3582 3583 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 3584 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>; 3585 interconnect-names = "usb-ddr", "apps-usb"; 3586 3587 wakeup-source; 3588 3589 status = "disabled"; 3590 3591 usb_0_dwc3: usb@a600000 { 3592 compatible = "snps,dwc3"; 3593 reg = <0 0x0a600000 0 0xcd00>; 3594 interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>; 3595 iommus = <&apps_smmu 0x820 0x0>; 3596 phys = <&usb_0_hsphy>, <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>; 3597 phy-names = "usb2-phy", "usb3-phy"; 3598 snps,dis-u1-entry-quirk; 3599 snps,dis-u2-entry-quirk; 3600 3601 ports { 3602 #address-cells = <1>; 3603 #size-cells = <0>; 3604 3605 port@0 { 3606 reg = <0>; 3607 3608 usb_0_dwc3_hs: endpoint { 3609 }; 3610 }; 3611 3612 port@1 { 3613 reg = <1>; 3614 3615 usb_0_dwc3_ss: endpoint { 3616 remote-endpoint = <&usb_0_qmpphy_usb_ss_in>; 3617 }; 3618 }; 3619 }; 3620 }; 3621 }; 3622 3623 usb_1: usb@a8f8800 { 3624 compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; 3625 reg = <0 0x0a8f8800 0 0x400>; 3626 #address-cells = <2>; 3627 #size-cells = <2>; 3628 ranges; 3629 3630 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 3631 <&gcc GCC_USB30_SEC_MASTER_CLK>, 3632 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 3633 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 3634 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3635 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, 3636 <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, 3637 <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, 3638 <&gcc GCC_SYS_NOC_USB_AXI_CLK>; 3639 clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", 3640 "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; 3641 3642 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 3643 <&gcc GCC_USB30_SEC_MASTER_CLK>; 3644 assigned-clock-rates = <19200000>, <200000000>; 3645 3646 interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 3647 <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 3648 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 3649 <&pdc 13 IRQ_TYPE_EDGE_BOTH>, 3650 <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; 3651 interrupt-names = "pwr_event", 3652 "hs_phy_irq", 3653 "dp_hs_phy_irq", 3654 "dm_hs_phy_irq", 3655 "ss_phy_irq"; 3656 3657 power-domains = <&gcc USB30_SEC_GDSC>; 3658 required-opps = <&rpmhpd_opp_nom>; 3659 3660 resets = <&gcc GCC_USB30_SEC_BCR>; 3661 3662 interconnects = <&aggre1_noc MASTER_USB3_1 0 &mc_virt SLAVE_EBI1 0>, 3663 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_1 0>; 3664 interconnect-names = "usb-ddr", "apps-usb"; 3665 3666 wakeup-source; 3667 3668 status = "disabled"; 3669 3670 usb_1_dwc3: usb@a800000 { 3671 compatible = "snps,dwc3"; 3672 reg = <0 0x0a800000 0 0xcd00>; 3673 interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>; 3674 iommus = <&apps_smmu 0x860 0x0>; 3675 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 3676 phy-names = "usb2-phy", "usb3-phy"; 3677 snps,dis-u1-entry-quirk; 3678 snps,dis-u2-entry-quirk; 3679 3680 ports { 3681 #address-cells = <1>; 3682 #size-cells = <0>; 3683 3684 port@0 { 3685 reg = <0>; 3686 3687 usb_1_dwc3_hs: endpoint { 3688 }; 3689 }; 3690 3691 port@1 { 3692 reg = <1>; 3693 3694 usb_1_dwc3_ss: endpoint { 3695 remote-endpoint = <&usb_1_qmpphy_usb_ss_in>; 3696 }; 3697 }; 3698 }; 3699 }; 3700 }; 3701 3702 cci0: cci@ac4a000 { 3703 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3704 reg = <0 0x0ac4a000 0 0x1000>; 3705 3706 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 3707 3708 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3709 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3710 <&camcc CAMCC_CPAS_AHB_CLK>, 3711 <&camcc CAMCC_CCI_0_CLK>; 3712 clock-names = "camnoc_axi", 3713 "slow_ahb_src", 3714 "cpas_ahb", 3715 "cci"; 3716 3717 power-domains = <&camcc TITAN_TOP_GDSC>; 3718 3719 pinctrl-0 = <&cci0_default>; 3720 pinctrl-1 = <&cci0_sleep>; 3721 pinctrl-names = "default", "sleep"; 3722 3723 #address-cells = <1>; 3724 #size-cells = <0>; 3725 3726 status = "disabled"; 3727 3728 cci0_i2c0: i2c-bus@0 { 3729 reg = <0>; 3730 clock-frequency = <1000000>; 3731 #address-cells = <1>; 3732 #size-cells = <0>; 3733 }; 3734 3735 cci0_i2c1: i2c-bus@1 { 3736 reg = <1>; 3737 clock-frequency = <1000000>; 3738 #address-cells = <1>; 3739 #size-cells = <0>; 3740 }; 3741 }; 3742 3743 cci1: cci@ac4b000 { 3744 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3745 reg = <0 0x0ac4b000 0 0x1000>; 3746 3747 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 3748 3749 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3750 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3751 <&camcc CAMCC_CPAS_AHB_CLK>, 3752 <&camcc CAMCC_CCI_1_CLK>; 3753 clock-names = "camnoc_axi", 3754 "slow_ahb_src", 3755 "cpas_ahb", 3756 "cci"; 3757 3758 power-domains = <&camcc TITAN_TOP_GDSC>; 3759 3760 pinctrl-0 = <&cci1_default>; 3761 pinctrl-1 = <&cci1_sleep>; 3762 pinctrl-names = "default", "sleep"; 3763 3764 #address-cells = <1>; 3765 #size-cells = <0>; 3766 3767 status = "disabled"; 3768 3769 cci1_i2c0: i2c-bus@0 { 3770 reg = <0>; 3771 clock-frequency = <1000000>; 3772 #address-cells = <1>; 3773 #size-cells = <0>; 3774 }; 3775 3776 cci1_i2c1: i2c-bus@1 { 3777 reg = <1>; 3778 clock-frequency = <1000000>; 3779 #address-cells = <1>; 3780 #size-cells = <0>; 3781 }; 3782 }; 3783 3784 cci2: cci@ac4c000 { 3785 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3786 reg = <0 0x0ac4c000 0 0x1000>; 3787 3788 interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>; 3789 3790 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3791 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3792 <&camcc CAMCC_CPAS_AHB_CLK>, 3793 <&camcc CAMCC_CCI_2_CLK>; 3794 clock-names = "camnoc_axi", 3795 "slow_ahb_src", 3796 "cpas_ahb", 3797 "cci"; 3798 power-domains = <&camcc TITAN_TOP_GDSC>; 3799 3800 pinctrl-0 = <&cci2_default>; 3801 pinctrl-1 = <&cci2_sleep>; 3802 pinctrl-names = "default", "sleep"; 3803 3804 #address-cells = <1>; 3805 #size-cells = <0>; 3806 3807 status = "disabled"; 3808 3809 cci2_i2c0: i2c-bus@0 { 3810 reg = <0>; 3811 clock-frequency = <1000000>; 3812 #address-cells = <1>; 3813 #size-cells = <0>; 3814 }; 3815 3816 cci2_i2c1: i2c-bus@1 { 3817 reg = <1>; 3818 clock-frequency = <1000000>; 3819 #address-cells = <1>; 3820 #size-cells = <0>; 3821 }; 3822 }; 3823 3824 cci3: cci@ac4d000 { 3825 compatible = "qcom,sc8280xp-cci", "qcom,msm8996-cci"; 3826 reg = <0 0x0ac4d000 0 0x1000>; 3827 3828 interrupts = <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 3829 3830 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3831 <&camcc CAMCC_SLOW_AHB_CLK_SRC>, 3832 <&camcc CAMCC_CPAS_AHB_CLK>, 3833 <&camcc CAMCC_CCI_3_CLK>; 3834 clock-names = "camnoc_axi", 3835 "slow_ahb_src", 3836 "cpas_ahb", 3837 "cci"; 3838 3839 power-domains = <&camcc TITAN_TOP_GDSC>; 3840 3841 pinctrl-0 = <&cci3_default>; 3842 pinctrl-1 = <&cci3_sleep>; 3843 pinctrl-names = "default", "sleep"; 3844 3845 #address-cells = <1>; 3846 #size-cells = <0>; 3847 3848 status = "disabled"; 3849 3850 cci3_i2c0: i2c-bus@0 { 3851 reg = <0>; 3852 clock-frequency = <1000000>; 3853 #address-cells = <1>; 3854 #size-cells = <0>; 3855 }; 3856 3857 cci3_i2c1: i2c-bus@1 { 3858 reg = <1>; 3859 clock-frequency = <1000000>; 3860 #address-cells = <1>; 3861 #size-cells = <0>; 3862 }; 3863 }; 3864 3865 camss: camss@ac5a000 { 3866 compatible = "qcom,sc8280xp-camss"; 3867 3868 reg = <0 0x0ac5a000 0 0x2000>, 3869 <0 0x0ac5c000 0 0x2000>, 3870 <0 0x0ac65000 0 0x2000>, 3871 <0 0x0ac67000 0 0x2000>, 3872 <0 0x0acaf000 0 0x4000>, 3873 <0 0x0acb3000 0 0x1000>, 3874 <0 0x0acb6000 0 0x4000>, 3875 <0 0x0acba000 0 0x1000>, 3876 <0 0x0acbd000 0 0x4000>, 3877 <0 0x0acc1000 0 0x1000>, 3878 <0 0x0acc4000 0 0x4000>, 3879 <0 0x0acc8000 0 0x1000>, 3880 <0 0x0accb000 0 0x4000>, 3881 <0 0x0accf000 0 0x1000>, 3882 <0 0x0acd2000 0 0x4000>, 3883 <0 0x0acd6000 0 0x1000>, 3884 <0 0x0acd9000 0 0x4000>, 3885 <0 0x0acdd000 0 0x1000>, 3886 <0 0x0ace0000 0 0x4000>, 3887 <0 0x0ace4000 0 0x1000>; 3888 reg-names = "csiphy2", 3889 "csiphy3", 3890 "csiphy0", 3891 "csiphy1", 3892 "vfe0", 3893 "csid0", 3894 "vfe1", 3895 "csid1", 3896 "vfe2", 3897 "csid2", 3898 "vfe_lite0", 3899 "csid0_lite", 3900 "vfe_lite1", 3901 "csid1_lite", 3902 "vfe_lite2", 3903 "csid2_lite", 3904 "vfe_lite3", 3905 "csid3_lite", 3906 "vfe3", 3907 "csid3"; 3908 3909 interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 3910 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, 3911 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 3912 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 3913 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 3914 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 3915 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 3916 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 3917 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 3918 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 3919 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 3920 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 3921 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 3922 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 3923 <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, 3924 <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, 3925 <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, 3926 <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, 3927 <GIC_SPI 762 IRQ_TYPE_EDGE_RISING>, 3928 <GIC_SPI 764 IRQ_TYPE_EDGE_RISING>; 3929 interrupt-names = "csid1_lite", 3930 "vfe_lite1", 3931 "csiphy3", 3932 "csid0", 3933 "vfe0", 3934 "csid1", 3935 "vfe1", 3936 "csid0_lite", 3937 "vfe_lite0", 3938 "csiphy0", 3939 "csiphy1", 3940 "csiphy2", 3941 "csid2", 3942 "vfe2", 3943 "csid3_lite", 3944 "csid2_lite", 3945 "vfe_lite3", 3946 "vfe_lite2", 3947 "csid3", 3948 "vfe3"; 3949 3950 power-domains = <&camcc IFE_0_GDSC>, 3951 <&camcc IFE_1_GDSC>, 3952 <&camcc IFE_2_GDSC>, 3953 <&camcc IFE_3_GDSC>, 3954 <&camcc TITAN_TOP_GDSC>; 3955 power-domain-names = "ife0", 3956 "ife1", 3957 "ife2", 3958 "ife3", 3959 "top"; 3960 3961 clocks = <&camcc CAMCC_CAMNOC_AXI_CLK>, 3962 <&camcc CAMCC_CPAS_AHB_CLK>, 3963 <&camcc CAMCC_CSIPHY0_CLK>, 3964 <&camcc CAMCC_CSI0PHYTIMER_CLK>, 3965 <&camcc CAMCC_CSIPHY1_CLK>, 3966 <&camcc CAMCC_CSI1PHYTIMER_CLK>, 3967 <&camcc CAMCC_CSIPHY2_CLK>, 3968 <&camcc CAMCC_CSI2PHYTIMER_CLK>, 3969 <&camcc CAMCC_CSIPHY3_CLK>, 3970 <&camcc CAMCC_CSI3PHYTIMER_CLK>, 3971 <&camcc CAMCC_IFE_0_AXI_CLK>, 3972 <&camcc CAMCC_IFE_0_CLK>, 3973 <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, 3974 <&camcc CAMCC_IFE_0_CSID_CLK>, 3975 <&camcc CAMCC_IFE_1_AXI_CLK>, 3976 <&camcc CAMCC_IFE_1_CLK>, 3977 <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, 3978 <&camcc CAMCC_IFE_1_CSID_CLK>, 3979 <&camcc CAMCC_IFE_2_AXI_CLK>, 3980 <&camcc CAMCC_IFE_2_CLK>, 3981 <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, 3982 <&camcc CAMCC_IFE_2_CSID_CLK>, 3983 <&camcc CAMCC_IFE_3_AXI_CLK>, 3984 <&camcc CAMCC_IFE_3_CLK>, 3985 <&camcc CAMCC_IFE_3_CPHY_RX_CLK>, 3986 <&camcc CAMCC_IFE_3_CSID_CLK>, 3987 <&camcc CAMCC_IFE_LITE_0_CLK>, 3988 <&camcc CAMCC_IFE_LITE_0_CPHY_RX_CLK>, 3989 <&camcc CAMCC_IFE_LITE_0_CSID_CLK>, 3990 <&camcc CAMCC_IFE_LITE_1_CLK>, 3991 <&camcc CAMCC_IFE_LITE_1_CPHY_RX_CLK>, 3992 <&camcc CAMCC_IFE_LITE_1_CSID_CLK>, 3993 <&camcc CAMCC_IFE_LITE_2_CLK>, 3994 <&camcc CAMCC_IFE_LITE_2_CPHY_RX_CLK>, 3995 <&camcc CAMCC_IFE_LITE_2_CSID_CLK>, 3996 <&camcc CAMCC_IFE_LITE_3_CLK>, 3997 <&camcc CAMCC_IFE_LITE_3_CPHY_RX_CLK>, 3998 <&camcc CAMCC_IFE_LITE_3_CSID_CLK>, 3999 <&gcc GCC_CAMERA_HF_AXI_CLK>, 4000 <&gcc GCC_CAMERA_SF_AXI_CLK>; 4001 clock-names = "camnoc_axi", 4002 "cpas_ahb", 4003 "csiphy0", 4004 "csiphy0_timer", 4005 "csiphy1", 4006 "csiphy1_timer", 4007 "csiphy2", 4008 "csiphy2_timer", 4009 "csiphy3", 4010 "csiphy3_timer", 4011 "vfe0_axi", 4012 "vfe0", 4013 "vfe0_cphy_rx", 4014 "vfe0_csid", 4015 "vfe1_axi", 4016 "vfe1", 4017 "vfe1_cphy_rx", 4018 "vfe1_csid", 4019 "vfe2_axi", 4020 "vfe2", 4021 "vfe2_cphy_rx", 4022 "vfe2_csid", 4023 "vfe3_axi", 4024 "vfe3", 4025 "vfe3_cphy_rx", 4026 "vfe3_csid", 4027 "vfe_lite0", 4028 "vfe_lite0_cphy_rx", 4029 "vfe_lite0_csid", 4030 "vfe_lite1", 4031 "vfe_lite1_cphy_rx", 4032 "vfe_lite1_csid", 4033 "vfe_lite2", 4034 "vfe_lite2_cphy_rx", 4035 "vfe_lite2_csid", 4036 "vfe_lite3", 4037 "vfe_lite3_cphy_rx", 4038 "vfe_lite3_csid", 4039 "gcc_axi_hf", 4040 "gcc_axi_sf"; 4041 4042 iommus = <&apps_smmu 0x2000 0x4e0>, 4043 <&apps_smmu 0x2020 0x4e0>, 4044 <&apps_smmu 0x2040 0x4e0>, 4045 <&apps_smmu 0x2060 0x4e0>, 4046 <&apps_smmu 0x2080 0x4e0>, 4047 <&apps_smmu 0x20e0 0x4e0>, 4048 <&apps_smmu 0x20c0 0x4e0>, 4049 <&apps_smmu 0x20a0 0x4e0>, 4050 <&apps_smmu 0x2400 0x4e0>, 4051 <&apps_smmu 0x2420 0x4e0>, 4052 <&apps_smmu 0x2440 0x4e0>, 4053 <&apps_smmu 0x2460 0x4e0>, 4054 <&apps_smmu 0x2480 0x4e0>, 4055 <&apps_smmu 0x24e0 0x4e0>, 4056 <&apps_smmu 0x24c0 0x4e0>, 4057 <&apps_smmu 0x24a0 0x4e0>; 4058 4059 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_CAMERA_CFG 0>, 4060 <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>, 4061 <&mmss_noc MASTER_CAMNOC_SF 0 &mc_virt SLAVE_EBI1 0>, 4062 <&mmss_noc MASTER_CAMNOC_ICP 0 &mc_virt SLAVE_EBI1 0>; 4063 interconnect-names = "cam_ahb", 4064 "cam_hf_mnoc", 4065 "cam_sf_mnoc", 4066 "cam_sf_icp_mnoc"; 4067 4068 status = "disabled"; 4069 4070 ports { 4071 #address-cells = <1>; 4072 #size-cells = <0>; 4073 4074 port@0 { 4075 reg = <0>; 4076 #address-cells = <1>; 4077 #size-cells = <0>; 4078 }; 4079 4080 port@1 { 4081 reg = <1>; 4082 #address-cells = <1>; 4083 #size-cells = <0>; 4084 }; 4085 4086 port@2 { 4087 reg = <2>; 4088 #address-cells = <1>; 4089 #size-cells = <0>; 4090 }; 4091 4092 port@3 { 4093 reg = <3>; 4094 #address-cells = <1>; 4095 #size-cells = <0>; 4096 }; 4097 }; 4098 }; 4099 4100 camcc: clock-controller@ad00000 { 4101 compatible = "qcom,sc8280xp-camcc"; 4102 reg = <0 0x0ad00000 0 0x20000>; 4103 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4104 <&rpmhcc RPMH_CXO_CLK>, 4105 <&rpmhcc RPMH_CXO_CLK_A>, 4106 <&sleep_clk>; 4107 power-domains = <&rpmhpd SC8280XP_MMCX>; 4108 required-opps = <&rpmhpd_opp_low_svs>; 4109 #clock-cells = <1>; 4110 #reset-cells = <1>; 4111 #power-domain-cells = <1>; 4112 }; 4113 4114 mdss0: display-subsystem@ae00000 { 4115 compatible = "qcom,sc8280xp-mdss"; 4116 reg = <0 0x0ae00000 0 0x1000>; 4117 reg-names = "mdss"; 4118 4119 clocks = <&gcc GCC_DISP_AHB_CLK>, 4120 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4121 <&dispcc0 DISP_CC_MDSS_MDP_CLK>; 4122 clock-names = "iface", 4123 "ahb", 4124 "core"; 4125 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 4126 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>, 4127 <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>; 4128 interconnect-names = "mdp0-mem", "mdp1-mem"; 4129 iommus = <&apps_smmu 0x1000 0x402>; 4130 power-domains = <&dispcc0 MDSS_GDSC>; 4131 resets = <&dispcc0 DISP_CC_MDSS_CORE_BCR>; 4132 4133 interrupt-controller; 4134 #interrupt-cells = <1>; 4135 #address-cells = <2>; 4136 #size-cells = <2>; 4137 ranges; 4138 4139 status = "disabled"; 4140 4141 mdss0_mdp: display-controller@ae01000 { 4142 compatible = "qcom,sc8280xp-dpu"; 4143 reg = <0 0x0ae01000 0 0x8f000>, 4144 <0 0x0aeb0000 0 0x2008>; 4145 reg-names = "mdp", "vbif"; 4146 4147 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 4148 <&gcc GCC_DISP_SF_AXI_CLK>, 4149 <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4150 <&dispcc0 DISP_CC_MDSS_MDP_LUT_CLK>, 4151 <&dispcc0 DISP_CC_MDSS_MDP_CLK>, 4152 <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4153 clock-names = "bus", 4154 "nrt_bus", 4155 "iface", 4156 "lut", 4157 "core", 4158 "vsync"; 4159 interrupt-parent = <&mdss0>; 4160 interrupts = <0>; 4161 power-domains = <&rpmhpd SC8280XP_MMCX>; 4162 4163 assigned-clocks = <&dispcc0 DISP_CC_MDSS_VSYNC_CLK>; 4164 assigned-clock-rates = <19200000>; 4165 operating-points-v2 = <&mdss0_mdp_opp_table>; 4166 4167 ports { 4168 #address-cells = <1>; 4169 #size-cells = <0>; 4170 4171 port@0 { 4172 reg = <0>; 4173 mdss0_intf0_out: endpoint { 4174 remote-endpoint = <&mdss0_dp0_in>; 4175 }; 4176 }; 4177 4178 port@4 { 4179 reg = <4>; 4180 mdss0_intf4_out: endpoint { 4181 remote-endpoint = <&mdss0_dp1_in>; 4182 }; 4183 }; 4184 4185 port@5 { 4186 reg = <5>; 4187 mdss0_intf5_out: endpoint { 4188 remote-endpoint = <&mdss0_dp3_in>; 4189 }; 4190 }; 4191 4192 port@6 { 4193 reg = <6>; 4194 mdss0_intf6_out: endpoint { 4195 remote-endpoint = <&mdss0_dp2_in>; 4196 }; 4197 }; 4198 }; 4199 4200 mdss0_mdp_opp_table: opp-table { 4201 compatible = "operating-points-v2"; 4202 4203 opp-200000000 { 4204 opp-hz = /bits/ 64 <200000000>; 4205 required-opps = <&rpmhpd_opp_low_svs>; 4206 }; 4207 4208 opp-300000000 { 4209 opp-hz = /bits/ 64 <300000000>; 4210 required-opps = <&rpmhpd_opp_svs>; 4211 }; 4212 4213 opp-375000000 { 4214 opp-hz = /bits/ 64 <375000000>; 4215 required-opps = <&rpmhpd_opp_svs_l1>; 4216 }; 4217 4218 opp-500000000 { 4219 opp-hz = /bits/ 64 <500000000>; 4220 required-opps = <&rpmhpd_opp_nom>; 4221 }; 4222 opp-600000000 { 4223 opp-hz = /bits/ 64 <600000000>; 4224 required-opps = <&rpmhpd_opp_turbo_l1>; 4225 }; 4226 }; 4227 }; 4228 4229 mdss0_dp0: displayport-controller@ae90000 { 4230 compatible = "qcom,sc8280xp-dp"; 4231 reg = <0 0xae90000 0 0x200>, 4232 <0 0xae90200 0 0x200>, 4233 <0 0xae90400 0 0x600>, 4234 <0 0xae91000 0 0x400>, 4235 <0 0xae91400 0 0x400>; 4236 interrupt-parent = <&mdss0>; 4237 interrupts = <12>; 4238 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4239 <&dispcc0 DISP_CC_MDSS_DPTX0_AUX_CLK>, 4240 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK>, 4241 <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 4242 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 4243 clock-names = "core_iface", "core_aux", 4244 "ctrl_link", 4245 "ctrl_link_iface", 4246 "stream_pixel"; 4247 4248 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 4249 <&dispcc0 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 4250 assigned-clock-parents = <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4251 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4252 4253 phys = <&usb_0_qmpphy QMP_USB43DP_DP_PHY>; 4254 phy-names = "dp"; 4255 4256 #sound-dai-cells = <0>; 4257 4258 operating-points-v2 = <&mdss0_dp0_opp_table>; 4259 power-domains = <&rpmhpd SC8280XP_MMCX>; 4260 4261 status = "disabled"; 4262 4263 ports { 4264 #address-cells = <1>; 4265 #size-cells = <0>; 4266 4267 port@0 { 4268 reg = <0>; 4269 4270 mdss0_dp0_in: endpoint { 4271 remote-endpoint = <&mdss0_intf0_out>; 4272 }; 4273 }; 4274 4275 port@1 { 4276 reg = <1>; 4277 4278 mdss0_dp0_out: endpoint { 4279 }; 4280 }; 4281 }; 4282 4283 mdss0_dp0_opp_table: opp-table { 4284 compatible = "operating-points-v2"; 4285 4286 opp-160000000 { 4287 opp-hz = /bits/ 64 <160000000>; 4288 required-opps = <&rpmhpd_opp_low_svs>; 4289 }; 4290 4291 opp-270000000 { 4292 opp-hz = /bits/ 64 <270000000>; 4293 required-opps = <&rpmhpd_opp_svs>; 4294 }; 4295 4296 opp-540000000 { 4297 opp-hz = /bits/ 64 <540000000>; 4298 required-opps = <&rpmhpd_opp_svs_l1>; 4299 }; 4300 4301 opp-810000000 { 4302 opp-hz = /bits/ 64 <810000000>; 4303 required-opps = <&rpmhpd_opp_nom>; 4304 }; 4305 }; 4306 }; 4307 4308 mdss0_dp1: displayport-controller@ae98000 { 4309 compatible = "qcom,sc8280xp-dp"; 4310 reg = <0 0xae98000 0 0x200>, 4311 <0 0xae98200 0 0x200>, 4312 <0 0xae98400 0 0x600>, 4313 <0 0xae99000 0 0x400>, 4314 <0 0xae99400 0 0x400>; 4315 interrupt-parent = <&mdss0>; 4316 interrupts = <13>; 4317 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4318 <&dispcc0 DISP_CC_MDSS_DPTX1_AUX_CLK>, 4319 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK>, 4320 <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 4321 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 4322 clock-names = "core_iface", "core_aux", 4323 "ctrl_link", 4324 "ctrl_link_iface", "stream_pixel"; 4325 4326 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 4327 <&dispcc0 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 4328 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4329 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 4330 4331 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 4332 phy-names = "dp"; 4333 4334 #sound-dai-cells = <0>; 4335 4336 operating-points-v2 = <&mdss0_dp1_opp_table>; 4337 power-domains = <&rpmhpd SC8280XP_MMCX>; 4338 4339 status = "disabled"; 4340 4341 ports { 4342 #address-cells = <1>; 4343 #size-cells = <0>; 4344 4345 port@0 { 4346 reg = <0>; 4347 4348 mdss0_dp1_in: endpoint { 4349 remote-endpoint = <&mdss0_intf4_out>; 4350 }; 4351 }; 4352 4353 port@1 { 4354 reg = <1>; 4355 4356 mdss0_dp1_out: endpoint { 4357 }; 4358 }; 4359 }; 4360 4361 mdss0_dp1_opp_table: opp-table { 4362 compatible = "operating-points-v2"; 4363 4364 opp-160000000 { 4365 opp-hz = /bits/ 64 <160000000>; 4366 required-opps = <&rpmhpd_opp_low_svs>; 4367 }; 4368 4369 opp-270000000 { 4370 opp-hz = /bits/ 64 <270000000>; 4371 required-opps = <&rpmhpd_opp_svs>; 4372 }; 4373 4374 opp-540000000 { 4375 opp-hz = /bits/ 64 <540000000>; 4376 required-opps = <&rpmhpd_opp_svs_l1>; 4377 }; 4378 4379 opp-810000000 { 4380 opp-hz = /bits/ 64 <810000000>; 4381 required-opps = <&rpmhpd_opp_nom>; 4382 }; 4383 }; 4384 }; 4385 4386 mdss0_dp2: displayport-controller@ae9a000 { 4387 compatible = "qcom,sc8280xp-dp"; 4388 reg = <0 0xae9a000 0 0x200>, 4389 <0 0xae9a200 0 0x200>, 4390 <0 0xae9a400 0 0x600>, 4391 <0 0xae9b000 0 0x400>, 4392 <0 0xae9b400 0 0x400>; 4393 4394 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4395 <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4396 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK>, 4397 <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 4398 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 4399 clock-names = "core_iface", "core_aux", 4400 "ctrl_link", 4401 "ctrl_link_iface", "stream_pixel"; 4402 interrupt-parent = <&mdss0>; 4403 interrupts = <14>; 4404 phys = <&mdss0_dp2_phy>; 4405 phy-names = "dp"; 4406 power-domains = <&rpmhpd SC8280XP_MMCX>; 4407 4408 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 4409 <&dispcc0 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 4410 assigned-clock-parents = <&mdss0_dp2_phy 0>, <&mdss0_dp2_phy 1>; 4411 operating-points-v2 = <&mdss0_dp2_opp_table>; 4412 4413 #sound-dai-cells = <0>; 4414 4415 status = "disabled"; 4416 4417 ports { 4418 #address-cells = <1>; 4419 #size-cells = <0>; 4420 4421 port@0 { 4422 reg = <0>; 4423 mdss0_dp2_in: endpoint { 4424 remote-endpoint = <&mdss0_intf6_out>; 4425 }; 4426 }; 4427 4428 port@1 { 4429 reg = <1>; 4430 }; 4431 }; 4432 4433 mdss0_dp2_opp_table: opp-table { 4434 compatible = "operating-points-v2"; 4435 4436 opp-160000000 { 4437 opp-hz = /bits/ 64 <160000000>; 4438 required-opps = <&rpmhpd_opp_low_svs>; 4439 }; 4440 4441 opp-270000000 { 4442 opp-hz = /bits/ 64 <270000000>; 4443 required-opps = <&rpmhpd_opp_svs>; 4444 }; 4445 4446 opp-540000000 { 4447 opp-hz = /bits/ 64 <540000000>; 4448 required-opps = <&rpmhpd_opp_svs_l1>; 4449 }; 4450 4451 opp-810000000 { 4452 opp-hz = /bits/ 64 <810000000>; 4453 required-opps = <&rpmhpd_opp_nom>; 4454 }; 4455 }; 4456 }; 4457 4458 mdss0_dp3: displayport-controller@aea0000 { 4459 compatible = "qcom,sc8280xp-dp"; 4460 reg = <0 0xaea0000 0 0x200>, 4461 <0 0xaea0200 0 0x200>, 4462 <0 0xaea0400 0 0x600>, 4463 <0 0xaea1000 0 0x400>, 4464 <0 0xaea1400 0 0x400>; 4465 4466 clocks = <&dispcc0 DISP_CC_MDSS_AHB_CLK>, 4467 <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4468 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK>, 4469 <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 4470 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 4471 clock-names = "core_iface", "core_aux", 4472 "ctrl_link", 4473 "ctrl_link_iface", "stream_pixel"; 4474 interrupt-parent = <&mdss0>; 4475 interrupts = <15>; 4476 phys = <&mdss0_dp3_phy>; 4477 phy-names = "dp"; 4478 power-domains = <&rpmhpd SC8280XP_MMCX>; 4479 4480 assigned-clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 4481 <&dispcc0 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 4482 assigned-clock-parents = <&mdss0_dp3_phy 0>, <&mdss0_dp3_phy 1>; 4483 operating-points-v2 = <&mdss0_dp3_opp_table>; 4484 4485 #sound-dai-cells = <0>; 4486 4487 status = "disabled"; 4488 4489 ports { 4490 #address-cells = <1>; 4491 #size-cells = <0>; 4492 4493 port@0 { 4494 reg = <0>; 4495 mdss0_dp3_in: endpoint { 4496 remote-endpoint = <&mdss0_intf5_out>; 4497 }; 4498 }; 4499 4500 port@1 { 4501 reg = <1>; 4502 }; 4503 }; 4504 4505 mdss0_dp3_opp_table: opp-table { 4506 compatible = "operating-points-v2"; 4507 4508 opp-160000000 { 4509 opp-hz = /bits/ 64 <160000000>; 4510 required-opps = <&rpmhpd_opp_low_svs>; 4511 }; 4512 4513 opp-270000000 { 4514 opp-hz = /bits/ 64 <270000000>; 4515 required-opps = <&rpmhpd_opp_svs>; 4516 }; 4517 4518 opp-540000000 { 4519 opp-hz = /bits/ 64 <540000000>; 4520 required-opps = <&rpmhpd_opp_svs_l1>; 4521 }; 4522 4523 opp-810000000 { 4524 opp-hz = /bits/ 64 <810000000>; 4525 required-opps = <&rpmhpd_opp_nom>; 4526 }; 4527 }; 4528 }; 4529 }; 4530 4531 mdss0_dp2_phy: phy@aec2a00 { 4532 compatible = "qcom,sc8280xp-dp-phy"; 4533 reg = <0 0x0aec2a00 0 0x19c>, 4534 <0 0x0aec2200 0 0xec>, 4535 <0 0x0aec2600 0 0xec>, 4536 <0 0x0aec2000 0 0x1c8>; 4537 4538 clocks = <&dispcc0 DISP_CC_MDSS_DPTX2_AUX_CLK>, 4539 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4540 clock-names = "aux", "cfg_ahb"; 4541 power-domains = <&rpmhpd SC8280XP_MX>; 4542 4543 #clock-cells = <1>; 4544 #phy-cells = <0>; 4545 4546 status = "disabled"; 4547 }; 4548 4549 mdss0_dp3_phy: phy@aec5a00 { 4550 compatible = "qcom,sc8280xp-dp-phy"; 4551 reg = <0 0x0aec5a00 0 0x19c>, 4552 <0 0x0aec5200 0 0xec>, 4553 <0 0x0aec5600 0 0xec>, 4554 <0 0x0aec5000 0 0x1c8>; 4555 4556 clocks = <&dispcc0 DISP_CC_MDSS_DPTX3_AUX_CLK>, 4557 <&dispcc0 DISP_CC_MDSS_AHB_CLK>; 4558 clock-names = "aux", "cfg_ahb"; 4559 power-domains = <&rpmhpd SC8280XP_MX>; 4560 4561 #clock-cells = <1>; 4562 #phy-cells = <0>; 4563 4564 status = "disabled"; 4565 }; 4566 4567 dispcc0: clock-controller@af00000 { 4568 compatible = "qcom,sc8280xp-dispcc0"; 4569 reg = <0 0x0af00000 0 0x20000>; 4570 4571 clocks = <&gcc GCC_DISP_AHB_CLK>, 4572 <&rpmhcc RPMH_CXO_CLK>, 4573 <&sleep_clk>, 4574 <&usb_0_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4575 <&usb_0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4576 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 4577 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 4578 <&mdss0_dp2_phy 0>, 4579 <&mdss0_dp2_phy 1>, 4580 <&mdss0_dp3_phy 0>, 4581 <&mdss0_dp3_phy 1>, 4582 <0>, 4583 <0>, 4584 <0>, 4585 <0>; 4586 power-domains = <&rpmhpd SC8280XP_MMCX>; 4587 4588 #clock-cells = <1>; 4589 #power-domain-cells = <1>; 4590 #reset-cells = <1>; 4591 4592 status = "disabled"; 4593 }; 4594 4595 pdc: interrupt-controller@b220000 { 4596 compatible = "qcom,sc8280xp-pdc", "qcom,pdc"; 4597 reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x60>; 4598 qcom,pdc-ranges = <0 480 40>, 4599 <40 140 14>, 4600 <54 263 1>, 4601 <55 306 4>, 4602 <59 312 3>, 4603 <62 374 2>, 4604 <64 434 2>, 4605 <66 438 3>, 4606 <69 86 1>, 4607 <70 520 54>, 4608 <124 609 28>, 4609 <159 638 1>, 4610 <160 720 8>, 4611 <168 801 1>, 4612 <169 728 30>, 4613 <199 416 2>, 4614 <201 449 1>, 4615 <202 89 1>, 4616 <203 451 1>, 4617 <204 462 1>, 4618 <205 264 1>, 4619 <206 579 1>, 4620 <207 653 1>, 4621 <208 656 1>, 4622 <209 659 1>, 4623 <210 122 1>, 4624 <211 699 1>, 4625 <212 705 1>, 4626 <213 450 1>, 4627 <214 643 1>, 4628 <216 646 5>, 4629 <221 390 5>, 4630 <226 700 3>, 4631 <229 240 3>, 4632 <232 269 1>, 4633 <233 377 1>, 4634 <234 372 1>, 4635 <235 138 1>, 4636 <236 857 1>, 4637 <237 860 1>, 4638 <238 137 1>, 4639 <239 668 1>, 4640 <240 366 1>, 4641 <241 949 1>, 4642 <242 815 5>, 4643 <247 769 1>, 4644 <248 768 1>, 4645 <249 663 1>, 4646 <250 799 2>, 4647 <252 798 1>, 4648 <253 765 1>, 4649 <254 763 1>, 4650 <255 454 1>, 4651 <258 139 1>, 4652 <259 786 2>, 4653 <261 370 2>, 4654 <263 158 2>; 4655 #interrupt-cells = <2>; 4656 interrupt-parent = <&intc>; 4657 interrupt-controller; 4658 }; 4659 4660 tsens2: thermal-sensor@c251000 { 4661 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4662 reg = <0 0x0c251000 0 0x1ff>, 4663 <0 0x0c224000 0 0x8>; 4664 #qcom,sensors = <11>; 4665 interrupts-extended = <&pdc 122 IRQ_TYPE_LEVEL_HIGH>, 4666 <&pdc 124 IRQ_TYPE_LEVEL_HIGH>; 4667 interrupt-names = "uplow", "critical"; 4668 #thermal-sensor-cells = <1>; 4669 }; 4670 4671 tsens3: thermal-sensor@c252000 { 4672 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4673 reg = <0 0x0c252000 0 0x1ff>, 4674 <0 0x0c225000 0 0x8>; 4675 #qcom,sensors = <5>; 4676 interrupts-extended = <&pdc 123 IRQ_TYPE_LEVEL_HIGH>, 4677 <&pdc 125 IRQ_TYPE_LEVEL_HIGH>; 4678 interrupt-names = "uplow", "critical"; 4679 #thermal-sensor-cells = <1>; 4680 }; 4681 4682 tsens0: thermal-sensor@c263000 { 4683 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4684 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 4685 <0 0x0c222000 0 0x8>; /* SROT */ 4686 #qcom,sensors = <14>; 4687 interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, 4688 <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; 4689 interrupt-names = "uplow", "critical"; 4690 #thermal-sensor-cells = <1>; 4691 }; 4692 4693 restart@c264000 { 4694 compatible = "qcom,pshold"; 4695 reg = <0 0x0c264000 0 0x4>; 4696 /* TZ seems to block access */ 4697 status = "reserved"; 4698 }; 4699 4700 tsens1: thermal-sensor@c265000 { 4701 compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; 4702 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 4703 <0 0x0c223000 0 0x8>; /* SROT */ 4704 #qcom,sensors = <16>; 4705 interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, 4706 <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; 4707 interrupt-names = "uplow", "critical"; 4708 #thermal-sensor-cells = <1>; 4709 }; 4710 4711 aoss_qmp: power-management@c300000 { 4712 compatible = "qcom,sc8280xp-aoss-qmp", "qcom,aoss-qmp"; 4713 reg = <0 0x0c300000 0 0x400>; 4714 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP IRQ_TYPE_EDGE_RISING>; 4715 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4716 4717 #clock-cells = <0>; 4718 }; 4719 4720 sram@c3f0000 { 4721 compatible = "qcom,rpmh-stats"; 4722 reg = <0 0x0c3f0000 0 0x400>; 4723 qcom,qmp = <&aoss_qmp>; 4724 }; 4725 4726 spmi_bus: spmi@c440000 { 4727 compatible = "qcom,spmi-pmic-arb"; 4728 reg = <0 0x0c440000 0 0x1100>, 4729 <0 0x0c600000 0 0x2000000>, 4730 <0 0x0e600000 0 0x100000>, 4731 <0 0x0e700000 0 0xa0000>, 4732 <0 0x0c40a000 0 0x26000>; 4733 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 4734 interrupt-names = "periph_irq"; 4735 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4736 qcom,ee = <0>; 4737 qcom,channel = <0>; 4738 #address-cells = <2>; 4739 #size-cells = <0>; 4740 interrupt-controller; 4741 #interrupt-cells = <4>; 4742 }; 4743 4744 tlmm: pinctrl@f100000 { 4745 compatible = "qcom,sc8280xp-tlmm"; 4746 reg = <0 0x0f100000 0 0x300000>; 4747 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4748 gpio-controller; 4749 #gpio-cells = <2>; 4750 interrupt-controller; 4751 #interrupt-cells = <2>; 4752 gpio-ranges = <&tlmm 0 0 230>; 4753 wakeup-parent = <&pdc>; 4754 4755 cci0_default: cci0-default-state { 4756 cci0_i2c0_default: cci0-i2c0-default-pins { 4757 /* cci_i2c_sda0, cci_i2c_scl0 */ 4758 pins = "gpio113", "gpio114"; 4759 function = "cci_i2c"; 4760 drive-strength = <2>; 4761 bias-pull-up; 4762 }; 4763 4764 cci0_i2c1_default: cci0-i2c1-default-pins { 4765 /* cci_i2c_sda1, cci_i2c_scl1 */ 4766 pins = "gpio115", "gpio116"; 4767 function = "cci_i2c"; 4768 drive-strength = <2>; 4769 bias-pull-up; 4770 }; 4771 }; 4772 4773 cci0_sleep: cci0-sleep-state { 4774 cci0_i2c0_sleep: cci0-i2c0-sleep-pins { 4775 /* cci_i2c_sda0, cci_i2c_scl0 */ 4776 pins = "gpio113", "gpio114"; 4777 function = "cci_i2c"; 4778 drive-strength = <2>; 4779 bias-pull-down; 4780 }; 4781 4782 cci0_i2c1_sleep: cci0-i2c1-sleep-pins { 4783 /* cci_i2c_sda1, cci_i2c_scl1 */ 4784 pins = "gpio115", "gpio116"; 4785 function = "cci_i2c"; 4786 drive-strength = <2>; 4787 bias-pull-down; 4788 }; 4789 }; 4790 4791 cci1_default: cci1-default-state { 4792 cci1_i2c0_default: cci1-i2c0-default-pins { 4793 /* cci_i2c_sda2, cci_i2c_scl2 */ 4794 pins = "gpio10","gpio11"; 4795 function = "cci_i2c"; 4796 drive-strength = <2>; 4797 bias-pull-up; 4798 }; 4799 4800 cci1_i2c1_default: cci1-i2c1-default-pins { 4801 /* cci_i2c_sda3, cci_i2c_scl3 */ 4802 pins = "gpio123","gpio124"; 4803 function = "cci_i2c"; 4804 drive-strength = <2>; 4805 bias-pull-up; 4806 }; 4807 }; 4808 4809 cci1_sleep: cci1-sleep-state { 4810 cci1_i2c0_sleep: cci1-i2c0-sleep-pins { 4811 /* cci_i2c_sda2, cci_i2c_scl2 */ 4812 pins = "gpio10","gpio11"; 4813 function = "cci_i2c"; 4814 drive-strength = <2>; 4815 bias-pull-down; 4816 }; 4817 4818 cci1_i2c1_sleep: cci1-i2c1-sleep-pins { 4819 /* cci_i2c_sda3, cci_i2c_scl3 */ 4820 pins = "gpio123","gpio124"; 4821 function = "cci_i2c"; 4822 drive-strength = <2>; 4823 bias-pull-down; 4824 }; 4825 }; 4826 4827 cci2_default: cci2-default-state { 4828 cci2_i2c0_default: cci2-i2c0-default-pins { 4829 /* cci_i2c_sda4, cci_i2c_scl4 */ 4830 pins = "gpio117","gpio118"; 4831 function = "cci_i2c"; 4832 drive-strength = <2>; 4833 bias-pull-up; 4834 }; 4835 4836 cci2_i2c1_default: cci2-i2c1-default-pins { 4837 /* cci_i2c_sda5, cci_i2c_scl5 */ 4838 pins = "gpio12","gpio13"; 4839 function = "cci_i2c"; 4840 drive-strength = <2>; 4841 bias-pull-up; 4842 }; 4843 }; 4844 4845 cci2_sleep: cci2-sleep-state { 4846 cci2_i2c0_sleep: cci2-i2c0-sleep-pins { 4847 /* cci_i2c_sda4, cci_i2c_scl4 */ 4848 pins = "gpio117","gpio118"; 4849 function = "cci_i2c"; 4850 drive-strength = <2>; 4851 bias-pull-down; 4852 }; 4853 4854 cci2_i2c1_sleep: cci2-i2c1-sleep-pins { 4855 /* cci_i2c_sda5, cci_i2c_scl5 */ 4856 pins = "gpio12","gpio13"; 4857 function = "cci_i2c"; 4858 drive-strength = <2>; 4859 bias-pull-down; 4860 }; 4861 }; 4862 4863 cci3_default: cci3-default-state { 4864 cci3_i2c0_default: cci3-i2c0-default-pins { 4865 /* cci_i2c_sda6, cci_i2c_scl6 */ 4866 pins = "gpio145","gpio146"; 4867 function = "cci_i2c"; 4868 drive-strength = <2>; 4869 bias-pull-up; 4870 }; 4871 4872 cci3_i2c1_default: cci3-i2c1-default-pins { 4873 /* cci_i2c_sda7, cci_i2c_scl7 */ 4874 pins = "gpio164","gpio165"; 4875 function = "cci_i2c"; 4876 drive-strength = <2>; 4877 bias-pull-up; 4878 }; 4879 }; 4880 4881 cci3_sleep: cci3-sleep-state { 4882 cci3_i2c0_sleep: cci3-i2c0-sleep-pins { 4883 /* cci_i2c_sda6, cci_i2c_scl6 */ 4884 pins = "gpio145","gpio146"; 4885 function = "cci_i2c"; 4886 drive-strength = <2>; 4887 bias-pull-down; 4888 }; 4889 4890 cci3_i2c1_sleep: cci3-i2c1-sleep-pins { 4891 /* cci_i2c_sda7, cci_i2c_scl7 */ 4892 pins = "gpio164","gpio165"; 4893 function = "cci_i2c"; 4894 drive-strength = <2>; 4895 bias-pull-down; 4896 }; 4897 }; 4898 4899 qup_uart18_default: qup-uart18-default-state { 4900 cts-pins { 4901 pins = "gpio66"; 4902 function = "qup18"; 4903 drive-strength = <2>; 4904 bias-disable; 4905 }; 4906 4907 rts-pins { 4908 pins = "gpio67"; 4909 function = "qup18"; 4910 drive-strength = <2>; 4911 bias-disable; 4912 }; 4913 4914 tx-pins { 4915 pins = "gpio68"; 4916 function = "qup18"; 4917 drive-strength = <2>; 4918 bias-disable; 4919 }; 4920 4921 rx-pins { 4922 pins = "gpio69"; 4923 function = "qup18"; 4924 drive-strength = <2>; 4925 bias-disable; 4926 }; 4927 }; 4928 }; 4929 4930 apps_smmu: iommu@15000000 { 4931 compatible = "qcom,sc8280xp-smmu-500", "arm,mmu-500"; 4932 reg = <0 0x15000000 0 0x100000>; 4933 #iommu-cells = <2>; 4934 #global-interrupts = <2>; 4935 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 4936 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4937 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4938 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4939 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4940 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4941 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4942 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4943 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4944 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4945 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4946 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4947 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4948 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4949 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4950 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4951 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4952 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4953 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4954 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4955 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4956 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4957 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4958 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4959 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4960 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4961 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4962 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4963 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4964 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4965 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4966 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4967 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4968 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4969 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4970 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4971 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4972 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4973 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4974 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4975 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4976 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4977 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4978 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4979 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4980 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4981 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4982 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4983 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4984 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4985 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4986 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4987 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4988 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4989 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4990 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4991 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 4992 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 4993 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 4994 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 4995 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 4996 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 4997 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 4998 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 4999 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5000 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5001 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5002 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5003 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5004 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5005 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5006 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5007 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5008 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5009 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5010 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5011 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5012 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5013 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5014 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5015 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5016 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5017 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5018 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5019 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5020 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5021 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5022 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5023 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5024 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5025 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5026 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5027 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5028 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5029 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5030 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5031 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5032 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5033 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5034 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5035 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5036 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5037 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5038 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5039 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5040 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5041 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5042 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5043 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5044 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5045 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5046 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5047 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5048 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5049 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5050 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5051 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5052 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5053 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5054 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5055 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5056 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5057 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5058 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5059 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>, 5060 <GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>, 5061 <GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>, 5062 <GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>, 5063 <GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>, 5064 <GIC_SPI 890 IRQ_TYPE_LEVEL_HIGH>; 5065 dma-coherent; 5066 }; 5067 5068 intc: interrupt-controller@17a00000 { 5069 compatible = "arm,gic-v3"; 5070 interrupt-controller; 5071 #interrupt-cells = <3>; 5072 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 5073 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 5074 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5075 #redistributor-regions = <1>; 5076 redistributor-stride = <0 0x20000>; 5077 5078 #address-cells = <2>; 5079 #size-cells = <2>; 5080 ranges; 5081 5082 its: msi-controller@17a40000 { 5083 compatible = "arm,gic-v3-its"; 5084 reg = <0 0x17a40000 0 0x20000>; 5085 msi-controller; 5086 #msi-cells = <1>; 5087 }; 5088 }; 5089 5090 watchdog@17c10000 { 5091 compatible = "qcom,apss-wdt-sc8280xp", "qcom,kpss-wdt"; 5092 reg = <0 0x17c10000 0 0x1000>; 5093 clocks = <&sleep_clk>; 5094 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5095 }; 5096 5097 timer@17c20000 { 5098 compatible = "arm,armv7-timer-mem"; 5099 reg = <0x0 0x17c20000 0x0 0x1000>; 5100 #address-cells = <1>; 5101 #size-cells = <1>; 5102 ranges = <0x0 0x0 0x0 0x20000000>; 5103 5104 frame@17c21000 { 5105 frame-number = <0>; 5106 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5107 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5108 reg = <0x17c21000 0x1000>, 5109 <0x17c22000 0x1000>; 5110 }; 5111 5112 frame@17c23000 { 5113 frame-number = <1>; 5114 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5115 reg = <0x17c23000 0x1000>; 5116 status = "disabled"; 5117 }; 5118 5119 frame@17c25000 { 5120 frame-number = <2>; 5121 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5122 reg = <0x17c25000 0x1000>; 5123 status = "disabled"; 5124 }; 5125 5126 frame@17c27000 { 5127 frame-number = <3>; 5128 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5129 reg = <0x17c26000 0x1000>; 5130 status = "disabled"; 5131 }; 5132 5133 frame@17c29000 { 5134 frame-number = <4>; 5135 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5136 reg = <0x17c29000 0x1000>; 5137 status = "disabled"; 5138 }; 5139 5140 frame@17c2b000 { 5141 frame-number = <5>; 5142 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5143 reg = <0x17c2b000 0x1000>; 5144 status = "disabled"; 5145 }; 5146 5147 frame@17c2d000 { 5148 frame-number = <6>; 5149 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5150 reg = <0x17c2d000 0x1000>; 5151 status = "disabled"; 5152 }; 5153 }; 5154 5155 apps_rsc: rsc@18200000 { 5156 compatible = "qcom,rpmh-rsc"; 5157 reg = <0x0 0x18200000 0x0 0x10000>, 5158 <0x0 0x18210000 0x0 0x10000>, 5159 <0x0 0x18220000 0x0 0x10000>; 5160 reg-names = "drv-0", "drv-1", "drv-2"; 5161 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5162 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5163 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5164 qcom,tcs-offset = <0xd00>; 5165 qcom,drv-id = <2>; 5166 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 5167 <WAKE_TCS 3>, <CONTROL_TCS 1>; 5168 label = "apps_rsc"; 5169 power-domains = <&cluster_pd>; 5170 5171 apps_bcm_voter: bcm-voter { 5172 compatible = "qcom,bcm-voter"; 5173 }; 5174 5175 rpmhcc: clock-controller { 5176 compatible = "qcom,sc8280xp-rpmh-clk"; 5177 #clock-cells = <1>; 5178 clock-names = "xo"; 5179 clocks = <&xo_board_clk>; 5180 }; 5181 5182 rpmhpd: power-controller { 5183 compatible = "qcom,sc8280xp-rpmhpd"; 5184 #power-domain-cells = <1>; 5185 operating-points-v2 = <&rpmhpd_opp_table>; 5186 5187 rpmhpd_opp_table: opp-table { 5188 compatible = "operating-points-v2"; 5189 5190 rpmhpd_opp_ret: opp1 { 5191 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5192 }; 5193 5194 rpmhpd_opp_min_svs: opp2 { 5195 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5196 }; 5197 5198 rpmhpd_opp_low_svs: opp3 { 5199 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5200 }; 5201 5202 rpmhpd_opp_svs: opp4 { 5203 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5204 }; 5205 5206 rpmhpd_opp_svs_l1: opp5 { 5207 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5208 }; 5209 5210 rpmhpd_opp_nom: opp6 { 5211 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5212 }; 5213 5214 rpmhpd_opp_nom_l1: opp7 { 5215 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5216 }; 5217 5218 rpmhpd_opp_nom_l2: opp8 { 5219 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5220 }; 5221 5222 rpmhpd_opp_turbo: opp9 { 5223 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5224 }; 5225 5226 rpmhpd_opp_turbo_l1: opp10 { 5227 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5228 }; 5229 }; 5230 }; 5231 }; 5232 5233 epss_l3: interconnect@18590000 { 5234 compatible = "qcom,sc8280xp-epss-l3", "qcom,epss-l3"; 5235 reg = <0 0x18590000 0 0x1000>; 5236 5237 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5238 clock-names = "xo", "alternate"; 5239 5240 #interconnect-cells = <1>; 5241 }; 5242 5243 cpufreq_hw: cpufreq@18591000 { 5244 compatible = "qcom,sc8280xp-cpufreq-epss", "qcom,cpufreq-epss"; 5245 reg = <0 0x18591000 0 0x1000>, 5246 <0 0x18592000 0 0x1000>; 5247 reg-names = "freq-domain0", "freq-domain1"; 5248 5249 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 5250 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 5251 interrupt-names = "dcvsh-irq-0", 5252 "dcvsh-irq-1"; 5253 5254 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 5255 clock-names = "xo", "alternate"; 5256 5257 #freq-domain-cells = <1>; 5258 #clock-cells = <1>; 5259 }; 5260 5261 remoteproc_nsp0: remoteproc@1b300000 { 5262 compatible = "qcom,sc8280xp-nsp0-pas"; 5263 reg = <0 0x1b300000 0 0x10000>; 5264 5265 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5266 <&smp2p_nsp0_in 0 IRQ_TYPE_EDGE_RISING>, 5267 <&smp2p_nsp0_in 1 IRQ_TYPE_EDGE_RISING>, 5268 <&smp2p_nsp0_in 2 IRQ_TYPE_EDGE_RISING>, 5269 <&smp2p_nsp0_in 3 IRQ_TYPE_EDGE_RISING>; 5270 interrupt-names = "wdog", "fatal", "ready", 5271 "handover", "stop-ack"; 5272 5273 clocks = <&rpmhcc RPMH_CXO_CLK>; 5274 clock-names = "xo"; 5275 5276 power-domains = <&rpmhpd SC8280XP_NSP>; 5277 power-domain-names = "nsp"; 5278 5279 memory-region = <&pil_nsp0_mem>; 5280 5281 qcom,smem-states = <&smp2p_nsp0_out 0>; 5282 qcom,smem-state-names = "stop"; 5283 5284 interconnects = <&nspa_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 5285 5286 status = "disabled"; 5287 5288 glink-edge { 5289 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 5290 IPCC_MPROC_SIGNAL_GLINK_QMP 5291 IRQ_TYPE_EDGE_RISING>; 5292 mboxes = <&ipcc IPCC_CLIENT_CDSP 5293 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5294 5295 label = "nsp0"; 5296 qcom,remote-pid = <5>; 5297 5298 fastrpc { 5299 compatible = "qcom,fastrpc"; 5300 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5301 label = "cdsp"; 5302 #address-cells = <1>; 5303 #size-cells = <0>; 5304 5305 compute-cb@1 { 5306 compatible = "qcom,fastrpc-compute-cb"; 5307 reg = <1>; 5308 iommus = <&apps_smmu 0x3181 0x0420>; 5309 }; 5310 5311 compute-cb@2 { 5312 compatible = "qcom,fastrpc-compute-cb"; 5313 reg = <2>; 5314 iommus = <&apps_smmu 0x3182 0x0420>; 5315 }; 5316 5317 compute-cb@3 { 5318 compatible = "qcom,fastrpc-compute-cb"; 5319 reg = <3>; 5320 iommus = <&apps_smmu 0x3183 0x0420>; 5321 }; 5322 5323 compute-cb@4 { 5324 compatible = "qcom,fastrpc-compute-cb"; 5325 reg = <4>; 5326 iommus = <&apps_smmu 0x3184 0x0420>; 5327 }; 5328 5329 compute-cb@5 { 5330 compatible = "qcom,fastrpc-compute-cb"; 5331 reg = <5>; 5332 iommus = <&apps_smmu 0x3185 0x0420>; 5333 }; 5334 5335 compute-cb@6 { 5336 compatible = "qcom,fastrpc-compute-cb"; 5337 reg = <6>; 5338 iommus = <&apps_smmu 0x3186 0x0420>; 5339 }; 5340 5341 compute-cb@7 { 5342 compatible = "qcom,fastrpc-compute-cb"; 5343 reg = <7>; 5344 iommus = <&apps_smmu 0x3187 0x0420>; 5345 }; 5346 5347 compute-cb@8 { 5348 compatible = "qcom,fastrpc-compute-cb"; 5349 reg = <8>; 5350 iommus = <&apps_smmu 0x3188 0x0420>; 5351 }; 5352 5353 compute-cb@9 { 5354 compatible = "qcom,fastrpc-compute-cb"; 5355 reg = <9>; 5356 iommus = <&apps_smmu 0x318b 0x0420>; 5357 }; 5358 5359 compute-cb@10 { 5360 compatible = "qcom,fastrpc-compute-cb"; 5361 reg = <10>; 5362 iommus = <&apps_smmu 0x318b 0x0420>; 5363 }; 5364 5365 compute-cb@11 { 5366 compatible = "qcom,fastrpc-compute-cb"; 5367 reg = <11>; 5368 iommus = <&apps_smmu 0x318c 0x0420>; 5369 }; 5370 5371 compute-cb@12 { 5372 compatible = "qcom,fastrpc-compute-cb"; 5373 reg = <12>; 5374 iommus = <&apps_smmu 0x318d 0x0420>; 5375 }; 5376 5377 compute-cb@13 { 5378 compatible = "qcom,fastrpc-compute-cb"; 5379 reg = <13>; 5380 iommus = <&apps_smmu 0x318e 0x0420>; 5381 }; 5382 5383 compute-cb@14 { 5384 compatible = "qcom,fastrpc-compute-cb"; 5385 reg = <14>; 5386 iommus = <&apps_smmu 0x318f 0x0420>; 5387 }; 5388 }; 5389 }; 5390 }; 5391 5392 remoteproc_nsp1: remoteproc@21300000 { 5393 compatible = "qcom,sc8280xp-nsp1-pas"; 5394 reg = <0 0x21300000 0 0x10000>; 5395 5396 interrupts-extended = <&intc GIC_SPI 887 IRQ_TYPE_EDGE_RISING>, 5397 <&smp2p_nsp1_in 0 IRQ_TYPE_EDGE_RISING>, 5398 <&smp2p_nsp1_in 1 IRQ_TYPE_EDGE_RISING>, 5399 <&smp2p_nsp1_in 2 IRQ_TYPE_EDGE_RISING>, 5400 <&smp2p_nsp1_in 3 IRQ_TYPE_EDGE_RISING>; 5401 interrupt-names = "wdog", "fatal", "ready", 5402 "handover", "stop-ack"; 5403 5404 clocks = <&rpmhcc RPMH_CXO_CLK>; 5405 clock-names = "xo"; 5406 5407 power-domains = <&rpmhpd SC8280XP_NSP>; 5408 power-domain-names = "nsp"; 5409 5410 memory-region = <&pil_nsp1_mem>; 5411 5412 qcom,smem-states = <&smp2p_nsp1_out 0>; 5413 qcom,smem-state-names = "stop"; 5414 5415 interconnects = <&nspb_noc MASTER_CDSP_PROC_B 0 &mc_virt SLAVE_EBI1 0>; 5416 5417 status = "disabled"; 5418 5419 glink-edge { 5420 interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 5421 IPCC_MPROC_SIGNAL_GLINK_QMP 5422 IRQ_TYPE_EDGE_RISING>; 5423 mboxes = <&ipcc IPCC_CLIENT_NSP1 5424 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5425 5426 label = "nsp1"; 5427 qcom,remote-pid = <12>; 5428 }; 5429 }; 5430 5431 mdss1: display-subsystem@22000000 { 5432 compatible = "qcom,sc8280xp-mdss"; 5433 reg = <0 0x22000000 0 0x1000>; 5434 reg-names = "mdss"; 5435 5436 clocks = <&gcc GCC_DISP_AHB_CLK>, 5437 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5438 <&dispcc1 DISP_CC_MDSS_MDP_CLK>; 5439 clock-names = "iface", 5440 "ahb", 5441 "core"; 5442 interconnects = <&mmss_noc MASTER_MDP_CORE1_0 0 &mc_virt SLAVE_EBI1 0>, 5443 <&mmss_noc MASTER_MDP_CORE1_1 0 &mc_virt SLAVE_EBI1 0>; 5444 interconnect-names = "mdp0-mem", "mdp1-mem"; 5445 interrupts = <GIC_SPI 865 IRQ_TYPE_LEVEL_HIGH>; 5446 5447 iommus = <&apps_smmu 0x1800 0x402>; 5448 power-domains = <&dispcc1 MDSS_GDSC>; 5449 resets = <&dispcc1 DISP_CC_MDSS_CORE_BCR>; 5450 5451 interrupt-controller; 5452 #interrupt-cells = <1>; 5453 #address-cells = <2>; 5454 #size-cells = <2>; 5455 ranges; 5456 5457 status = "disabled"; 5458 5459 mdss1_mdp: display-controller@22001000 { 5460 compatible = "qcom,sc8280xp-dpu"; 5461 reg = <0 0x22001000 0 0x8f000>, 5462 <0 0x220b0000 0 0x2008>; 5463 reg-names = "mdp", "vbif"; 5464 5465 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5466 <&gcc GCC_DISP_SF_AXI_CLK>, 5467 <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5468 <&dispcc1 DISP_CC_MDSS_MDP_LUT_CLK>, 5469 <&dispcc1 DISP_CC_MDSS_MDP_CLK>, 5470 <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5471 clock-names = "bus", 5472 "nrt_bus", 5473 "iface", 5474 "lut", 5475 "core", 5476 "vsync"; 5477 interrupt-parent = <&mdss1>; 5478 interrupts = <0>; 5479 power-domains = <&rpmhpd SC8280XP_MMCX>; 5480 5481 assigned-clocks = <&dispcc1 DISP_CC_MDSS_VSYNC_CLK>; 5482 assigned-clock-rates = <19200000>; 5483 operating-points-v2 = <&mdss1_mdp_opp_table>; 5484 5485 ports { 5486 #address-cells = <1>; 5487 #size-cells = <0>; 5488 5489 port@0 { 5490 reg = <0>; 5491 mdss1_intf0_out: endpoint { 5492 remote-endpoint = <&mdss1_dp0_in>; 5493 }; 5494 }; 5495 5496 port@4 { 5497 reg = <4>; 5498 mdss1_intf4_out: endpoint { 5499 remote-endpoint = <&mdss1_dp1_in>; 5500 }; 5501 }; 5502 5503 port@5 { 5504 reg = <5>; 5505 mdss1_intf5_out: endpoint { 5506 remote-endpoint = <&mdss1_dp3_in>; 5507 }; 5508 }; 5509 5510 port@6 { 5511 reg = <6>; 5512 mdss1_intf6_out: endpoint { 5513 remote-endpoint = <&mdss1_dp2_in>; 5514 }; 5515 }; 5516 }; 5517 5518 mdss1_mdp_opp_table: opp-table { 5519 compatible = "operating-points-v2"; 5520 5521 opp-200000000 { 5522 opp-hz = /bits/ 64 <200000000>; 5523 required-opps = <&rpmhpd_opp_low_svs>; 5524 }; 5525 5526 opp-300000000 { 5527 opp-hz = /bits/ 64 <300000000>; 5528 required-opps = <&rpmhpd_opp_svs>; 5529 }; 5530 5531 opp-375000000 { 5532 opp-hz = /bits/ 64 <375000000>; 5533 required-opps = <&rpmhpd_opp_svs_l1>; 5534 }; 5535 5536 opp-500000000 { 5537 opp-hz = /bits/ 64 <500000000>; 5538 required-opps = <&rpmhpd_opp_nom>; 5539 }; 5540 opp-600000000 { 5541 opp-hz = /bits/ 64 <600000000>; 5542 required-opps = <&rpmhpd_opp_turbo_l1>; 5543 }; 5544 }; 5545 }; 5546 5547 mdss1_dp0: displayport-controller@22090000 { 5548 compatible = "qcom,sc8280xp-dp"; 5549 reg = <0 0x22090000 0 0x200>, 5550 <0 0x22090200 0 0x200>, 5551 <0 0x22090400 0 0x600>, 5552 <0 0x22091000 0 0x400>, 5553 <0 0x22091400 0 0x400>; 5554 5555 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5556 <&dispcc1 DISP_CC_MDSS_DPTX0_AUX_CLK>, 5557 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK>, 5558 <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, 5559 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 5560 clock-names = "core_iface", "core_aux", 5561 "ctrl_link", 5562 "ctrl_link_iface", "stream_pixel"; 5563 interrupt-parent = <&mdss1>; 5564 interrupts = <12>; 5565 phys = <&mdss1_dp0_phy>; 5566 phy-names = "dp"; 5567 power-domains = <&rpmhpd SC8280XP_MMCX>; 5568 5569 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, 5570 <&dispcc1 DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; 5571 assigned-clock-parents = <&mdss1_dp0_phy 0>, <&mdss1_dp0_phy 1>; 5572 operating-points-v2 = <&mdss1_dp0_opp_table>; 5573 5574 #sound-dai-cells = <0>; 5575 5576 status = "disabled"; 5577 5578 ports { 5579 #address-cells = <1>; 5580 #size-cells = <0>; 5581 5582 port@0 { 5583 reg = <0>; 5584 mdss1_dp0_in: endpoint { 5585 remote-endpoint = <&mdss1_intf0_out>; 5586 }; 5587 }; 5588 5589 port@1 { 5590 reg = <1>; 5591 }; 5592 }; 5593 5594 mdss1_dp0_opp_table: opp-table { 5595 compatible = "operating-points-v2"; 5596 5597 opp-160000000 { 5598 opp-hz = /bits/ 64 <160000000>; 5599 required-opps = <&rpmhpd_opp_low_svs>; 5600 }; 5601 5602 opp-270000000 { 5603 opp-hz = /bits/ 64 <270000000>; 5604 required-opps = <&rpmhpd_opp_svs>; 5605 }; 5606 5607 opp-540000000 { 5608 opp-hz = /bits/ 64 <540000000>; 5609 required-opps = <&rpmhpd_opp_svs_l1>; 5610 }; 5611 5612 opp-810000000 { 5613 opp-hz = /bits/ 64 <810000000>; 5614 required-opps = <&rpmhpd_opp_nom>; 5615 }; 5616 }; 5617 }; 5618 5619 mdss1_dp1: displayport-controller@22098000 { 5620 compatible = "qcom,sc8280xp-dp"; 5621 reg = <0 0x22098000 0 0x200>, 5622 <0 0x22098200 0 0x200>, 5623 <0 0x22098400 0 0x600>, 5624 <0 0x22099000 0 0x400>, 5625 <0 0x22099400 0 0x400>; 5626 5627 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5628 <&dispcc1 DISP_CC_MDSS_DPTX1_AUX_CLK>, 5629 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK>, 5630 <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>, 5631 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK>; 5632 clock-names = "core_iface", "core_aux", 5633 "ctrl_link", 5634 "ctrl_link_iface", "stream_pixel"; 5635 interrupt-parent = <&mdss1>; 5636 interrupts = <13>; 5637 phys = <&mdss1_dp1_phy>; 5638 phy-names = "dp"; 5639 power-domains = <&rpmhpd SC8280XP_MMCX>; 5640 5641 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>, 5642 <&dispcc1 DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>; 5643 assigned-clock-parents = <&mdss1_dp1_phy 0>, <&mdss1_dp1_phy 1>; 5644 operating-points-v2 = <&mdss1_dp1_opp_table>; 5645 5646 #sound-dai-cells = <0>; 5647 5648 status = "disabled"; 5649 5650 ports { 5651 #address-cells = <1>; 5652 #size-cells = <0>; 5653 5654 port@0 { 5655 reg = <0>; 5656 mdss1_dp1_in: endpoint { 5657 remote-endpoint = <&mdss1_intf4_out>; 5658 }; 5659 }; 5660 5661 port@1 { 5662 reg = <1>; 5663 }; 5664 }; 5665 5666 mdss1_dp1_opp_table: opp-table { 5667 compatible = "operating-points-v2"; 5668 5669 opp-160000000 { 5670 opp-hz = /bits/ 64 <160000000>; 5671 required-opps = <&rpmhpd_opp_low_svs>; 5672 }; 5673 5674 opp-270000000 { 5675 opp-hz = /bits/ 64 <270000000>; 5676 required-opps = <&rpmhpd_opp_svs>; 5677 }; 5678 5679 opp-540000000 { 5680 opp-hz = /bits/ 64 <540000000>; 5681 required-opps = <&rpmhpd_opp_svs_l1>; 5682 }; 5683 5684 opp-810000000 { 5685 opp-hz = /bits/ 64 <810000000>; 5686 required-opps = <&rpmhpd_opp_nom>; 5687 }; 5688 }; 5689 }; 5690 5691 mdss1_dp2: displayport-controller@2209a000 { 5692 compatible = "qcom,sc8280xp-dp"; 5693 reg = <0 0x2209a000 0 0x200>, 5694 <0 0x2209a200 0 0x200>, 5695 <0 0x2209a400 0 0x600>, 5696 <0 0x2209b000 0 0x400>, 5697 <0 0x2209b400 0 0x400>; 5698 5699 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5700 <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5701 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK>, 5702 <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>, 5703 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK>; 5704 clock-names = "core_iface", "core_aux", 5705 "ctrl_link", 5706 "ctrl_link_iface", "stream_pixel"; 5707 interrupt-parent = <&mdss1>; 5708 interrupts = <14>; 5709 phys = <&mdss1_dp2_phy>; 5710 phy-names = "dp"; 5711 power-domains = <&rpmhpd SC8280XP_MMCX>; 5712 5713 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>, 5714 <&dispcc1 DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>; 5715 assigned-clock-parents = <&mdss1_dp2_phy 0>, <&mdss1_dp2_phy 1>; 5716 operating-points-v2 = <&mdss1_dp2_opp_table>; 5717 5718 #sound-dai-cells = <0>; 5719 5720 status = "disabled"; 5721 5722 ports { 5723 #address-cells = <1>; 5724 #size-cells = <0>; 5725 5726 port@0 { 5727 reg = <0>; 5728 mdss1_dp2_in: endpoint { 5729 remote-endpoint = <&mdss1_intf6_out>; 5730 }; 5731 }; 5732 5733 port@1 { 5734 reg = <1>; 5735 }; 5736 }; 5737 5738 mdss1_dp2_opp_table: opp-table { 5739 compatible = "operating-points-v2"; 5740 5741 opp-160000000 { 5742 opp-hz = /bits/ 64 <160000000>; 5743 required-opps = <&rpmhpd_opp_low_svs>; 5744 }; 5745 5746 opp-270000000 { 5747 opp-hz = /bits/ 64 <270000000>; 5748 required-opps = <&rpmhpd_opp_svs>; 5749 }; 5750 5751 opp-540000000 { 5752 opp-hz = /bits/ 64 <540000000>; 5753 required-opps = <&rpmhpd_opp_svs_l1>; 5754 }; 5755 5756 opp-810000000 { 5757 opp-hz = /bits/ 64 <810000000>; 5758 required-opps = <&rpmhpd_opp_nom>; 5759 }; 5760 }; 5761 }; 5762 5763 mdss1_dp3: displayport-controller@220a0000 { 5764 compatible = "qcom,sc8280xp-dp"; 5765 reg = <0 0x220a0000 0 0x200>, 5766 <0 0x220a0200 0 0x200>, 5767 <0 0x220a0400 0 0x600>, 5768 <0 0x220a1000 0 0x400>, 5769 <0 0x220a1400 0 0x400>; 5770 5771 clocks = <&dispcc1 DISP_CC_MDSS_AHB_CLK>, 5772 <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5773 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK>, 5774 <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>, 5775 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK>; 5776 clock-names = "core_iface", "core_aux", 5777 "ctrl_link", 5778 "ctrl_link_iface", "stream_pixel"; 5779 interrupt-parent = <&mdss1>; 5780 interrupts = <15>; 5781 phys = <&mdss1_dp3_phy>; 5782 phy-names = "dp"; 5783 power-domains = <&rpmhpd SC8280XP_MMCX>; 5784 5785 assigned-clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>, 5786 <&dispcc1 DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>; 5787 assigned-clock-parents = <&mdss1_dp3_phy 0>, <&mdss1_dp3_phy 1>; 5788 operating-points-v2 = <&mdss1_dp3_opp_table>; 5789 5790 #sound-dai-cells = <0>; 5791 5792 status = "disabled"; 5793 5794 ports { 5795 #address-cells = <1>; 5796 #size-cells = <0>; 5797 5798 port@0 { 5799 reg = <0>; 5800 mdss1_dp3_in: endpoint { 5801 remote-endpoint = <&mdss1_intf5_out>; 5802 }; 5803 }; 5804 5805 port@1 { 5806 reg = <1>; 5807 }; 5808 }; 5809 5810 mdss1_dp3_opp_table: opp-table { 5811 compatible = "operating-points-v2"; 5812 5813 opp-160000000 { 5814 opp-hz = /bits/ 64 <160000000>; 5815 required-opps = <&rpmhpd_opp_low_svs>; 5816 }; 5817 5818 opp-270000000 { 5819 opp-hz = /bits/ 64 <270000000>; 5820 required-opps = <&rpmhpd_opp_svs>; 5821 }; 5822 5823 opp-540000000 { 5824 opp-hz = /bits/ 64 <540000000>; 5825 required-opps = <&rpmhpd_opp_svs_l1>; 5826 }; 5827 5828 opp-810000000 { 5829 opp-hz = /bits/ 64 <810000000>; 5830 required-opps = <&rpmhpd_opp_nom>; 5831 }; 5832 }; 5833 }; 5834 }; 5835 5836 mdss1_dp2_phy: phy@220c2a00 { 5837 compatible = "qcom,sc8280xp-dp-phy"; 5838 reg = <0 0x220c2a00 0 0x19c>, 5839 <0 0x220c2200 0 0xec>, 5840 <0 0x220c2600 0 0xec>, 5841 <0 0x220c2000 0 0x1c8>; 5842 5843 clocks = <&dispcc1 DISP_CC_MDSS_DPTX2_AUX_CLK>, 5844 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5845 clock-names = "aux", "cfg_ahb"; 5846 power-domains = <&rpmhpd SC8280XP_MX>; 5847 5848 #clock-cells = <1>; 5849 #phy-cells = <0>; 5850 5851 status = "disabled"; 5852 }; 5853 5854 mdss1_dp3_phy: phy@220c5a00 { 5855 compatible = "qcom,sc8280xp-dp-phy"; 5856 reg = <0 0x220c5a00 0 0x19c>, 5857 <0 0x220c5200 0 0xec>, 5858 <0 0x220c5600 0 0xec>, 5859 <0 0x220c5000 0 0x1c8>; 5860 5861 clocks = <&dispcc1 DISP_CC_MDSS_DPTX3_AUX_CLK>, 5862 <&dispcc1 DISP_CC_MDSS_AHB_CLK>; 5863 clock-names = "aux", "cfg_ahb"; 5864 power-domains = <&rpmhpd SC8280XP_MX>; 5865 5866 #clock-cells = <1>; 5867 #phy-cells = <0>; 5868 5869 status = "disabled"; 5870 }; 5871 5872 dispcc1: clock-controller@22100000 { 5873 compatible = "qcom,sc8280xp-dispcc1"; 5874 reg = <0 0x22100000 0 0x20000>; 5875 5876 clocks = <&gcc GCC_DISP_AHB_CLK>, 5877 <&rpmhcc RPMH_CXO_CLK>, 5878 <0>, 5879 <&mdss1_dp0_phy 0>, 5880 <&mdss1_dp0_phy 1>, 5881 <&mdss1_dp1_phy 0>, 5882 <&mdss1_dp1_phy 1>, 5883 <&mdss1_dp2_phy 0>, 5884 <&mdss1_dp2_phy 1>, 5885 <&mdss1_dp3_phy 0>, 5886 <&mdss1_dp3_phy 1>, 5887 <0>, 5888 <0>, 5889 <0>, 5890 <0>; 5891 power-domains = <&rpmhpd SC8280XP_MMCX>; 5892 5893 #clock-cells = <1>; 5894 #power-domain-cells = <1>; 5895 #reset-cells = <1>; 5896 5897 status = "disabled"; 5898 }; 5899 5900 ethernet1: ethernet@23000000 { 5901 compatible = "qcom,sc8280xp-ethqos"; 5902 reg = <0x0 0x23000000 0x0 0x10000>, 5903 <0x0 0x23016000 0x0 0x100>; 5904 reg-names = "stmmaceth", "rgmii"; 5905 5906 clocks = <&gcc GCC_EMAC1_AXI_CLK>, 5907 <&gcc GCC_EMAC1_SLV_AHB_CLK>, 5908 <&gcc GCC_EMAC1_PTP_CLK>, 5909 <&gcc GCC_EMAC1_RGMII_CLK>; 5910 clock-names = "stmmaceth", 5911 "pclk", 5912 "ptp_ref", 5913 "rgmii"; 5914 5915 interrupts = <GIC_SPI 929 IRQ_TYPE_LEVEL_HIGH>, 5916 <GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>; 5917 interrupt-names = "macirq", "eth_lpi"; 5918 5919 iommus = <&apps_smmu 0x40 0xf>; 5920 power-domains = <&gcc EMAC_1_GDSC>; 5921 5922 snps,tso; 5923 snps,pbl = <32>; 5924 rx-fifo-depth = <4096>; 5925 tx-fifo-depth = <4096>; 5926 5927 status = "disabled"; 5928 }; 5929 }; 5930 5931 sound: sound { 5932 }; 5933 5934 thermal-zones { 5935 cpu0-thermal { 5936 polling-delay-passive = <250>; 5937 5938 thermal-sensors = <&tsens0 1>; 5939 5940 trips { 5941 cpu-crit { 5942 temperature = <110000>; 5943 hysteresis = <1000>; 5944 type = "critical"; 5945 }; 5946 }; 5947 }; 5948 5949 cpu1-thermal { 5950 polling-delay-passive = <250>; 5951 5952 thermal-sensors = <&tsens0 2>; 5953 5954 trips { 5955 cpu-crit { 5956 temperature = <110000>; 5957 hysteresis = <1000>; 5958 type = "critical"; 5959 }; 5960 }; 5961 }; 5962 5963 cpu2-thermal { 5964 polling-delay-passive = <250>; 5965 5966 thermal-sensors = <&tsens0 3>; 5967 5968 trips { 5969 cpu-crit { 5970 temperature = <110000>; 5971 hysteresis = <1000>; 5972 type = "critical"; 5973 }; 5974 }; 5975 }; 5976 5977 cpu3-thermal { 5978 polling-delay-passive = <250>; 5979 5980 thermal-sensors = <&tsens0 4>; 5981 5982 trips { 5983 cpu-crit { 5984 temperature = <110000>; 5985 hysteresis = <1000>; 5986 type = "critical"; 5987 }; 5988 }; 5989 }; 5990 5991 cpu4-thermal { 5992 polling-delay-passive = <250>; 5993 5994 thermal-sensors = <&tsens0 5>; 5995 5996 trips { 5997 cpu-crit { 5998 temperature = <110000>; 5999 hysteresis = <1000>; 6000 type = "critical"; 6001 }; 6002 }; 6003 }; 6004 6005 cpu5-thermal { 6006 polling-delay-passive = <250>; 6007 6008 thermal-sensors = <&tsens0 6>; 6009 6010 trips { 6011 cpu-crit { 6012 temperature = <110000>; 6013 hysteresis = <1000>; 6014 type = "critical"; 6015 }; 6016 }; 6017 }; 6018 6019 cpu6-thermal { 6020 polling-delay-passive = <250>; 6021 6022 thermal-sensors = <&tsens0 7>; 6023 6024 trips { 6025 cpu-crit { 6026 temperature = <110000>; 6027 hysteresis = <1000>; 6028 type = "critical"; 6029 }; 6030 }; 6031 }; 6032 6033 cpu7-thermal { 6034 polling-delay-passive = <250>; 6035 6036 thermal-sensors = <&tsens0 8>; 6037 6038 trips { 6039 cpu-crit { 6040 temperature = <110000>; 6041 hysteresis = <1000>; 6042 type = "critical"; 6043 }; 6044 }; 6045 }; 6046 6047 cluster0-thermal { 6048 polling-delay-passive = <250>; 6049 6050 thermal-sensors = <&tsens0 9>; 6051 6052 trips { 6053 cpu-crit { 6054 temperature = <110000>; 6055 hysteresis = <1000>; 6056 type = "critical"; 6057 }; 6058 }; 6059 }; 6060 6061 gpu-thermal { 6062 polling-delay-passive = <250>; 6063 6064 thermal-sensors = <&tsens2 2>; 6065 6066 cooling-maps { 6067 map0 { 6068 trip = <&gpu_alert0>; 6069 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 6070 }; 6071 }; 6072 6073 trips { 6074 gpu_alert0: trip-point0 { 6075 temperature = <85000>; 6076 hysteresis = <1000>; 6077 type = "passive"; 6078 }; 6079 6080 trip-point1 { 6081 temperature = <110000>; 6082 hysteresis = <1000>; 6083 type = "critical"; 6084 }; 6085 }; 6086 }; 6087 6088 mem-thermal { 6089 polling-delay-passive = <250>; 6090 6091 thermal-sensors = <&tsens1 15>; 6092 6093 trips { 6094 trip-point0 { 6095 temperature = <90000>; 6096 hysteresis = <2000>; 6097 type = "hot"; 6098 }; 6099 }; 6100 }; 6101 }; 6102 6103 timer { 6104 compatible = "arm,armv8-timer"; 6105 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6106 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6107 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6108 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6109 }; 6110}; 6111