1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qdu1000-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/dma/qcom-gpi.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/interconnect/qcom,icc.h> 11#include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen: chosen { }; 23 24 clocks { 25 xo_board: xo-board-clk { 26 compatible = "fixed-clock"; 27 clock-frequency = <19200000>; 28 #clock-cells = <0>; 29 }; 30 31 sleep_clk: sleep-clk { 32 compatible = "fixed-clock"; 33 clock-frequency = <32764>; 34 #clock-cells = <0>; 35 }; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a55"; 45 reg = <0x0 0x0>; 46 clocks = <&cpufreq_hw 0>; 47 enable-method = "psci"; 48 power-domains = <&cpu_pd0>; 49 power-domain-names = "psci"; 50 qcom,freq-domains = <&cpufreq_hw 0>; 51 next-level-cache = <&l2_0>; 52 l2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 next-level-cache = <&l3_0>; 57 l3_0: l3-cache { 58 compatible = "cache"; 59 cache-level = <3>; 60 cache-unified; 61 }; 62 }; 63 }; 64 65 cpu1: cpu@100 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a55"; 68 reg = <0x0 0x100>; 69 clocks = <&cpufreq_hw 0>; 70 enable-method = "psci"; 71 power-domains = <&cpu_pd1>; 72 power-domain-names = "psci"; 73 qcom,freq-domains = <&cpufreq_hw 0>; 74 next-level-cache = <&l2_100>; 75 l2_100: l2-cache { 76 compatible = "cache"; 77 cache-level = <2>; 78 cache-unified; 79 next-level-cache = <&l3_0>; 80 }; 81 }; 82 83 cpu2: cpu@200 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a55"; 86 reg = <0x0 0x200>; 87 clocks = <&cpufreq_hw 0>; 88 enable-method = "psci"; 89 power-domains = <&cpu_pd2>; 90 power-domain-names = "psci"; 91 qcom,freq-domains = <&cpufreq_hw 0>; 92 next-level-cache = <&l2_200>; 93 l2_200: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&l3_0>; 98 }; 99 }; 100 101 cpu3: cpu@300 { 102 device_type = "cpu"; 103 compatible = "arm,cortex-a55"; 104 reg = <0x0 0x300>; 105 clocks = <&cpufreq_hw 0>; 106 enable-method = "psci"; 107 power-domains = <&cpu_pd3>; 108 power-domain-names = "psci"; 109 qcom,freq-domains = <&cpufreq_hw 0>; 110 next-level-cache = <&l2_300>; 111 l2_300: l2-cache { 112 compatible = "cache"; 113 cache-level = <2>; 114 cache-unified; 115 next-level-cache = <&l3_0>; 116 }; 117 }; 118 119 cpu-map { 120 cluster0 { 121 core0 { 122 cpu = <&cpu0>; 123 }; 124 125 core1 { 126 cpu = <&cpu1>; 127 }; 128 129 core2 { 130 cpu = <&cpu2>; 131 }; 132 133 core3 { 134 cpu = <&cpu3>; 135 }; 136 }; 137 }; 138 }; 139 140 idle-states { 141 entry-method = "psci"; 142 143 cpu_off: cpu-sleep-0 { 144 compatible = "arm,idle-state"; 145 entry-latency-us = <274>; 146 exit-latency-us = <480>; 147 min-residency-us = <3934>; 148 arm,psci-suspend-param = <0x40000004>; 149 local-timer-stop; 150 }; 151 }; 152 153 domain-idle-states { 154 cluster_sleep_0: cluster-sleep-0 { 155 compatible = "domain-idle-state"; 156 entry-latency-us = <584>; 157 exit-latency-us = <2332>; 158 min-residency-us = <6118>; 159 arm,psci-suspend-param = <0x41000044>; 160 }; 161 162 cluster_sleep_1: cluster-sleep-1 { 163 compatible = "domain-idle-state"; 164 entry-latency-us = <2893>; 165 exit-latency-us = <4023>; 166 min-residency-us = <9987>; 167 arm,psci-suspend-param = <0x41003344>; 168 }; 169 }; 170 171 firmware { 172 scm { 173 compatible = "qcom,scm-qdu1000", "qcom,scm"; 174 }; 175 }; 176 177 mc_virt: interconnect-0 { 178 compatible = "qcom,qdu1000-mc-virt"; 179 qcom,bcm-voters = <&apps_bcm_voter>; 180 #interconnect-cells = <2>; 181 }; 182 183 clk_virt: interconnect-1 { 184 compatible = "qcom,qdu1000-clk-virt"; 185 qcom,bcm-voters = <&apps_bcm_voter>; 186 #interconnect-cells = <2>; 187 }; 188 189 memory@80000000 { 190 device_type = "memory"; 191 /* We expect the bootloader to fill in the size */ 192 reg = <0x0 0x80000000 0x0 0x0>; 193 }; 194 195 pmu { 196 compatible = "arm,cortex-a55-pmu"; 197 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 198 }; 199 200 psci { 201 compatible = "arm,psci-1.0"; 202 method = "smc"; 203 204 cpu_pd0: power-domain-cpu0 { 205 #power-domain-cells = <0>; 206 power-domains = <&cluster_pd>; 207 domain-idle-states = <&cpu_off>; 208 }; 209 210 cpu_pd1: power-domain-cpu1 { 211 #power-domain-cells = <0>; 212 power-domains = <&cluster_pd>; 213 domain-idle-states = <&cpu_off>; 214 }; 215 216 cpu_pd2: power-domain-cpu2 { 217 #power-domain-cells = <0>; 218 power-domains = <&cluster_pd>; 219 domain-idle-states = <&cpu_off>; 220 }; 221 222 cpu_pd3: power-domain-cpu3 { 223 #power-domain-cells = <0>; 224 power-domains = <&cluster_pd>; 225 domain-idle-states = <&cpu_off>; 226 }; 227 228 cluster_pd: power-domain-cluster { 229 #power-domain-cells = <0>; 230 domain-idle-states = <&cluster_sleep_0 &cluster_sleep_1>; 231 }; 232 }; 233 234 reserved_memory: reserved-memory { 235 #address-cells = <2>; 236 #size-cells = <2>; 237 ranges; 238 239 hyp_mem: hyp@80000000 { 240 reg = <0x0 0x80000000 0x0 0x600000>; 241 no-map; 242 }; 243 244 xbl_dt_log_mem: xbl-dt-log@80600000 { 245 reg = <0x0 0x80600000 0x0 0x40000>; 246 no-map; 247 }; 248 249 xbl_ramdump_mem: xbl-ramdump@80640000 { 250 reg = <0x0 0x80640000 0x0 0x1c0000>; 251 no-map; 252 }; 253 254 aop_image_mem: aop-image@80800000 { 255 reg = <0x0 0x80800000 0x0 0x60000>; 256 no-map; 257 }; 258 259 aop_cmd_db_mem: aop-cmd-db@80860000 { 260 compatible = "qcom,cmd-db"; 261 reg = <0x0 0x80860000 0x0 0x20000>; 262 no-map; 263 }; 264 265 aop_config_mem: aop-config@80880000 { 266 reg = <0x0 0x80880000 0x0 0x20000>; 267 no-map; 268 }; 269 270 tme_crash_dump_mem: tme-crash-dump@808a0000 { 271 reg = <0x0 0x808a0000 0x0 0x40000>; 272 no-map; 273 }; 274 275 tme_log_mem: tme-log@808e0000 { 276 reg = <0x0 0x808e0000 0x0 0x4000>; 277 no-map; 278 }; 279 280 uefi_log_mem: uefi-log@808e4000 { 281 reg = <0x0 0x808e4000 0x0 0x10000>; 282 no-map; 283 }; 284 285 smem_mem: smem@80900000 { 286 compatible = "qcom,smem"; 287 reg = <0x0 0x80900000 0x0 0x200000>; 288 no-map; 289 hwlocks = <&tcsr_mutex 3>; 290 }; 291 292 cpucp_fw_mem: cpucp-fw@80b00000 { 293 reg = <0x0 0x80b00000 0x0 0x100000>; 294 no-map; 295 }; 296 297 xbl_sc_mem: memory@80c00000 { 298 reg = <0x0 0x80c00000 0x0 0x40000>; 299 no-map; 300 }; 301 302 tz_stat_mem: tz-stat@81d00000 { 303 reg = <0x0 0x81d00000 0x0 0x100000>; 304 no-map; 305 }; 306 307 tags_mem: tags@81e00000 { 308 reg = <0x0 0x81e00000 0x0 0x500000>; 309 no-map; 310 }; 311 312 qtee_mem: qtee@82300000 { 313 reg = <0x0 0x82300000 0x0 0x500000>; 314 no-map; 315 }; 316 317 ta_mem: ta@82800000 { 318 reg = <0x0 0x82800000 0x0 0xa00000>; 319 no-map; 320 }; 321 322 fs1_mem: fs1@83200000 { 323 reg = <0x0 0x83200000 0x0 0x400000>; 324 no-map; 325 }; 326 327 fs2_mem: fs2@83600000 { 328 reg = <0x0 0x83600000 0x0 0x400000>; 329 no-map; 330 }; 331 332 fs3_mem: fs3@83a00000 { 333 reg = <0x0 0x83a00000 0x0 0x400000>; 334 no-map; 335 }; 336 337 /* Linux kernel image is loaded at 0x83e00000 */ 338 339 ipa_fw_mem: ipa-fw@8be00000 { 340 reg = <0x0 0x8be00000 0x0 0x10000>; 341 no-map; 342 }; 343 344 ipa_gsi_mem: ipa-gsi@8be10000 { 345 reg = <0x0 0x8be10000 0x0 0x14000>; 346 no-map; 347 }; 348 349 mpss_mem: mpss@8c000000 { 350 reg = <0x0 0x8c000000 0x0 0x12c00000>; 351 no-map; 352 }; 353 354 q6_mpss_dtb_mem: q6-mpss-dtb@9ec00000 { 355 reg = <0x0 0x9ec00000 0x0 0x80000>; 356 no-map; 357 }; 358 359 tenx_mem: tenx@a0000000 { 360 reg = <0x0 0xa0000000 0x0 0x19600000>; 361 no-map; 362 }; 363 364 oem_tenx_mem: oem-tenx@b9600000 { 365 reg = <0x0 0xb9600000 0x0 0x6a00000>; 366 no-map; 367 }; 368 369 tenx_q6_buffer_mem: tenx-q6-buffer@c0000000 { 370 reg = <0x0 0xc0000000 0x0 0x3200000>; 371 no-map; 372 }; 373 374 ipa_buffer_mem: ipa-buffer@c3200000 { 375 reg = <0x0 0xc3200000 0x0 0x12c00000>; 376 no-map; 377 }; 378 }; 379 380 soc: soc@0 { 381 compatible = "simple-bus"; 382 #address-cells = <2>; 383 #size-cells = <2>; 384 ranges = <0 0 0 0 0x10 0>; 385 dma-ranges = <0 0 0 0 0x10 0>; 386 387 gcc: clock-controller@80000 { 388 compatible = "qcom,qdu1000-gcc"; 389 reg = <0x0 0x80000 0x0 0x1f4200>; 390 clocks = <&rpmhcc RPMH_CXO_CLK>, 391 <&sleep_clk>, 392 <0>, 393 <0>, 394 <0>; 395 #clock-cells = <1>; 396 #reset-cells = <1>; 397 #power-domain-cells = <1>; 398 }; 399 400 ecpricc: clock-controller@280000 { 401 compatible = "qcom,qdu1000-ecpricc"; 402 reg = <0x0 0x00280000 0x0 0x31c00>; 403 clocks = <&rpmhcc RPMH_CXO_CLK>, 404 <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, 405 <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, 406 <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, 407 <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, 408 <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, 409 <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; 410 #clock-cells = <1>; 411 #reset-cells = <1>; 412 }; 413 414 gpi_dma0: dma-controller@900000 { 415 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; 416 reg = <0x0 0x900000 0x0 0x60000>; 417 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 428 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 429 dma-channels = <12>; 430 dma-channel-mask = <0x3f>; 431 iommus = <&apps_smmu 0xf6 0x0>; 432 #dma-cells = <3>; 433 }; 434 435 qupv3_id_0: geniqup@9c0000 { 436 compatible = "qcom,geni-se-qup"; 437 reg = <0x0 0x9c0000 0x0 0x2000>; 438 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 439 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 440 clock-names = "m-ahb", "s-ahb"; 441 iommus = <&apps_smmu 0xe3 0x0>; 442 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 443 &clk_virt SLAVE_QUP_CORE_0 0>; 444 interconnect-names = "qup-core"; 445 446 #address-cells = <2>; 447 #size-cells = <2>; 448 ranges; 449 status = "disabled"; 450 451 uart0: serial@980000 { 452 compatible = "qcom,geni-uart"; 453 reg = <0x0 0x980000 0x0 0x4000>; 454 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 455 clock-names = "se"; 456 pinctrl-0 = <&qup_uart0_default>; 457 pinctrl-names = "default"; 458 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 459 status = "disabled"; 460 }; 461 462 i2c1: i2c@984000 { 463 compatible = "qcom,geni-i2c"; 464 reg = <0x0 0x984000 0x0 0x4000>; 465 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 466 clock-names = "se"; 467 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 468 pinctrl-0 = <&qup_i2c1_data_clk>; 469 pinctrl-names = "default"; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 status = "disabled"; 473 }; 474 475 spi1: spi@984000 { 476 compatible = "qcom,geni-spi"; 477 reg = <0x0 0x984000 0x0 0x4000>; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 481 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 482 clock-names = "se"; 483 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 484 pinctrl-names = "default"; 485 status = "disabled"; 486 }; 487 488 i2c2: i2c@988000 { 489 compatible = "qcom,geni-i2c"; 490 reg = <0x0 0x988000 0x0 0x4000>; 491 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 492 clock-names = "se"; 493 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 494 pinctrl-0 = <&qup_i2c2_data_clk>; 495 pinctrl-names = "default"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 status = "disabled"; 499 }; 500 501 spi2: spi@988000 { 502 compatible = "qcom,geni-spi"; 503 reg = <0x0 0x988000 0x0 0x4000>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 508 clock-names = "se"; 509 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 510 pinctrl-names = "default"; 511 status = "disabled"; 512 }; 513 514 i2c3: i2c@98c000 { 515 compatible = "qcom,geni-i2c"; 516 reg = <0x0 0x98c000 0x0 0x4000>; 517 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 518 clock-names = "se"; 519 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 520 pinctrl-0 = <&qup_i2c3_data_clk>; 521 pinctrl-names = "default"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 status = "disabled"; 525 }; 526 527 spi3: spi@98c000 { 528 compatible = "qcom,geni-spi"; 529 reg = <0x0 0x98c000 0x0 0x4000>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 534 clock-names = "se"; 535 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 536 pinctrl-names = "default"; 537 status = "disabled"; 538 }; 539 540 i2c4: i2c@990000 { 541 compatible = "qcom,geni-i2c"; 542 reg = <0x0 0x990000 0x0 0x4000>; 543 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 544 clock-names = "se"; 545 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 546 pinctrl-0 = <&qup_i2c4_data_clk>; 547 pinctrl-names = "default"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 status = "disabled"; 551 }; 552 553 spi4: spi@990000 { 554 compatible = "qcom,geni-spi"; 555 reg = <0x0 0x990000 0x0 0x4000>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 560 clock-names = "se"; 561 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 562 pinctrl-names = "default"; 563 status = "disabled"; 564 }; 565 566 i2c5: i2c@994000 { 567 compatible = "qcom,geni-i2c"; 568 reg = <0x0 0x994000 0x0 0x4000>; 569 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 570 clock-names = "se"; 571 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 572 pinctrl-0 = <&qup_i2c5_data_clk>; 573 pinctrl-names = "default"; 574 #address-cells = <1>; 575 #size-cells = <0>; 576 status = "disabled"; 577 }; 578 579 spi5: spi@994000 { 580 compatible = "qcom,geni-spi"; 581 reg = <0x0 0x994000 0x0 0x4000>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 586 clock-names = "se"; 587 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 588 pinctrl-names = "default"; 589 status = "disabled"; 590 }; 591 592 i2c6: i2c@998000 { 593 compatible = "qcom,geni-i2c"; 594 reg = <0x0 0x998000 0x0 0x4000>; 595 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 596 clock-names = "se"; 597 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 598 pinctrl-0 = <&qup_i2c6_data_clk>; 599 pinctrl-names = "default"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 status = "disabled"; 603 }; 604 605 spi6: spi@998000 { 606 compatible = "qcom,geni-spi"; 607 reg = <0x0 0x998000 0x0 0x4000>; 608 #address-cells = <1>; 609 #size-cells = <0>; 610 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 611 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 612 clock-names = "se"; 613 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 614 pinctrl-names = "default"; 615 status = "disabled"; 616 }; 617 618 uart7: serial@99c000 { 619 compatible = "qcom,geni-debug-uart"; 620 reg = <0x0 0x99c000 0x0 0x4000>; 621 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 622 clock-names = "se"; 623 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 624 pinctrl-names = "default"; 625 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 626 status = "disabled"; 627 }; 628 }; 629 630 gpi_dma1: dma-controller@a00000 { 631 compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; 632 reg = <0x0 0xa00000 0x0 0x60000>; 633 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 634 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 645 dma-channels = <12>; 646 dma-channel-mask = <0x3f>; 647 iommus = <&apps_smmu 0x116 0x0>; 648 #dma-cells = <3>; 649 }; 650 651 qupv3_id_1: geniqup@ac0000 { 652 compatible = "qcom,geni-se-qup"; 653 reg = <0x0 0xac0000 0x0 0x2000>; 654 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 655 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 656 clock-names = "m-ahb", "s-ahb"; 657 iommus = <&apps_smmu 0x103 0x0>; 658 #address-cells = <2>; 659 #size-cells = <2>; 660 ranges; 661 status = "disabled"; 662 663 uart8: serial@a80000 { 664 compatible = "qcom,geni-uart"; 665 reg = <0x0 0xa80000 0x0 0x4000>; 666 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 667 clock-names = "se"; 668 pinctrl-0 = <&qup_uart8_default>; 669 pinctrl-names = "default"; 670 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 status = "disabled"; 674 }; 675 676 i2c9: i2c@a84000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0x0 0xa84000 0x0 0x4000>; 679 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 680 clock-names = "se"; 681 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 682 pinctrl-0 = <&qup_i2c9_data_clk>; 683 pinctrl-names = "default"; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 spi9: spi@a84000 { 690 compatible = "qcom,geni-spi"; 691 reg = <0x0 0xa84000 0x0 0x4000>; 692 #address-cells = <1>; 693 #size-cells = <0>; 694 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 696 clock-names = "se"; 697 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 698 pinctrl-names = "default"; 699 status = "disabled"; 700 }; 701 702 i2c10: i2c@a88000 { 703 compatible = "qcom,geni-i2c"; 704 reg = <0x0 0xa88000 0x0 0x4000>; 705 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 706 clock-names = "se"; 707 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 708 pinctrl-0 = <&qup_i2c10_data_clk>; 709 pinctrl-names = "default"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 status = "disabled"; 713 }; 714 715 spi10: spi@a88000 { 716 compatible = "qcom,geni-spi"; 717 reg = <0x0 0xa88000 0x0 0x4000>; 718 #address-cells = <1>; 719 #size-cells = <0>; 720 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 722 clock-names = "se"; 723 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 724 pinctrl-names = "default"; 725 status = "disabled"; 726 }; 727 728 i2c11: i2c@a8c000 { 729 compatible = "qcom,geni-i2c"; 730 reg = <0x0 0xa8c000 0x0 0x4000>; 731 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 732 clock-names = "se"; 733 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 734 pinctrl-0 = <&qup_i2c11_data_clk>; 735 pinctrl-names = "default"; 736 #address-cells = <1>; 737 #size-cells = <0>; 738 status = "disabled"; 739 }; 740 741 spi11: spi@a8c000 { 742 compatible = "qcom,geni-spi"; 743 reg = <0x0 0xa8c000 0x0 0x4000>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 747 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 748 clock-names = "se"; 749 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 750 pinctrl-names = "default"; 751 status = "disabled"; 752 }; 753 754 i2c12: i2c@a90000 { 755 compatible = "qcom,geni-i2c"; 756 reg = <0x0 0xa90000 0x0 0x4000>; 757 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 758 clock-names = "se"; 759 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 760 pinctrl-0 = <&qup_i2c12_data_clk>; 761 pinctrl-names = "default"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 status = "disabled"; 765 }; 766 767 spi12: spi@a90000 { 768 compatible = "qcom,geni-spi"; 769 reg = <0x0 0xa90000 0x0 0x4000>; 770 #address-cells = <1>; 771 #size-cells = <0>; 772 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 773 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 774 clock-names = "se"; 775 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 776 pinctrl-names = "default"; 777 status = "disabled"; 778 }; 779 780 i2c13: i2c@a94000 { 781 compatible = "qcom,geni-i2c"; 782 reg = <0x0 0xa94000 0x0 0x4000>; 783 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 784 clock-names = "se"; 785 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 786 pinctrl-0 = <&qup_i2c13_data_clk>; 787 pinctrl-names = "default"; 788 #address-cells = <1>; 789 #size-cells = <0>; 790 status = "disabled"; 791 }; 792 793 uart13: serial@a94000 { 794 compatible = "qcom,geni-uart"; 795 reg = <0x0 0xa94000 0x0 0x4000>; 796 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 797 clock-names = "se"; 798 pinctrl-0 = <&qup_uart13_default>; 799 pinctrl-names = "default"; 800 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 801 #address-cells = <1>; 802 #size-cells = <0>; 803 status = "disabled"; 804 }; 805 806 spi13: spi@a94000 { 807 compatible = "qcom,geni-spi"; 808 reg = <0x0 0xa94000 0x0 0x4000>; 809 #address-cells = <1>; 810 #size-cells = <0>; 811 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 813 clock-names = "se"; 814 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 815 pinctrl-names = "default"; 816 status = "disabled"; 817 }; 818 819 i2c14: i2c@a98000 { 820 compatible = "qcom,geni-i2c"; 821 reg = <0x0 0xa98000 0x0 0x4000>; 822 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 823 clock-names = "se"; 824 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 825 pinctrl-0 = <&qup_i2c14_data_clk>; 826 pinctrl-names = "default"; 827 #address-cells = <1>; 828 #size-cells = <0>; 829 status = "disabled"; 830 }; 831 832 spi14: spi@a98000 { 833 compatible = "qcom,geni-spi"; 834 reg = <0x0 0xa98000 0x0 0x4000>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 839 clock-names = "se"; 840 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 841 pinctrl-names = "default"; 842 status = "disabled"; 843 }; 844 845 i2c15: i2c@a9c000 { 846 compatible = "qcom,geni-i2c"; 847 reg = <0x0 0xa9c000 0x0 0x4000>; 848 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 849 clock-names = "se"; 850 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 851 pinctrl-0 = <&qup_i2c15_data_clk>; 852 pinctrl-names = "default"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 status = "disabled"; 856 }; 857 858 spi15: spi@a9c000 { 859 compatible = "qcom,geni-spi"; 860 reg = <0x0 0xa9c000 0x0 0x4000>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 interrupts = <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 865 clock-names = "se"; 866 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 867 pinctrl-names = "default"; 868 status = "disabled"; 869 }; 870 }; 871 872 system_noc: interconnect@1640000 { 873 compatible = "qcom,qdu1000-system-noc"; 874 reg = <0x0 0x1640000 0x0 0x45080>; 875 qcom,bcm-voters = <&apps_bcm_voter>; 876 #interconnect-cells = <2>; 877 }; 878 879 tcsr_mutex: hwlock@1f40000 { 880 compatible = "qcom,tcsr-mutex"; 881 reg = <0x0 0x1f40000 0x0 0x20000>; 882 #hwlock-cells = <1>; 883 }; 884 885 sdhc: mmc@8804000 { 886 compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5"; 887 reg = <0x0 0x08804000 0x0 0x1000>, 888 <0x0 0x08805000 0x0 0x1000>; 889 reg-names = "hc", "cqhci"; 890 891 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 893 interrupt-names = "hc_irq", "pwr_irq"; 894 895 clocks = <&gcc GCC_SDCC5_AHB_CLK>, 896 <&gcc GCC_SDCC5_APPS_CLK>, 897 <&rpmhcc RPMH_CXO_CLK>; 898 clock-names = "iface", 899 "core", 900 "xo"; 901 902 resets = <&gcc GCC_SDCC5_BCR>; 903 904 interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 905 <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>; 906 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 907 power-domains = <&rpmhpd QDU1000_CX>; 908 operating-points-v2 = <&sdhc1_opp_table>; 909 910 iommus = <&apps_smmu 0x80 0x0>; 911 dma-coherent; 912 913 bus-width = <8>; 914 915 qcom,dll-config = <0x0007642c>; 916 qcom,ddr-config = <0x80040868>; 917 918 status = "disabled"; 919 920 sdhc1_opp_table: opp-table { 921 compatible = "operating-points-v2"; 922 923 opp-384000000 { 924 opp-hz = /bits/ 64 <384000000>; 925 required-opps = <&rpmhpd_opp_nom>; 926 opp-peak-kBps = <6528000 1652800>; 927 opp-avg-kBps = <400000 0>; 928 }; 929 }; 930 }; 931 932 usb_1_hsphy: phy@88e3000 { 933 compatible = "qcom,qdu1000-usb-hs-phy", 934 "qcom,usb-snps-hs-7nm-phy"; 935 reg = <0x0 0x088e3000 0x0 0x120>; 936 #phy-cells = <0>; 937 938 clocks = <&gcc GCC_USB2_CLKREF_EN>; 939 clock-names = "ref"; 940 941 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 942 943 status = "disabled"; 944 }; 945 946 usb_1_qmpphy: phy@88e5000 { 947 compatible = "qcom,qdu1000-qmp-usb3-uni-phy"; 948 reg = <0x0 0x088e5000 0x0 0x2000>; 949 950 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 951 <&gcc GCC_USB2_CLKREF_EN>, 952 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 953 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 954 clock-names = "aux", 955 "ref", 956 "com_aux", 957 "pipe"; 958 959 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 960 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 961 reset-names = "phy", 962 "phy_phy"; 963 964 #clock-cells = <0>; 965 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 966 967 #phy-cells = <0>; 968 969 status = "disabled"; 970 }; 971 972 usb_1: usb@a6f8800 { 973 compatible = "qcom,qdu1000-dwc3", "qcom,dwc3"; 974 reg = <0 0x0a6f8800 0 0x400>; 975 #address-cells = <2>; 976 #size-cells = <2>; 977 ranges; 978 979 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 980 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 981 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 982 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 983 clock-names = "cfg_noc", 984 "core", 985 "sleep", 986 "mock_utmi"; 987 988 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 989 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 990 assigned-clock-rates = <19200000>, <200000000>; 991 992 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 993 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 994 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 995 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 996 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-names = "pwr_event", 998 "hs_phy_irq", 999 "dp_hs_phy_irq", 1000 "dm_hs_phy_irq", 1001 "ss_phy_irq"; 1002 1003 power-domains = <&gcc USB30_PRIM_GDSC>; 1004 required-opps = <&rpmhpd_opp_nom>; 1005 1006 resets = <&gcc GCC_USB30_PRIM_BCR>; 1007 1008 interconnects = <&system_noc MASTER_USB3 QCOM_ICC_TAG_ALWAYS 1009 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1010 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1011 &system_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 1012 1013 interconnect-names = "usb-ddr", 1014 "apps-usb"; 1015 1016 status = "disabled"; 1017 1018 usb_1_dwc3: usb@a600000 { 1019 compatible = "snps,dwc3"; 1020 reg = <0 0x0a600000 0 0xcd00>; 1021 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1022 1023 iommus = <&apps_smmu 0xc0 0x0>; 1024 snps,dis_u2_susphy_quirk; 1025 snps,dis_enblslpm_quirk; 1026 snps,dis-u1-entry-quirk; 1027 snps,dis-u2-entry-quirk; 1028 phys = <&usb_1_hsphy>, 1029 <&usb_1_qmpphy>; 1030 phy-names = "usb2-phy", 1031 "usb3-phy"; 1032 1033 ports { 1034 #address-cells = <1>; 1035 #size-cells = <0>; 1036 1037 port@0 { 1038 reg = <0>; 1039 1040 usb_1_dwc3_hs: endpoint { 1041 }; 1042 }; 1043 1044 port@1 { 1045 reg = <1>; 1046 1047 usb_1_dwc3_ss: endpoint { 1048 }; 1049 }; 1050 }; 1051 }; 1052 }; 1053 1054 pdc: interrupt-controller@b220000 { 1055 compatible = "qcom,qdu1000-pdc", "qcom,pdc"; 1056 reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>; 1057 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>, 1058 <94 609 31>, <125 63 1>; 1059 #interrupt-cells = <2>; 1060 interrupt-parent = <&intc>; 1061 interrupt-controller; 1062 }; 1063 1064 spmi_bus: spmi@c400000 { 1065 compatible = "qcom,spmi-pmic-arb"; 1066 reg = <0x0 0xc400000 0x0 0x3000>, 1067 <0x0 0xc500000 0x0 0x400000>, 1068 <0x0 0xc440000 0x0 0x80000>, 1069 <0x0 0xc4c0000 0x0 0x10000>, 1070 <0x0 0xc42d000 0x0 0x4000>; 1071 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1072 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 1073 interrupt-names = "periph_irq"; 1074 qcom,ee = <0>; 1075 qcom,channel = <0>; 1076 #address-cells = <2>; 1077 #size-cells = <0>; 1078 interrupt-controller; 1079 #interrupt-cells = <4>; 1080 }; 1081 1082 tlmm: pinctrl@f000000 { 1083 compatible = "qcom,qdu1000-tlmm"; 1084 reg = <0x0 0xf000000 0x0 0x1000000>; 1085 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1086 gpio-controller; 1087 #gpio-cells = <2>; 1088 interrupt-controller; 1089 #interrupt-cells = <2>; 1090 gpio-ranges = <&tlmm 0 0 151>; 1091 wakeup-parent = <&pdc>; 1092 1093 qup_uart0_default: qup-uart0-default-state { 1094 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 1095 function = "qup00"; 1096 }; 1097 1098 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1099 pins = "gpio10", "gpio11"; 1100 function = "qup01"; 1101 }; 1102 1103 qup_spi1_data_clk: qup-spi1-data-clk-state { 1104 pins = "gpio10", "gpio11", "gpio12"; 1105 function = "qup01"; 1106 }; 1107 1108 qup_spi1_cs: qup-spi1-cs-state { 1109 pins = "gpio13"; 1110 function = "gpio"; 1111 }; 1112 1113 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1114 pins = "gpio12", "gpio13"; 1115 function = "qup02"; 1116 }; 1117 1118 qup_spi2_data_clk: qup-spi2-data-clk-state { 1119 pins = "gpio12", "gpio13", "gpio10"; 1120 function = "qup02"; 1121 }; 1122 1123 qup_spi2_cs: qup-spi2-cs-state { 1124 pins = "gpio11"; 1125 function = "gpio"; 1126 }; 1127 1128 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1129 pins = "gpio14", "gpio15"; 1130 function = "qup03"; 1131 }; 1132 1133 qup_spi3_data_clk: qup-spi3-data-clk-state { 1134 pins = "gpio14", "gpio15", "gpio16"; 1135 function = "qup03"; 1136 }; 1137 1138 qup_spi3_cs: qup-spi3-cs-state { 1139 pins = "gpio17"; 1140 function = "gpio"; 1141 }; 1142 1143 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1144 pins = "gpio16", "gpio17"; 1145 function = "qup04"; 1146 }; 1147 1148 qup_spi4_data_clk: qup-spi4-data-clk-state { 1149 pins = "gpio16", "gpio17", "gpio14"; 1150 function = "qup04"; 1151 }; 1152 1153 qup_spi4_cs: qup-spi4-cs-state { 1154 pins = "gpio15"; 1155 function = "gpio"; 1156 }; 1157 1158 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1159 pins = "gpio130", "gpio131"; 1160 function = "qup05"; 1161 }; 1162 1163 qup_spi5_data_clk: qup-spi5-data-clk-state { 1164 pins = "gpio130", "gpio131", "gpio132"; 1165 function = "qup05"; 1166 }; 1167 1168 qup_spi5_cs: qup-spi5-cs-state { 1169 pins = "gpio133"; 1170 function = "gpio"; 1171 }; 1172 1173 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1174 pins = "gpio132", "gpio133"; 1175 function = "qup06"; 1176 }; 1177 1178 qup_spi6_data_clk: qup-spi6-data-clk-state { 1179 pins = "gpio132", "gpio133", "gpio130"; 1180 function = "qup06"; 1181 }; 1182 1183 qup_spi6_cs: qup-spi6-cs-state { 1184 pins = "gpio131"; 1185 function = "gpio"; 1186 }; 1187 1188 qup_uart7_rx: qup-uart7-rx-state { 1189 pins = "gpio135"; 1190 function = "qup07"; 1191 }; 1192 1193 qup_uart7_tx: qup-uart7-tx-state { 1194 pins = "gpio134"; 1195 function = "qup07"; 1196 }; 1197 1198 qup_uart8_default: qup-uart8-default-state { 1199 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 1200 function = "qup10"; 1201 }; 1202 1203 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 1204 pins = "gpio22", "gpio23"; 1205 function = "qup11"; 1206 }; 1207 1208 qup_spi9_data_clk: qup-spi9-data-clk-state { 1209 pins = "gpio22", "gpio23", "gpio24"; 1210 function = "qup11"; 1211 }; 1212 1213 qup_spi9_cs: qup-spi9-cs-state { 1214 pins = "gpio25"; 1215 function = "gpio"; 1216 }; 1217 1218 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 1219 pins = "gpio24", "gpio25"; 1220 function = "qup12"; 1221 }; 1222 1223 qup_spi10_data_clk: qup-spi10-data-clk-state { 1224 pins = "gpio24", "gpio25", "gpio22"; 1225 function = "qup12"; 1226 }; 1227 1228 qup_spi10_cs: qup-spi10-cs-state { 1229 pins = "gpio23"; 1230 function = "gpio"; 1231 }; 1232 1233 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 1234 pins = "gpio26", "gpio27"; 1235 function = "qup13"; 1236 }; 1237 1238 qup_spi11_data_clk: qup-spi11-data-clk-state { 1239 pins = "gpio26", "gpio27", "gpio28"; 1240 function = "qup13"; 1241 }; 1242 1243 qup_spi11_cs: qup-spi11-cs-state { 1244 pins = "gpio29"; 1245 function = "gpio"; 1246 }; 1247 1248 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 1249 pins = "gpio28", "gpio29"; 1250 function = "qup14"; 1251 }; 1252 1253 qup_spi12_data_clk: qup-spi12-data-clk-state { 1254 pins = "gpio28", "gpio29", "gpio26"; 1255 function = "qup14"; 1256 }; 1257 1258 qup_spi12_cs: qup-spi12-cs-state { 1259 pins = "gpio27"; 1260 function = "gpio"; 1261 }; 1262 1263 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 1264 pins = "gpio30", "gpio31"; 1265 function = "qup15"; 1266 }; 1267 1268 qup_spi13_data_clk: qup-spi13-data-clk-state { 1269 pins = "gpio30", "gpio31", "gpio32"; 1270 function = "qup15"; 1271 }; 1272 1273 qup_spi13_cs: qup-spi13-cs-state { 1274 pins = "gpio33"; 1275 function = "gpio"; 1276 }; 1277 1278 qup_uart13_default: qup-uart13-default-state { 1279 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 1280 function = "qup15"; 1281 }; 1282 1283 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 1284 pins = "gpio34", "gpio35"; 1285 function = "qup16"; 1286 }; 1287 1288 qup_spi14_data_clk: qup-spi14-data-clk-state { 1289 pins = "gpio34", "gpio35", "gpio36"; 1290 function = "qup16"; 1291 }; 1292 1293 qup_spi14_cs: qup-spi14-cs-state { 1294 pins = "gpio37", "gpio38"; 1295 function = "gpio"; 1296 }; 1297 1298 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 1299 pins = "gpio40", "gpio41"; 1300 function = "qup17"; 1301 }; 1302 1303 qup_spi15_data_clk: qup-spi15-data-clk-state { 1304 pins = "gpio40", "gpio41", "gpio30"; 1305 function = "qup17"; 1306 }; 1307 1308 qup_spi15_cs: qup-spi15-cs-state { 1309 pins = "gpio31"; 1310 function = "gpio"; 1311 }; 1312 1313 sdc_on_state: sdc-on-state { 1314 clk-pins { 1315 pins = "sdc1_clk"; 1316 drive-strength = <16>; 1317 bias-disable; 1318 }; 1319 1320 cmd-pins { 1321 pins = "sdc1_cmd"; 1322 drive-strength = <10>; 1323 bias-pull-up; 1324 }; 1325 1326 data-pins { 1327 pins = "sdc1_data"; 1328 drive-strength = <10>; 1329 bias-pull-up; 1330 }; 1331 1332 rclk-pins { 1333 pins = "sdc1_rclk"; 1334 bias-pull-down; 1335 }; 1336 }; 1337 1338 sdc_off_state: sdc-off-state { 1339 clk-pins { 1340 pins = "sdc1_clk"; 1341 drive-strength = <2>; 1342 bias-disable; 1343 }; 1344 1345 cmd-pins { 1346 pins = "sdc1_cmd"; 1347 drive-strength = <2>; 1348 bias-pull-up; 1349 }; 1350 1351 data-pins { 1352 pins = "sdc1_data"; 1353 drive-strength = <2>; 1354 bias-pull-up; 1355 }; 1356 1357 rclk-pins { 1358 pins = "sdc1_rclk"; 1359 bias-pull-down; 1360 }; 1361 }; 1362 }; 1363 1364 sram@14680000 { 1365 compatible = "qcom,qdu1000-imem", "syscon", "simple-mfd"; 1366 reg = <0 0x14680000 0 0x1000>; 1367 ranges = <0 0 0x14680000 0x1000>; 1368 #address-cells = <1>; 1369 #size-cells = <1>; 1370 1371 pil-reloc@94c { 1372 compatible = "qcom,pil-reloc-info"; 1373 reg = <0x94c 0xc8>; 1374 }; 1375 }; 1376 1377 apps_smmu: iommu@15000000 { 1378 compatible = "qcom,qdu1000-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1379 reg = <0x0 0x15000000 0x0 0x100000>; 1380 #iommu-cells = <2>; 1381 #global-interrupts = <2>; 1382 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 1384 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1385 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1386 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1387 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1388 <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>, 1389 <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 1390 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1391 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1392 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1393 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1394 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1395 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1398 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1399 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1400 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1401 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1402 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1403 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1404 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1405 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1406 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1407 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1410 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1412 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1413 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1414 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1415 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1416 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1417 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1418 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1419 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1420 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1421 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1422 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1423 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1424 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1425 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1426 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1427 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1428 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1429 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1430 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 1431 dma-coherent; 1432 }; 1433 1434 intc: interrupt-controller@17200000 { 1435 compatible = "arm,gic-v3"; 1436 reg = <0x0 0x17200000 0x0 0x10000>, /* GICD */ 1437 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */ 1438 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1439 #interrupt-cells = <3>; 1440 interrupt-controller; 1441 #redistributor-regions = <1>; 1442 redistributor-stride = <0x0 0x20000>; 1443 }; 1444 1445 timer@17420000 { 1446 compatible = "arm,armv7-timer-mem"; 1447 reg = <0x0 0x17420000 0x0 0x1000>; 1448 #address-cells = <1>; 1449 #size-cells = <1>; 1450 ranges = <0x0 0x0 0x0 0x20000000>; 1451 1452 frame@17421000 { 1453 reg = <0x17421000 0x1000>, 1454 <0x17422000 0x1000>; 1455 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1457 frame-number = <0>; 1458 }; 1459 1460 frame@17423000 { 1461 reg = <0x17423000 0x1000>; 1462 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1463 frame-number = <1>; 1464 status = "disabled"; 1465 }; 1466 1467 frame@17425000 { 1468 reg = <0x17425000 0x1000>, 1469 <0x17426000 0x1000>; 1470 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1471 frame-number = <2>; 1472 status = "disabled"; 1473 }; 1474 1475 frame@17427000 { 1476 reg = <0x17427000 0x1000>; 1477 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1478 frame-number = <3>; 1479 status = "disabled"; 1480 }; 1481 1482 frame@17429000 { 1483 reg = <0x17429000 0x1000>; 1484 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1485 frame-number = <4>; 1486 status = "disabled"; 1487 }; 1488 1489 frame@1742b000 { 1490 reg = <0x1742b000 0x1000>; 1491 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1492 frame-number = <5>; 1493 status = "disabled"; 1494 }; 1495 1496 frame@1742d000 { 1497 reg = <0x1742d000 0x1000>; 1498 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1499 frame-number = <6>; 1500 status = "disabled"; 1501 }; 1502 }; 1503 1504 apps_rsc: rsc@17a00000 { 1505 compatible = "qcom,rpmh-rsc"; 1506 reg = <0x0 0x17a00000 0x0 0x10000>, 1507 <0x0 0x17a10000 0x0 0x10000>, 1508 <0x0 0x17a20000 0x0 0x10000>; 1509 reg-names = "drv-0", "drv-1", "drv-2"; 1510 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1511 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 1512 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1513 qcom,tcs-offset = <0xd00>; 1514 qcom,drv-id = <2>; 1515 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>, 1516 <WAKE_TCS 3>, <CONTROL_TCS 0>; 1517 label = "apps_rsc"; 1518 power-domains = <&cluster_pd>; 1519 1520 apps_bcm_voter: bcm-voter { 1521 compatible = "qcom,bcm-voter"; 1522 }; 1523 1524 rpmhcc: clock-controller { 1525 compatible = "qcom,qdu1000-rpmh-clk"; 1526 clocks = <&xo_board>; 1527 clock-names = "xo"; 1528 #clock-cells = <1>; 1529 }; 1530 1531 rpmhpd: power-controller { 1532 compatible = "qcom,qdu1000-rpmhpd"; 1533 #power-domain-cells = <1>; 1534 operating-points-v2 = <&rpmhpd_opp_table>; 1535 1536 rpmhpd_opp_table: opp-table { 1537 compatible = "operating-points-v2"; 1538 1539 rpmhpd_opp_ret: opp1 { 1540 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1541 }; 1542 1543 rpmhpd_opp_min_svs: opp2 { 1544 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1545 }; 1546 1547 rpmhpd_opp_low_svs: opp3 { 1548 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1549 }; 1550 1551 rpmhpd_opp_svs: opp4 { 1552 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1553 }; 1554 1555 rpmhpd_opp_svs_l1: opp5 { 1556 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1557 }; 1558 1559 rpmhpd_opp_nom: opp6 { 1560 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1561 }; 1562 1563 rpmhpd_opp_nom_l1: opp7 { 1564 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1565 }; 1566 1567 rpmhpd_opp_nom_l2: opp8 { 1568 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1569 }; 1570 1571 rpmhpd_opp_turbo: opp9 { 1572 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1573 }; 1574 1575 rpmhpd_opp_turbo_l1: opp10 { 1576 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1577 }; 1578 }; 1579 }; 1580 }; 1581 1582 cpufreq_hw: cpufreq@17d90000 { 1583 compatible = "qcom,qdu1000-cpufreq-epss", "qcom,cpufreq-epss"; 1584 reg = <0x0 0x17d90000 0x0 0x1000>, <0x0 0x17d91000 0x0 0x1000>; 1585 reg-names = "freq-domain0", "freq-domain1"; 1586 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 1587 clock-names = "xo", "alternate"; 1588 #freq-domain-cells = <1>; 1589 #clock-cells = <1>; 1590 }; 1591 1592 gem_noc: interconnect@19100000 { 1593 compatible = "qcom,qdu1000-gem-noc"; 1594 reg = <0x0 0x19100000 0x0 0xB8080>; 1595 qcom,bcm-voters = <&apps_bcm_voter>; 1596 #interconnect-cells = <2>; 1597 }; 1598 1599 system-cache-controller@19200000 { 1600 compatible = "qcom,qdu1000-llcc"; 1601 reg = <0 0x19200000 0 0x80000>, 1602 <0 0x19300000 0 0x80000>, 1603 <0 0x19600000 0 0x80000>, 1604 <0 0x19700000 0 0x80000>, 1605 <0 0x19a00000 0 0x80000>, 1606 <0 0x19b00000 0 0x80000>, 1607 <0 0x19e00000 0 0x80000>, 1608 <0 0x19f00000 0 0x80000>, 1609 <0 0x1a200000 0 0x80000>; 1610 reg-names = "llcc0_base", 1611 "llcc1_base", 1612 "llcc2_base", 1613 "llcc3_base", 1614 "llcc4_base", 1615 "llcc5_base", 1616 "llcc6_base", 1617 "llcc7_base", 1618 "llcc_broadcast_base"; 1619 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1620 1621 nvmem-cells = <&multi_chan_ddr>; 1622 nvmem-cell-names = "multi-chan-ddr"; 1623 }; 1624 1625 sec_qfprom: efuse@221c8000 { 1626 compatible = "qcom,qdu1000-sec-qfprom", "qcom,sec-qfprom"; 1627 reg = <0 0x221c8000 0 0x1000>; 1628 #address-cells = <1>; 1629 #size-cells = <1>; 1630 1631 multi_chan_ddr: multi-chan-ddr@12b { 1632 reg = <0x12b 0x1>; 1633 bits = <0 2>; 1634 }; 1635 }; 1636 }; 1637 1638 timer { 1639 compatible = "arm,armv8-timer"; 1640 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1641 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1642 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1643 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1644 <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1645 }; 1646}; 1647